1 //=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64r6 instructions.
12 //===----------------------------------------------------------------------===//
14 // Notes about removals/changes from MIPS32r6:
15 // Reencoded: dclo, dclz
17 //===----------------------------------------------------------------------===//
19 // Instruction Encodings
21 //===----------------------------------------------------------------------===//
23 class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
24 class DAUI_ENC : DAUI_FM;
25 class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
26 class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
27 class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
28 class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
29 class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
30 class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
31 class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
32 class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
33 class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
34 class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
35 class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b011100>;
36 class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>;
37 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
38 class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
39 class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;
40 class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
41 class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
43 //===----------------------------------------------------------------------===//
45 // Instruction Descriptions
47 //===----------------------------------------------------------------------===//
49 class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
50 dag OutOperandList = (outs GPROpnd:$rs);
51 dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm);
52 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
53 string Constraints = "$rs = $rt";
54 InstrItinClass Itinerary = itin;
57 class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
58 class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
59 class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
60 class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
61 class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
62 class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
63 class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
64 class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
65 class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
66 class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
67 class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
68 class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
69 class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
70 class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
71 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
72 class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
73 class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
74 class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm16, II_LLD>;
75 class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
76 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
77 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
79 class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
82 list<Register> Defs = [RA];
85 class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
88 list<Register> Defs = [AT];
91 class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
92 class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
93 //===----------------------------------------------------------------------===//
95 // Instruction Definitions
97 //===----------------------------------------------------------------------===//
99 let AdditionalPredicates = [NotInMicroMips] in {
100 def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
101 def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
102 def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
103 def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
105 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
106 let AdditionalPredicates = [NotInMicroMips] in {
107 def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
108 def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
109 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
110 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
111 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
112 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
114 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
115 let AdditionalPredicates = [NotInMicroMips] in {
116 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
117 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
118 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
119 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
120 def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
122 def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
123 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
124 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
125 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
126 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
128 let AdditionalPredicates = [NotInMicroMips],
129 DecoderNamespace = "Mips32r6_64r6_PTR64" in {
130 def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
131 def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
133 let isCodeGenOnly = 1 in {
134 def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
135 def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
137 //===----------------------------------------------------------------------===//
139 // Instruction Aliases
141 //===----------------------------------------------------------------------===//
143 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
145 def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
147 def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
148 //===----------------------------------------------------------------------===//
150 // Patterns and Pseudo Instructions
152 //===----------------------------------------------------------------------===//
155 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
156 (OR64 (SELNEZ64 i64:$t, i64:$cond),
157 (SELEQZ64 i64:$f, i64:$cond))>,
159 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
160 (OR64 (SELEQZ64 i64:$t, i64:$cond),
161 (SELNEZ64 i64:$f, i64:$cond))>,
163 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
164 (OR64 (SELNEZ64 i64:$t, i64:$cond),
165 (SELEQZ64 i64:$f, i64:$cond))>,
167 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
168 (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
169 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
171 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
172 (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
173 (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
176 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
177 (OR64 (SELEQZ64 i64:$t,
178 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
181 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
185 (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
186 (OR64 (SELEQZ64 i64:$t,
187 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
190 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
194 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
195 (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
196 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
197 (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
198 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
199 (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
200 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
201 (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
203 // i64 selects from an i32 comparison
204 // One complicating factor here is that bits 32-63 of an i32 are undefined.
205 // FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
206 // This would allow us to remove the sign-extensions here.
207 def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
208 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
209 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
211 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
212 (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
213 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
215 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
216 (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
217 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
219 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
220 (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
222 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
225 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
226 (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
228 (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
232 def : MipsPat<(select i32:$cond, i64:$t, immz),
233 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
235 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
236 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
238 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
239 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
241 def : MipsPat<(select i32:$cond, immz, i64:$f),
242 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
244 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
245 (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
247 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
248 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,