1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetMachine.h"
23 #include "MipsTargetStreamer.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/IR/BasicBlock.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/Mangler.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCSectionELF.h"
44 #include "llvm/MC/MCSymbolELF.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "mips-asm-printer"
56 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
57 return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
60 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
61 Subtarget = &MF.getSubtarget<MipsSubtarget>();
63 // Initialize TargetLoweringObjectFile.
64 const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
65 .Initialize(OutContext, TM);
67 MipsFI = MF.getInfo<MipsFunctionInfo>();
68 if (Subtarget->inMips16Mode())
71 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
72 it = MipsFI->StubsNeeded.begin();
73 it != MipsFI->StubsNeeded.end(); ++it) {
74 const char *Symbol = it->first;
75 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
76 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
77 StubsNeeded[Symbol] = Signature;
79 MCP = MF.getConstantPool();
81 // In NaCl, all indirect jump targets must be aligned to bundle size.
82 if (Subtarget->isTargetNaCl())
83 NaClAlignIndirectJumpTargets(MF);
85 AsmPrinter::runOnMachineFunction(MF);
89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
90 MCOp = MCInstLowering.LowerOperand(MO);
91 return MCOp.isValid();
94 #include "MipsGenMCPseudoLowering.inc"
96 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
97 // JALR, or JALR64 as appropriate for the target
98 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
99 const MachineInstr *MI) {
100 bool HasLinkReg = false;
103 if (Subtarget->hasMips64r6()) {
104 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
105 TmpInst0.setOpcode(Mips::JALR64);
107 } else if (Subtarget->hasMips32r6()) {
108 // MIPS32r6 should use (JALR ZERO, $rs)
109 TmpInst0.setOpcode(Mips::JALR);
111 } else if (Subtarget->inMicroMipsMode())
112 // microMIPS should use (JR_MM $rs)
113 TmpInst0.setOpcode(Mips::JR_MM);
115 // Everything else should use (JR $rs)
116 TmpInst0.setOpcode(Mips::JR);
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
126 lowerOperand(MI->getOperand(0), MCOp);
127 TmpInst0.addOperand(MCOp);
129 EmitToStreamer(OutStreamer, TmpInst0);
132 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
133 MipsTargetStreamer &TS = getTargetStreamer();
134 TS.forbidModuleDirective();
136 if (MI->isDebugValue()) {
137 SmallString<128> Str;
138 raw_svector_ostream OS(Str);
140 PrintDebugValueComment(MI, OS);
144 // If we just ended a constant pool, mark it as such.
145 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
146 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
147 InConstantPool = false;
149 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
150 // CONSTPOOL_ENTRY - This instruction represents a floating
151 //constant pool in the function. The first operand is the ID#
152 // for this instruction, the second is the index into the
153 // MachineConstantPool that this is, the third is the size in
154 // bytes of this constant pool entry.
155 // The required alignment is specified on the basic block holding this MI.
157 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
158 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
160 // If this is the first entry of the pool, mark it.
161 if (!InConstantPool) {
162 OutStreamer->EmitDataRegion(MCDR_DataRegion);
163 InConstantPool = true;
166 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
168 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
169 if (MCPE.isMachineConstantPoolEntry())
170 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
172 EmitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal);
177 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
178 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
181 // Do any auto-generated pseudo lowerings.
182 if (emitPseudoExpansionLowering(*OutStreamer, &*I))
185 if (I->getOpcode() == Mips::PseudoReturn ||
186 I->getOpcode() == Mips::PseudoReturn64 ||
187 I->getOpcode() == Mips::PseudoIndirectBranch ||
188 I->getOpcode() == Mips::PseudoIndirectBranch64) {
189 emitPseudoIndirectBranch(*OutStreamer, &*I);
193 // The inMips16Mode() test is not permanent.
194 // Some instructions are marked as pseudo right now which
195 // would make the test fail for the wrong reason but
196 // that will be fixed soon. We need this here because we are
197 // removing another test for this situation downstream in the
200 if (I->isPseudo() && !Subtarget->inMips16Mode()
201 && !isLongBranchPseudo(I->getOpcode()))
202 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
205 MCInstLowering.Lower(&*I, TmpInst0);
206 EmitToStreamer(*OutStreamer, TmpInst0);
207 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
210 //===----------------------------------------------------------------------===//
212 // Mips Asm Directives
214 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
215 // Describe the stack frame.
217 // -- Mask directives "(f)mask bitmask, offset"
218 // Tells the assembler which registers are saved and where.
219 // bitmask - contain a little endian bitset indicating which registers are
220 // saved on function prologue (e.g. with a 0x80000000 mask, the
221 // assembler knows the register 31 (RA) is saved at prologue.
222 // offset - the position before stack pointer subtraction indicating where
223 // the first saved register on prologue is located. (e.g. with a
225 // Consider the following function prologue:
228 // .mask 0xc0000000,-8
229 // addiu $sp, $sp, -48
233 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
234 // 30 (FP) are saved at prologue. As the save order on prologue is from
235 // left to right, RA is saved first. A -8 offset means that after the
236 // stack pointer subtration, the first register in the mask (RA) will be
237 // saved at address 48-8=40.
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
245 // Create a bitmask with all callee saved registers for CPU or Floating Point
246 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
247 void MipsAsmPrinter::printSavedRegsBitmask() {
248 // CPU and FPU Saved Registers Bitmasks
249 unsigned CPUBitmask = 0, FPUBitmask = 0;
250 int CPUTopSavedRegOff, FPUTopSavedRegOff;
252 // Set the CPU and FPU Bitmasks
253 const MachineFrameInfo *MFI = MF->getFrameInfo();
254 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
255 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
256 // size of stack area to which FP callee-saved regs are saved.
257 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
258 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
259 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
260 bool HasAFGR64Reg = false;
261 unsigned CSFPRegsSize = 0;
263 for (const auto &I : CSI) {
264 unsigned Reg = I.getReg();
265 unsigned RegNum = TRI->getEncodingValue(Reg);
267 // If it's a floating point register, set the FPU Bitmask.
268 // If it's a general purpose register, set the CPU Bitmask.
269 if (Mips::FGR32RegClass.contains(Reg)) {
270 FPUBitmask |= (1 << RegNum);
271 CSFPRegsSize += FGR32RegSize;
272 } else if (Mips::AFGR64RegClass.contains(Reg)) {
273 FPUBitmask |= (3 << RegNum);
274 CSFPRegsSize += AFGR64RegSize;
276 } else if (Mips::GPR32RegClass.contains(Reg))
277 CPUBitmask |= (1 << RegNum);
280 // FP Regs are saved right below where the virtual frame pointer points to.
281 FPUTopSavedRegOff = FPUBitmask ?
282 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
284 // CPU Regs are saved below FP Regs.
285 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
287 MipsTargetStreamer &TS = getTargetStreamer();
289 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
292 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
295 //===----------------------------------------------------------------------===//
296 // Frame and Set directives
297 //===----------------------------------------------------------------------===//
300 void MipsAsmPrinter::emitFrameDirective() {
301 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
303 unsigned stackReg = RI.getFrameRegister(*MF);
304 unsigned returnReg = RI.getRARegister();
305 unsigned stackSize = MF->getFrameInfo()->getStackSize();
307 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
310 /// Emit Set directives.
311 const char *MipsAsmPrinter::getCurrentABIString() const {
312 switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
313 case MipsABIInfo::ABI::O32: return "abi32";
314 case MipsABIInfo::ABI::N32: return "abiN32";
315 case MipsABIInfo::ABI::N64: return "abi64";
316 default: llvm_unreachable("Unknown Mips ABI");
320 void MipsAsmPrinter::EmitFunctionEntryLabel() {
321 MipsTargetStreamer &TS = getTargetStreamer();
323 // NaCl sandboxing requires that indirect call instructions are masked.
324 // This means that function entry points should be bundle-aligned.
325 if (Subtarget->isTargetNaCl())
326 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
328 if (Subtarget->inMicroMipsMode()) {
329 TS.emitDirectiveSetMicroMips();
330 TS.setUsesMicroMips();
332 TS.emitDirectiveSetNoMicroMips();
334 if (Subtarget->inMips16Mode())
335 TS.emitDirectiveSetMips16();
337 TS.emitDirectiveSetNoMips16();
339 TS.emitDirectiveEnt(*CurrentFnSym);
340 OutStreamer->EmitLabel(CurrentFnSym);
343 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
344 /// the first basic block in the function.
345 void MipsAsmPrinter::EmitFunctionBodyStart() {
346 MipsTargetStreamer &TS = getTargetStreamer();
348 MCInstLowering.Initialize(&MF->getContext());
350 bool IsNakedFunction = MF->getFunction()->hasFnAttribute(Attribute::Naked);
351 if (!IsNakedFunction)
352 emitFrameDirective();
354 if (!IsNakedFunction)
355 printSavedRegsBitmask();
357 if (!Subtarget->inMips16Mode()) {
358 TS.emitDirectiveSetNoReorder();
359 TS.emitDirectiveSetNoMacro();
360 TS.emitDirectiveSetNoAt();
364 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
365 /// the last basic block in the function.
366 void MipsAsmPrinter::EmitFunctionBodyEnd() {
367 MipsTargetStreamer &TS = getTargetStreamer();
369 // There are instruction for this macros, but they must
370 // always be at the function end, and we can't emit and
371 // break with BB logic.
372 if (!Subtarget->inMips16Mode()) {
373 TS.emitDirectiveSetAt();
374 TS.emitDirectiveSetMacro();
375 TS.emitDirectiveSetReorder();
377 TS.emitDirectiveEnd(CurrentFnSym->getName());
378 // Make sure to terminate any constant pools that were at the end
382 InConstantPool = false;
383 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
386 void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) {
387 MipsTargetStreamer &TS = getTargetStreamer();
389 TS.emitDirectiveInsn();
392 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
393 /// exactly one predecessor and the control transfer mechanism between
394 /// the predecessor and this block is a fall-through.
395 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
397 // The predecessor has to be immediately before this block.
398 const MachineBasicBlock *Pred = *MBB->pred_begin();
400 // If the predecessor is a switch statement, assume a jump table
401 // implementation, so it is not a fall through.
402 if (const BasicBlock *bb = Pred->getBasicBlock())
403 if (isa<SwitchInst>(bb->getTerminator()))
406 // If this is a landing pad, it isn't a fall through. If it has no preds,
407 // then nothing falls through to it.
408 if (MBB->isEHPad() || MBB->pred_empty())
411 // If there isn't exactly one predecessor, it can't be a fall through.
412 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
415 if (PI2 != MBB->pred_end())
418 // The predecessor has to be immediately before this block.
419 if (!Pred->isLayoutSuccessor(MBB))
422 // If the block is completely empty, then it definitely does fall through.
426 // Otherwise, check the last instruction.
427 // Check if the last terminator is an unconditional branch.
428 MachineBasicBlock::const_iterator I = Pred->end();
429 while (I != Pred->begin() && !(--I)->isTerminator()) ;
431 return !I->isBarrier();
434 // Print out an operand for an inline asm expression.
435 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
436 unsigned AsmVariant, const char *ExtraCode,
438 // Does this asm operand have a single letter operand modifier?
439 if (ExtraCode && ExtraCode[0]) {
440 if (ExtraCode[1] != 0) return true; // Unknown modifier.
442 const MachineOperand &MO = MI->getOperand(OpNum);
443 switch (ExtraCode[0]) {
445 // See if this is a generic print operand
446 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
447 case 'X': // hex const int
448 if ((MO.getType()) != MachineOperand::MO_Immediate)
450 O << "0x" << Twine::utohexstr(MO.getImm());
452 case 'x': // hex const int (low 16 bits)
453 if ((MO.getType()) != MachineOperand::MO_Immediate)
455 O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
457 case 'd': // decimal const int
458 if ((MO.getType()) != MachineOperand::MO_Immediate)
462 case 'm': // decimal const int minus 1
463 if ((MO.getType()) != MachineOperand::MO_Immediate)
465 O << MO.getImm() - 1;
468 // $0 if zero, regular printing otherwise
469 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
473 // If not, call printOperand as normal.
476 case 'D': // Second part of a double word register operand
477 case 'L': // Low order register of a double word register operand
478 case 'M': // High order register of a double word register operand
482 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
483 if (!FlagsOP.isImm())
485 unsigned Flags = FlagsOP.getImm();
486 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
487 // Number of registers represented by this operand. We are looking
488 // for 2 for 32 bit mode and 1 for 64 bit mode.
490 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
491 unsigned Reg = MO.getReg();
492 O << '$' << MipsInstPrinter::getRegisterName(Reg);
498 unsigned RegOp = OpNum;
499 if (!Subtarget->isGP64bit()){
500 // Endianess reverses which register holds the high or low value
502 switch(ExtraCode[0]) {
504 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
507 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
509 case 'D': // Always the second part
512 if (RegOp >= MI->getNumOperands())
514 const MachineOperand &MO = MI->getOperand(RegOp);
517 unsigned Reg = MO.getReg();
518 O << '$' << MipsInstPrinter::getRegisterName(Reg);
523 // Print MSA registers for the 'f' constraint
524 // In LLVM, the 'w' modifier doesn't need to do anything.
525 // We can just call printOperand as normal.
530 printOperand(MI, OpNum, O);
534 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
535 unsigned OpNum, unsigned AsmVariant,
536 const char *ExtraCode,
538 assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
539 const MachineOperand &BaseMO = MI->getOperand(OpNum);
540 const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
541 assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
542 assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
543 int Offset = OffsetMO.getImm();
545 // Currently we are expecting either no ExtraCode or 'D'
547 if (ExtraCode[0] == 'D')
550 return true; // Unknown modifier.
551 // FIXME: M = high order bits
552 // FIXME: L = low order bits
555 O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")";
560 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
562 const MachineOperand &MO = MI->getOperand(opNum);
565 if (MO.getTargetFlags())
568 switch(MO.getTargetFlags()) {
569 case MipsII::MO_GPREL: O << "%gp_rel("; break;
570 case MipsII::MO_GOT_CALL: O << "%call16("; break;
571 case MipsII::MO_GOT: O << "%got("; break;
572 case MipsII::MO_ABS_HI: O << "%hi("; break;
573 case MipsII::MO_ABS_LO: O << "%lo("; break;
574 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
575 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
576 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
577 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
578 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
579 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
580 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
581 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
582 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
585 switch (MO.getType()) {
586 case MachineOperand::MO_Register:
588 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
591 case MachineOperand::MO_Immediate:
595 case MachineOperand::MO_MachineBasicBlock:
596 MO.getMBB()->getSymbol()->print(O, MAI);
599 case MachineOperand::MO_GlobalAddress:
600 getSymbol(MO.getGlobal())->print(O, MAI);
603 case MachineOperand::MO_BlockAddress: {
604 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
609 case MachineOperand::MO_ConstantPoolIndex:
610 O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
611 << getFunctionNumber() << "_" << MO.getIndex();
613 O << "+" << MO.getOffset();
617 llvm_unreachable("<unknown operand type>");
620 if (closeP) O << ")";
623 void MipsAsmPrinter::
624 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
625 // Load/Store memory operands -- imm($reg)
626 // If PIC target the target is loaded as the
627 // pattern lw $25,%call16($28)
629 // opNum can be invalid if instruction has reglist as operand.
630 // MemOperand is always last operand of instruction (base + offset).
631 switch (MI->getOpcode()) {
636 opNum = MI->getNumOperands() - 2;
640 printOperand(MI, opNum+1, O);
642 printOperand(MI, opNum, O);
646 void MipsAsmPrinter::
647 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
648 // when using stack locations for not load/store instructions
649 // print the same way as all normal 3 operand instructions.
650 printOperand(MI, opNum, O);
652 printOperand(MI, opNum+1, O);
656 void MipsAsmPrinter::
657 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
658 const char *Modifier) {
659 const MachineOperand &MO = MI->getOperand(opNum);
660 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
663 void MipsAsmPrinter::
664 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
665 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
666 if (i != opNum) O << ", ";
667 printOperand(MI, i, O);
671 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
672 MipsTargetStreamer &TS = getTargetStreamer();
674 // MipsTargetStreamer has an initialization order problem when emitting an
675 // object file directly (see MipsTargetELFStreamer for full details). Work
676 // around it by re-initializing the PIC state here.
677 TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent());
679 // Compute MIPS architecture attributes based on the default subtarget
680 // that we'd have constructed. Module level directives aren't LTO
682 // FIXME: For ifunc related functions we could iterate over and look
683 // for a feature string that doesn't match the default one.
684 const Triple &TT = TM.getTargetTriple();
685 StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
686 StringRef FS = TM.getTargetFeatureString();
687 const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
688 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
690 bool IsABICalls = STI.isABICalls();
691 const MipsABIInfo &ABI = MTM.getABI();
693 TS.emitDirectiveAbiCalls();
694 // FIXME: This condition should be a lot more complicated that it is here.
695 // Ideally it should test for properties of the ABI and not the ABI
697 // For the moment, I'm only correcting enough to make MIPS-IV work.
698 if (!isPositionIndependent() && !ABI.IsN64())
699 TS.emitDirectiveOptionPic0();
702 // Tell the assembler which ABI we are using
703 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
704 OutStreamer->SwitchSection(
705 OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
707 // NaN: At the moment we only support:
708 // 1. .nan legacy (default)
710 STI.isNaN2008() ? TS.emitDirectiveNaN2008()
711 : TS.emitDirectiveNaNLegacy();
713 // TODO: handle O64 ABI
715 TS.updateABIInfo(STI);
717 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
718 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
719 // -mfp64) and omit it otherwise.
720 if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
721 TS.emitDirectiveModuleFP();
723 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
724 // accept it. We therefore emit it when it contradicts the default or an
725 // option has changed the default (i.e. FPXX) and omit it otherwise.
726 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
727 TS.emitDirectiveModuleOddSPReg();
730 void MipsAsmPrinter::emitInlineAsmStart() const {
731 MipsTargetStreamer &TS = getTargetStreamer();
733 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
734 // and 'reorder') is different from LLVM's choice for generated code ('noat',
735 // 'nomacro' and 'noreorder').
736 // In order to maintain compatibility with inline assembly code which depends
737 // on GCC's assembler options being used, we have to switch to those options
738 // for the duration of the inline assembly block and then switch back.
739 TS.emitDirectiveSetPush();
740 TS.emitDirectiveSetAt();
741 TS.emitDirectiveSetMacro();
742 TS.emitDirectiveSetReorder();
743 OutStreamer->AddBlankLine();
746 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
747 const MCSubtargetInfo *EndInfo) const {
748 OutStreamer->AddBlankLine();
749 getTargetStreamer().emitDirectiveSetPop();
752 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
754 I.setOpcode(Mips::JAL);
756 MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext)));
757 OutStreamer->EmitInstruction(I, STI);
760 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
764 I.addOperand(MCOperand::createReg(Reg));
765 OutStreamer->EmitInstruction(I, STI);
768 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
769 unsigned Opcode, unsigned Reg1,
773 // Because of the current td files for Mips32, the operands for MTC1
774 // appear backwards from their normal assembly order. It's not a trivial
775 // change to fix this in the td file so we adjust for it here.
777 if (Opcode == Mips::MTC1) {
778 unsigned Temp = Reg1;
783 I.addOperand(MCOperand::createReg(Reg1));
784 I.addOperand(MCOperand::createReg(Reg2));
785 OutStreamer->EmitInstruction(I, STI);
788 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
789 unsigned Opcode, unsigned Reg1,
790 unsigned Reg2, unsigned Reg3) {
793 I.addOperand(MCOperand::createReg(Reg1));
794 I.addOperand(MCOperand::createReg(Reg2));
795 I.addOperand(MCOperand::createReg(Reg3));
796 OutStreamer->EmitInstruction(I, STI);
799 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
800 unsigned MovOpc, unsigned Reg1,
801 unsigned Reg2, unsigned FPReg1,
802 unsigned FPReg2, bool LE) {
804 unsigned temp = Reg1;
808 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
809 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
812 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
813 Mips16HardFloatInfo::FPParamVariant PV,
814 bool LE, bool ToFP) {
815 using namespace Mips16HardFloatInfo;
816 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
819 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
822 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
825 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
826 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
829 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
832 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
833 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
836 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
837 EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
844 void MipsAsmPrinter::EmitSwapFPIntRetval(
845 const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
847 using namespace Mips16HardFloatInfo;
848 unsigned MovOpc = Mips::MFC1;
851 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
854 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
857 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
860 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
861 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
868 void MipsAsmPrinter::EmitFPCallStub(
869 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
870 MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
871 using namespace Mips16HardFloatInfo;
872 bool LE = getDataLayout().isLittleEndian();
873 // Construct a local MCSubtargetInfo here.
874 // This is because the MachineFunction won't exist (but have not yet been
875 // freed) and since we're at the global level we can use the default
876 // constructed subtarget.
877 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
878 TM.getTargetTriple().str(), TM.getTargetCPU(),
879 TM.getTargetFeatureString()));
884 OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
887 // make the comment field identifying the return and parameter
888 // types of the floating point stub
889 // # Stub function to call rettype xxxx (params)
891 switch (Signature->RetSig) {
902 RetType = "double complex";
909 switch (Signature->ParamSig) {
914 Parms = "float, float";
917 Parms = "float, double";
923 Parms = "double, double";
926 Parms = "double, float";
932 OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " +
933 Twine(Symbol) + " (" + Twine(Parms) + ")");
935 // probably not necessary but we save and restore the current section state
937 OutStreamer->PushSection();
939 // .section mips16.call.fpxxxx,"ax",@progbits
941 MCSectionELF *M = OutContext.getELFSection(
942 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
943 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR);
944 OutStreamer->SwitchSection(M, nullptr);
948 OutStreamer->EmitValueToAlignment(4);
949 MipsTargetStreamer &TS = getTargetStreamer();
954 TS.emitDirectiveSetNoMips16();
955 TS.emitDirectiveSetNoMicroMips();
957 // .ent __call_stub_fp_xxxx
958 // .type __call_stub_fp_xxxx,@function
959 // __call_stub_fp_xxxx:
961 std::string x = "__call_stub_fp_" + std::string(Symbol);
963 cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x)));
964 TS.emitDirectiveEnt(*Stub);
966 OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
967 OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
968 OutStreamer->EmitLabel(Stub);
970 // Only handle non-pic for now.
971 assert(!isPositionIndependent() &&
972 "should not be here if we are compiling pic");
973 TS.emitDirectiveSetReorder();
975 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
976 // stubs without raw text but this current patch is for compiler generated
977 // functions and they all return some value.
978 // The calling sequence for non pic is different in that case and we need
979 // to implement %lo and %hi in order to handle the case of no return value
980 // See the corresponding method in Mips16HardFloat for details.
982 // mov the return address to S2.
983 // we have no stack space to store it and we are about to make another call.
984 // We need to make sure that the enclosing function knows to save S2
985 // This should have already been handled.
989 EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
991 EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
995 EmitJal(*STI, MSymbol);
998 EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1001 // if (Signature->RetSig == NoFPRet)
1002 // llvm_unreachable("should not be any stubs here with no return value");
1004 EmitInstrReg(*STI, Mips::JR, Mips::S2);
1006 MCSymbol *Tmp = OutContext.createTempSymbol();
1007 OutStreamer->EmitLabel(Tmp);
1008 const MCSymbolRefExpr *E = MCSymbolRefExpr::create(Stub, OutContext);
1009 const MCSymbolRefExpr *T = MCSymbolRefExpr::create(Tmp, OutContext);
1010 const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext);
1011 OutStreamer->emitELFSize(Stub, T_min_E);
1012 TS.emitDirectiveEnd(x);
1013 OutStreamer->PopSection();
1016 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
1017 // Emit needed stubs
1021 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1022 it = StubsNeeded.begin();
1023 it != StubsNeeded.end(); ++it) {
1024 const char *Symbol = it->first;
1025 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1026 EmitFPCallStub(Symbol, Signature);
1028 // return to the text section
1029 OutStreamer->SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
1032 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1037 // Align all targets of indirect branches on bundle size. Used only if target
1039 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1040 // Align all blocks that are jumped to through jump table.
1041 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1042 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1043 for (unsigned I = 0; I < JT.size(); ++I) {
1044 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1046 for (unsigned J = 0; J < MBBs.size(); ++J)
1047 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1051 // If basic block address is taken, block can be target of indirect branch.
1052 for (auto &MBB : MF) {
1053 if (MBB.hasAddressTaken())
1054 MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1058 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1059 return (Opcode == Mips::LONG_BRANCH_LUi
1060 || Opcode == Mips::LONG_BRANCH_ADDiu
1061 || Opcode == Mips::LONG_BRANCH_DADDiu);
1064 // Force static initialization.
1065 extern "C" void LLVMInitializeMipsAsmPrinter() {
1066 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
1067 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
1068 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
1069 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);