1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "MipsAsmPrinter.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MCTargetDesc/MipsMCNaCl.h"
20 #include "MCTargetDesc/MipsMCTargetDesc.h"
22 #include "MipsMCInstLower.h"
23 #include "MipsMachineFunction.h"
24 #include "MipsSubtarget.h"
25 #include "MipsTargetMachine.h"
26 #include "MipsTargetStreamer.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/BinaryFormat/ELF.h"
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineConstantPool.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstr.h"
37 #include "llvm/CodeGen/MachineJumpTableInfo.h"
38 #include "llvm/CodeGen/MachineOperand.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/BasicBlock.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCInst.h"
50 #include "llvm/MC/MCInstBuilder.h"
51 #include "llvm/MC/MCObjectFileInfo.h"
52 #include "llvm/MC/MCSectionELF.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/MC/MCSymbolELF.h"
55 #include "llvm/Support/Casting.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/TargetRegistry.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetMachine.h"
69 #define DEBUG_TYPE "mips-asm-printer"
71 extern cl::opt<bool> EmitJalrReloc;
73 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
74 return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
77 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
78 Subtarget = &MF.getSubtarget<MipsSubtarget>();
80 MipsFI = MF.getInfo<MipsFunctionInfo>();
81 if (Subtarget->inMips16Mode())
84 const Mips16HardFloatInfo::FuncSignature *>::const_iterator
85 it = MipsFI->StubsNeeded.begin();
86 it != MipsFI->StubsNeeded.end(); ++it) {
87 const char *Symbol = it->first;
88 const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
89 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
90 StubsNeeded[Symbol] = Signature;
92 MCP = MF.getConstantPool();
94 // In NaCl, all indirect jump targets must be aligned to bundle size.
95 if (Subtarget->isTargetNaCl())
96 NaClAlignIndirectJumpTargets(MF);
98 AsmPrinter::runOnMachineFunction(MF);
105 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
106 MCOp = MCInstLowering.LowerOperand(MO);
107 return MCOp.isValid();
110 #include "MipsGenMCPseudoLowering.inc"
112 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
113 // JALR, or JALR64 as appropriate for the target.
114 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
115 const MachineInstr *MI) {
116 bool HasLinkReg = false;
117 bool InMicroMipsMode = Subtarget->inMicroMipsMode();
120 if (Subtarget->hasMips64r6()) {
121 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
122 TmpInst0.setOpcode(Mips::JALR64);
124 } else if (Subtarget->hasMips32r6()) {
125 // MIPS32r6 should use (JALR ZERO, $rs)
127 TmpInst0.setOpcode(Mips::JRC16_MMR6);
129 TmpInst0.setOpcode(Mips::JALR);
132 } else if (Subtarget->inMicroMipsMode())
133 // microMIPS should use (JR_MM $rs)
134 TmpInst0.setOpcode(Mips::JR_MM);
136 // Everything else should use (JR $rs)
137 TmpInst0.setOpcode(Mips::JR);
143 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
144 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
147 lowerOperand(MI->getOperand(0), MCOp);
148 TmpInst0.addOperand(MCOp);
150 EmitToStreamer(OutStreamer, TmpInst0);
153 // If there is an MO_JALR operand, insert:
155 // .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
158 // This is an optimization hint for the linker which may then replace
159 // an indirect call with a direct branch.
160 static void emitDirectiveRelocJalr(const MachineInstr &MI,
161 MCContext &OutContext,
163 MCStreamer &OutStreamer,
164 const MipsSubtarget &Subtarget) {
165 for (unsigned int I = MI.getDesc().getNumOperands(), E = MI.getNumOperands();
167 MachineOperand MO = MI.getOperand(I);
168 if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR)) {
169 MCSymbol *Callee = MO.getMCSymbol();
170 if (Callee && !Callee->getName().empty()) {
171 MCSymbol *OffsetLabel = OutContext.createTempSymbol();
172 const MCExpr *OffsetExpr =
173 MCSymbolRefExpr::create(OffsetLabel, OutContext);
174 const MCExpr *CaleeExpr =
175 MCSymbolRefExpr::create(Callee, OutContext);
176 OutStreamer.EmitRelocDirective
178 Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
179 CaleeExpr, SMLoc(), *TM.getMCSubtargetInfo());
180 OutStreamer.EmitLabel(OffsetLabel);
187 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
188 MipsTargetStreamer &TS = getTargetStreamer();
189 unsigned Opc = MI->getOpcode();
190 TS.forbidModuleDirective();
192 if (MI->isDebugValue()) {
193 SmallString<128> Str;
194 raw_svector_ostream OS(Str);
196 PrintDebugValueComment(MI, OS);
199 if (MI->isDebugLabel())
202 // If we just ended a constant pool, mark it as such.
203 if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
204 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
205 InConstantPool = false;
207 if (Opc == Mips::CONSTPOOL_ENTRY) {
208 // CONSTPOOL_ENTRY - This instruction represents a floating
209 // constant pool in the function. The first operand is the ID#
210 // for this instruction, the second is the index into the
211 // MachineConstantPool that this is, the third is the size in
212 // bytes of this constant pool entry.
213 // The required alignment is specified on the basic block holding this MI.
215 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
216 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
218 // If this is the first entry of the pool, mark it.
219 if (!InConstantPool) {
220 OutStreamer->EmitDataRegion(MCDR_DataRegion);
221 InConstantPool = true;
224 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
226 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
227 if (MCPE.isMachineConstantPoolEntry())
228 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
230 EmitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal);
235 case Mips::PATCHABLE_FUNCTION_ENTER:
236 LowerPATCHABLE_FUNCTION_ENTER(*MI);
238 case Mips::PATCHABLE_FUNCTION_EXIT:
239 LowerPATCHABLE_FUNCTION_EXIT(*MI);
241 case Mips::PATCHABLE_TAIL_CALL:
242 LowerPATCHABLE_TAIL_CALL(*MI);
247 (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) {
248 emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget);
251 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
252 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
255 // Do any auto-generated pseudo lowerings.
256 if (emitPseudoExpansionLowering(*OutStreamer, &*I))
259 if (I->getOpcode() == Mips::PseudoReturn ||
260 I->getOpcode() == Mips::PseudoReturn64 ||
261 I->getOpcode() == Mips::PseudoIndirectBranch ||
262 I->getOpcode() == Mips::PseudoIndirectBranch64 ||
263 I->getOpcode() == Mips::TAILCALLREG ||
264 I->getOpcode() == Mips::TAILCALLREG64) {
265 emitPseudoIndirectBranch(*OutStreamer, &*I);
269 // The inMips16Mode() test is not permanent.
270 // Some instructions are marked as pseudo right now which
271 // would make the test fail for the wrong reason but
272 // that will be fixed soon. We need this here because we are
273 // removing another test for this situation downstream in the
276 if (I->isPseudo() && !Subtarget->inMips16Mode()
277 && !isLongBranchPseudo(I->getOpcode()))
278 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
281 MCInstLowering.Lower(&*I, TmpInst0);
282 EmitToStreamer(*OutStreamer, TmpInst0);
283 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
286 //===----------------------------------------------------------------------===//
288 // Mips Asm Directives
290 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
291 // Describe the stack frame.
293 // -- Mask directives "(f)mask bitmask, offset"
294 // Tells the assembler which registers are saved and where.
295 // bitmask - contain a little endian bitset indicating which registers are
296 // saved on function prologue (e.g. with a 0x80000000 mask, the
297 // assembler knows the register 31 (RA) is saved at prologue.
298 // offset - the position before stack pointer subtraction indicating where
299 // the first saved register on prologue is located. (e.g. with a
301 // Consider the following function prologue:
304 // .mask 0xc0000000,-8
305 // addiu $sp, $sp, -48
309 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
310 // 30 (FP) are saved at prologue. As the save order on prologue is from
311 // left to right, RA is saved first. A -8 offset means that after the
312 // stack pointer subtration, the first register in the mask (RA) will be
313 // saved at address 48-8=40.
315 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
319 //===----------------------------------------------------------------------===//
321 // Create a bitmask with all callee saved registers for CPU or Floating Point
322 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
323 void MipsAsmPrinter::printSavedRegsBitmask() {
324 // CPU and FPU Saved Registers Bitmasks
325 unsigned CPUBitmask = 0, FPUBitmask = 0;
326 int CPUTopSavedRegOff, FPUTopSavedRegOff;
328 // Set the CPU and FPU Bitmasks
329 const MachineFrameInfo &MFI = MF->getFrameInfo();
330 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
331 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
332 // size of stack area to which FP callee-saved regs are saved.
333 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
334 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
335 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
336 bool HasAFGR64Reg = false;
337 unsigned CSFPRegsSize = 0;
339 for (const auto &I : CSI) {
340 unsigned Reg = I.getReg();
341 unsigned RegNum = TRI->getEncodingValue(Reg);
343 // If it's a floating point register, set the FPU Bitmask.
344 // If it's a general purpose register, set the CPU Bitmask.
345 if (Mips::FGR32RegClass.contains(Reg)) {
346 FPUBitmask |= (1 << RegNum);
347 CSFPRegsSize += FGR32RegSize;
348 } else if (Mips::AFGR64RegClass.contains(Reg)) {
349 FPUBitmask |= (3 << RegNum);
350 CSFPRegsSize += AFGR64RegSize;
352 } else if (Mips::GPR32RegClass.contains(Reg))
353 CPUBitmask |= (1 << RegNum);
356 // FP Regs are saved right below where the virtual frame pointer points to.
357 FPUTopSavedRegOff = FPUBitmask ?
358 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
360 // CPU Regs are saved below FP Regs.
361 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
363 MipsTargetStreamer &TS = getTargetStreamer();
365 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
368 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
371 //===----------------------------------------------------------------------===//
372 // Frame and Set directives
373 //===----------------------------------------------------------------------===//
376 void MipsAsmPrinter::emitFrameDirective() {
377 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
379 unsigned stackReg = RI.getFrameRegister(*MF);
380 unsigned returnReg = RI.getRARegister();
381 unsigned stackSize = MF->getFrameInfo().getStackSize();
383 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
386 /// Emit Set directives.
387 const char *MipsAsmPrinter::getCurrentABIString() const {
388 switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
389 case MipsABIInfo::ABI::O32: return "abi32";
390 case MipsABIInfo::ABI::N32: return "abiN32";
391 case MipsABIInfo::ABI::N64: return "abi64";
392 default: llvm_unreachable("Unknown Mips ABI");
396 void MipsAsmPrinter::EmitFunctionEntryLabel() {
397 MipsTargetStreamer &TS = getTargetStreamer();
399 // NaCl sandboxing requires that indirect call instructions are masked.
400 // This means that function entry points should be bundle-aligned.
401 if (Subtarget->isTargetNaCl())
402 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
404 if (Subtarget->inMicroMipsMode()) {
405 TS.emitDirectiveSetMicroMips();
406 TS.setUsesMicroMips();
407 TS.updateABIInfo(*Subtarget);
409 TS.emitDirectiveSetNoMicroMips();
411 if (Subtarget->inMips16Mode())
412 TS.emitDirectiveSetMips16();
414 TS.emitDirectiveSetNoMips16();
416 TS.emitDirectiveEnt(*CurrentFnSym);
417 OutStreamer->EmitLabel(CurrentFnSym);
420 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
421 /// the first basic block in the function.
422 void MipsAsmPrinter::EmitFunctionBodyStart() {
423 MipsTargetStreamer &TS = getTargetStreamer();
425 MCInstLowering.Initialize(&MF->getContext());
427 bool IsNakedFunction = MF->getFunction().hasFnAttribute(Attribute::Naked);
428 if (!IsNakedFunction)
429 emitFrameDirective();
431 if (!IsNakedFunction)
432 printSavedRegsBitmask();
434 if (!Subtarget->inMips16Mode()) {
435 TS.emitDirectiveSetNoReorder();
436 TS.emitDirectiveSetNoMacro();
437 TS.emitDirectiveSetNoAt();
441 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
442 /// the last basic block in the function.
443 void MipsAsmPrinter::EmitFunctionBodyEnd() {
444 MipsTargetStreamer &TS = getTargetStreamer();
446 // There are instruction for this macros, but they must
447 // always be at the function end, and we can't emit and
448 // break with BB logic.
449 if (!Subtarget->inMips16Mode()) {
450 TS.emitDirectiveSetAt();
451 TS.emitDirectiveSetMacro();
452 TS.emitDirectiveSetReorder();
454 TS.emitDirectiveEnd(CurrentFnSym->getName());
455 // Make sure to terminate any constant pools that were at the end
459 InConstantPool = false;
460 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
463 void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) {
464 AsmPrinter::EmitBasicBlockEnd(MBB);
465 MipsTargetStreamer &TS = getTargetStreamer();
467 TS.emitDirectiveInsn();
470 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
471 /// exactly one predecessor and the control transfer mechanism between
472 /// the predecessor and this block is a fall-through.
473 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
475 // The predecessor has to be immediately before this block.
476 const MachineBasicBlock *Pred = *MBB->pred_begin();
478 // If the predecessor is a switch statement, assume a jump table
479 // implementation, so it is not a fall through.
480 if (const BasicBlock *bb = Pred->getBasicBlock())
481 if (isa<SwitchInst>(bb->getTerminator()))
484 // If this is a landing pad, it isn't a fall through. If it has no preds,
485 // then nothing falls through to it.
486 if (MBB->isEHPad() || MBB->pred_empty())
489 // If there isn't exactly one predecessor, it can't be a fall through.
490 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
493 if (PI2 != MBB->pred_end())
496 // The predecessor has to be immediately before this block.
497 if (!Pred->isLayoutSuccessor(MBB))
500 // If the block is completely empty, then it definitely does fall through.
504 // Otherwise, check the last instruction.
505 // Check if the last terminator is an unconditional branch.
506 MachineBasicBlock::const_iterator I = Pred->end();
507 while (I != Pred->begin() && !(--I)->isTerminator()) ;
509 return !I->isBarrier();
512 // Print out an operand for an inline asm expression.
513 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
514 unsigned AsmVariant, const char *ExtraCode,
516 // Does this asm operand have a single letter operand modifier?
517 if (ExtraCode && ExtraCode[0]) {
518 if (ExtraCode[1] != 0) return true; // Unknown modifier.
520 const MachineOperand &MO = MI->getOperand(OpNum);
521 switch (ExtraCode[0]) {
523 // See if this is a generic print operand
524 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
525 case 'X': // hex const int
526 if ((MO.getType()) != MachineOperand::MO_Immediate)
528 O << "0x" << Twine::utohexstr(MO.getImm());
530 case 'x': // hex const int (low 16 bits)
531 if ((MO.getType()) != MachineOperand::MO_Immediate)
533 O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
535 case 'd': // decimal const int
536 if ((MO.getType()) != MachineOperand::MO_Immediate)
540 case 'm': // decimal const int minus 1
541 if ((MO.getType()) != MachineOperand::MO_Immediate)
543 O << MO.getImm() - 1;
545 case 'y': // exact log2
546 if ((MO.getType()) != MachineOperand::MO_Immediate)
548 if (!isPowerOf2_64(MO.getImm()))
550 O << Log2_64(MO.getImm());
553 // $0 if zero, regular printing otherwise
554 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
558 // If not, call printOperand as normal.
560 case 'D': // Second part of a double word register operand
561 case 'L': // Low order register of a double word register operand
562 case 'M': // High order register of a double word register operand
566 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
567 if (!FlagsOP.isImm())
569 unsigned Flags = FlagsOP.getImm();
570 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
571 // Number of registers represented by this operand. We are looking
572 // for 2 for 32 bit mode and 1 for 64 bit mode.
574 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
575 unsigned Reg = MO.getReg();
576 O << '$' << MipsInstPrinter::getRegisterName(Reg);
582 unsigned RegOp = OpNum;
583 if (!Subtarget->isGP64bit()){
584 // Endianness reverses which register holds the high or low value
586 switch(ExtraCode[0]) {
588 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
591 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
593 case 'D': // Always the second part
596 if (RegOp >= MI->getNumOperands())
598 const MachineOperand &MO = MI->getOperand(RegOp);
601 unsigned Reg = MO.getReg();
602 O << '$' << MipsInstPrinter::getRegisterName(Reg);
608 // Print MSA registers for the 'f' constraint
609 // In LLVM, the 'w' modifier doesn't need to do anything.
610 // We can just call printOperand as normal.
615 printOperand(MI, OpNum, O);
619 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
620 unsigned OpNum, unsigned AsmVariant,
621 const char *ExtraCode,
623 assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
624 const MachineOperand &BaseMO = MI->getOperand(OpNum);
625 const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
626 assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
627 assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
628 int Offset = OffsetMO.getImm();
630 // Currently we are expecting either no ExtraCode or 'D','M','L'.
632 switch (ExtraCode[0]) {
637 if (Subtarget->isLittle())
641 if (!Subtarget->isLittle())
645 return true; // Unknown modifier.
649 O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg())
655 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
657 const MachineOperand &MO = MI->getOperand(opNum);
660 if (MO.getTargetFlags())
663 switch(MO.getTargetFlags()) {
664 case MipsII::MO_GPREL: O << "%gp_rel("; break;
665 case MipsII::MO_GOT_CALL: O << "%call16("; break;
666 case MipsII::MO_GOT: O << "%got("; break;
667 case MipsII::MO_ABS_HI: O << "%hi("; break;
668 case MipsII::MO_ABS_LO: O << "%lo("; break;
669 case MipsII::MO_HIGHER: O << "%higher("; break;
670 case MipsII::MO_HIGHEST: O << "%highest(("; break;
671 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
672 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
673 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
674 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
675 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
676 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
677 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
678 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
679 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
682 switch (MO.getType()) {
683 case MachineOperand::MO_Register:
685 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
688 case MachineOperand::MO_Immediate:
692 case MachineOperand::MO_MachineBasicBlock:
693 MO.getMBB()->getSymbol()->print(O, MAI);
696 case MachineOperand::MO_GlobalAddress:
697 getSymbol(MO.getGlobal())->print(O, MAI);
700 case MachineOperand::MO_BlockAddress: {
701 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
706 case MachineOperand::MO_ConstantPoolIndex:
707 O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
708 << getFunctionNumber() << "_" << MO.getIndex();
710 O << "+" << MO.getOffset();
714 llvm_unreachable("<unknown operand type>");
717 if (closeP) O << ")";
720 void MipsAsmPrinter::
721 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
722 // Load/Store memory operands -- imm($reg)
723 // If PIC target the target is loaded as the
724 // pattern lw $25,%call16($28)
726 // opNum can be invalid if instruction has reglist as operand.
727 // MemOperand is always last operand of instruction (base + offset).
728 switch (MI->getOpcode()) {
733 opNum = MI->getNumOperands() - 2;
737 printOperand(MI, opNum+1, O);
739 printOperand(MI, opNum, O);
743 void MipsAsmPrinter::
744 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
745 // when using stack locations for not load/store instructions
746 // print the same way as all normal 3 operand instructions.
747 printOperand(MI, opNum, O);
749 printOperand(MI, opNum+1, O);
752 void MipsAsmPrinter::
753 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
754 const char *Modifier) {
755 const MachineOperand &MO = MI->getOperand(opNum);
756 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
759 void MipsAsmPrinter::
760 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
761 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
762 if (i != opNum) O << ", ";
763 printOperand(MI, i, O);
767 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
768 MipsTargetStreamer &TS = getTargetStreamer();
770 // MipsTargetStreamer has an initialization order problem when emitting an
771 // object file directly (see MipsTargetELFStreamer for full details). Work
772 // around it by re-initializing the PIC state here.
773 TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent());
775 // Compute MIPS architecture attributes based on the default subtarget
776 // that we'd have constructed. Module level directives aren't LTO
778 // FIXME: For ifunc related functions we could iterate over and look
779 // for a feature string that doesn't match the default one.
780 const Triple &TT = TM.getTargetTriple();
781 StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
782 StringRef FS = TM.getTargetFeatureString();
783 const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
784 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, 0);
786 bool IsABICalls = STI.isABICalls();
787 const MipsABIInfo &ABI = MTM.getABI();
789 TS.emitDirectiveAbiCalls();
790 // FIXME: This condition should be a lot more complicated that it is here.
791 // Ideally it should test for properties of the ABI and not the ABI
793 // For the moment, I'm only correcting enough to make MIPS-IV work.
794 if (!isPositionIndependent() && STI.hasSym32())
795 TS.emitDirectiveOptionPic0();
798 // Tell the assembler which ABI we are using
799 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
800 OutStreamer->SwitchSection(
801 OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
803 // NaN: At the moment we only support:
804 // 1. .nan legacy (default)
806 STI.isNaN2008() ? TS.emitDirectiveNaN2008()
807 : TS.emitDirectiveNaNLegacy();
809 // TODO: handle O64 ABI
811 TS.updateABIInfo(STI);
813 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
814 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
815 // -mfp64) and omit it otherwise.
816 if ((ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit())) ||
818 TS.emitDirectiveModuleFP();
820 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
821 // accept it. We therefore emit it when it contradicts the default or an
822 // option has changed the default (i.e. FPXX) and omit it otherwise.
823 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
824 TS.emitDirectiveModuleOddSPReg();
827 void MipsAsmPrinter::emitInlineAsmStart() const {
828 MipsTargetStreamer &TS = getTargetStreamer();
830 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
831 // and 'reorder') is different from LLVM's choice for generated code ('noat',
832 // 'nomacro' and 'noreorder').
833 // In order to maintain compatibility with inline assembly code which depends
834 // on GCC's assembler options being used, we have to switch to those options
835 // for the duration of the inline assembly block and then switch back.
836 TS.emitDirectiveSetPush();
837 TS.emitDirectiveSetAt();
838 TS.emitDirectiveSetMacro();
839 TS.emitDirectiveSetReorder();
840 OutStreamer->AddBlankLine();
843 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
844 const MCSubtargetInfo *EndInfo) const {
845 OutStreamer->AddBlankLine();
846 getTargetStreamer().emitDirectiveSetPop();
849 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
851 I.setOpcode(Mips::JAL);
853 MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext)));
854 OutStreamer->EmitInstruction(I, STI);
857 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
861 I.addOperand(MCOperand::createReg(Reg));
862 OutStreamer->EmitInstruction(I, STI);
865 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
866 unsigned Opcode, unsigned Reg1,
870 // Because of the current td files for Mips32, the operands for MTC1
871 // appear backwards from their normal assembly order. It's not a trivial
872 // change to fix this in the td file so we adjust for it here.
874 if (Opcode == Mips::MTC1) {
875 unsigned Temp = Reg1;
880 I.addOperand(MCOperand::createReg(Reg1));
881 I.addOperand(MCOperand::createReg(Reg2));
882 OutStreamer->EmitInstruction(I, STI);
885 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
886 unsigned Opcode, unsigned Reg1,
887 unsigned Reg2, unsigned Reg3) {
890 I.addOperand(MCOperand::createReg(Reg1));
891 I.addOperand(MCOperand::createReg(Reg2));
892 I.addOperand(MCOperand::createReg(Reg3));
893 OutStreamer->EmitInstruction(I, STI);
896 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
897 unsigned MovOpc, unsigned Reg1,
898 unsigned Reg2, unsigned FPReg1,
899 unsigned FPReg2, bool LE) {
901 unsigned temp = Reg1;
905 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
906 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
909 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
910 Mips16HardFloatInfo::FPParamVariant PV,
911 bool LE, bool ToFP) {
912 using namespace Mips16HardFloatInfo;
914 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
917 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
920 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
923 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
924 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
927 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
930 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
931 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
934 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
935 EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
942 void MipsAsmPrinter::EmitSwapFPIntRetval(
943 const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
945 using namespace Mips16HardFloatInfo;
947 unsigned MovOpc = Mips::MFC1;
950 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
953 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
956 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
959 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
960 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
967 void MipsAsmPrinter::EmitFPCallStub(
968 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
969 using namespace Mips16HardFloatInfo;
971 MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
972 bool LE = getDataLayout().isLittleEndian();
973 // Construct a local MCSubtargetInfo here.
974 // This is because the MachineFunction won't exist (but have not yet been
975 // freed) and since we're at the global level we can use the default
976 // constructed subtarget.
977 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
978 TM.getTargetTriple().str(), TM.getTargetCPU(),
979 TM.getTargetFeatureString()));
984 OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
987 // make the comment field identifying the return and parameter
988 // types of the floating point stub
989 // # Stub function to call rettype xxxx (params)
991 switch (Signature->RetSig) {
1002 RetType = "double complex";
1009 switch (Signature->ParamSig) {
1014 Parms = "float, float";
1017 Parms = "float, double";
1023 Parms = "double, double";
1026 Parms = "double, float";
1032 OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " +
1033 Twine(Symbol) + " (" + Twine(Parms) + ")");
1035 // probably not necessary but we save and restore the current section state
1037 OutStreamer->PushSection();
1039 // .section mips16.call.fpxxxx,"ax",@progbits
1041 MCSectionELF *M = OutContext.getELFSection(
1042 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
1043 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR);
1044 OutStreamer->SwitchSection(M, nullptr);
1048 OutStreamer->EmitValueToAlignment(4);
1049 MipsTargetStreamer &TS = getTargetStreamer();
1054 TS.emitDirectiveSetNoMips16();
1055 TS.emitDirectiveSetNoMicroMips();
1057 // .ent __call_stub_fp_xxxx
1058 // .type __call_stub_fp_xxxx,@function
1059 // __call_stub_fp_xxxx:
1061 std::string x = "__call_stub_fp_" + std::string(Symbol);
1063 cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x)));
1064 TS.emitDirectiveEnt(*Stub);
1066 OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
1067 OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
1068 OutStreamer->EmitLabel(Stub);
1070 // Only handle non-pic for now.
1071 assert(!isPositionIndependent() &&
1072 "should not be here if we are compiling pic");
1073 TS.emitDirectiveSetReorder();
1075 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
1076 // stubs without raw text but this current patch is for compiler generated
1077 // functions and they all return some value.
1078 // The calling sequence for non pic is different in that case and we need
1079 // to implement %lo and %hi in order to handle the case of no return value
1080 // See the corresponding method in Mips16HardFloat for details.
1082 // mov the return address to S2.
1083 // we have no stack space to store it and we are about to make another call.
1084 // We need to make sure that the enclosing function knows to save S2
1085 // This should have already been handled.
1089 EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1091 EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
1095 EmitJal(*STI, MSymbol);
1097 // fix return values
1098 EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1101 // if (Signature->RetSig == NoFPRet)
1102 // llvm_unreachable("should not be any stubs here with no return value");
1104 EmitInstrReg(*STI, Mips::JR, Mips::S2);
1106 MCSymbol *Tmp = OutContext.createTempSymbol();
1107 OutStreamer->EmitLabel(Tmp);
1108 const MCSymbolRefExpr *E = MCSymbolRefExpr::create(Stub, OutContext);
1109 const MCSymbolRefExpr *T = MCSymbolRefExpr::create(Tmp, OutContext);
1110 const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext);
1111 OutStreamer->emitELFSize(Stub, T_min_E);
1112 TS.emitDirectiveEnd(x);
1113 OutStreamer->PopSection();
1116 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
1117 // Emit needed stubs
1121 const Mips16HardFloatInfo::FuncSignature *>::const_iterator
1122 it = StubsNeeded.begin();
1123 it != StubsNeeded.end(); ++it) {
1124 const char *Symbol = it->first;
1125 const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1126 EmitFPCallStub(Symbol, Signature);
1128 // return to the text section
1129 OutStreamer->SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
1132 void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1133 const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 15 : 11;
1134 // For mips32 we want to emit the following pattern:
1139 // 11 NOP instructions (44 bytes)
1143 // We need the 44 bytes (11 instructions) because at runtime, we'd
1144 // be patching over the full 48 bytes (12 instructions) with the following
1151 // LUI T9, %hi(__xray_FunctionEntry/Exit)
1152 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1153 // LUI T0, %hi(function_id)
1155 // ORI T0, T0, %lo(function_id)
1160 // We add 52 bytes to t9 because we want to adjust the function pointer to
1161 // the actual start of function i.e. the address just after the noop sled.
1162 // We do this because gp displacement relocation is emitted at the start of
1163 // of the function i.e after the nop sled and to correctly calculate the
1164 // global offset table address, t9 must hold the address of the instruction
1165 // containing the gp displacement relocation.
1166 // FIXME: Is this correct for the static relocation model?
1168 // For mips64 we want to emit the following pattern:
1173 // 15 NOP instructions (60 bytes)
1176 // We need the 60 bytes (15 instructions) because at runtime, we'd
1177 // be patching over the full 64 bytes (16 instructions) with the following
1180 // DADDIU SP, SP, -16
1184 // LUI T9, %highest(__xray_FunctionEntry/Exit)
1185 // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1187 // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1189 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1190 // LUI T0, %hi(function_id)
1192 // ADDIU T0, T0, %lo(function_id)
1195 // DADDIU SP, SP, 16
1197 OutStreamer->EmitCodeAlignment(4);
1198 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1199 OutStreamer->EmitLabel(CurSled);
1200 auto Target = OutContext.createTempSymbol();
1202 // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1203 // start of function
1204 const MCExpr *TargetExpr = MCSymbolRefExpr::create(
1205 Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext);
1206 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
1209 .addExpr(TargetExpr));
1211 for (int8_t I = 0; I < NoopsInSledCount; I++)
1212 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
1217 OutStreamer->EmitLabel(Target);
1219 if (!Subtarget->isGP64bit()) {
1220 EmitToStreamer(*OutStreamer,
1221 MCInstBuilder(Mips::ADDiu)
1227 recordSled(CurSled, MI, Kind);
1230 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) {
1231 EmitSled(MI, SledKind::FUNCTION_ENTER);
1234 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
1235 EmitSled(MI, SledKind::FUNCTION_EXIT);
1238 void MipsAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
1239 EmitSled(MI, SledKind::TAIL_CALL);
1242 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1247 // Emit .dtprelword or .dtpreldword directive
1248 // and value for debug thread local expression.
1249 void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const {
1250 if (auto *MipsExpr = dyn_cast<MipsMCExpr>(Value)) {
1251 if (MipsExpr && MipsExpr->getKind() == MipsMCExpr::MEK_DTPREL) {
1254 OutStreamer->EmitDTPRel32Value(MipsExpr->getSubExpr());
1257 OutStreamer->EmitDTPRel64Value(MipsExpr->getSubExpr());
1260 llvm_unreachable("Unexpected size of expression value.");
1265 AsmPrinter::EmitDebugValue(Value, Size);
1268 // Align all targets of indirect branches on bundle size. Used only if target
1270 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1271 // Align all blocks that are jumped to through jump table.
1272 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1273 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1274 for (unsigned I = 0; I < JT.size(); ++I) {
1275 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1277 for (unsigned J = 0; J < MBBs.size(); ++J)
1278 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1282 // If basic block address is taken, block can be target of indirect branch.
1283 for (auto &MBB : MF) {
1284 if (MBB.hasAddressTaken())
1285 MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1289 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1290 return (Opcode == Mips::LONG_BRANCH_LUi
1291 || Opcode == Mips::LONG_BRANCH_LUi2Op
1292 || Opcode == Mips::LONG_BRANCH_LUi2Op_64
1293 || Opcode == Mips::LONG_BRANCH_ADDiu
1294 || Opcode == Mips::LONG_BRANCH_ADDiu2Op
1295 || Opcode == Mips::LONG_BRANCH_DADDiu
1296 || Opcode == Mips::LONG_BRANCH_DADDiu2Op);
1299 // Force static initialization.
1300 extern "C" void LLVMInitializeMipsAsmPrinter() {
1301 RegisterAsmPrinter<MipsAsmPrinter> X(getTheMipsTarget());
1302 RegisterAsmPrinter<MipsAsmPrinter> Y(getTheMipselTarget());
1303 RegisterAsmPrinter<MipsAsmPrinter> A(getTheMips64Target());
1304 RegisterAsmPrinter<MipsAsmPrinter> B(getTheMips64elTarget());