1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "MipsAsmPrinter.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MCTargetDesc/MipsMCNaCl.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetMachine.h"
23 #include "MipsTargetStreamer.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/BinaryFormat/ELF.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/IR/BasicBlock.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/InlineAsm.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/Mangler.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCSection.h"
45 #include "llvm/MC/MCSectionELF.h"
46 #include "llvm/MC/MCSymbolELF.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
55 #define DEBUG_TYPE "mips-asm-printer"
57 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
58 return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
61 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
62 Subtarget = &MF.getSubtarget<MipsSubtarget>();
64 MipsFI = MF.getInfo<MipsFunctionInfo>();
65 if (Subtarget->inMips16Mode())
68 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
69 it = MipsFI->StubsNeeded.begin();
70 it != MipsFI->StubsNeeded.end(); ++it) {
71 const char *Symbol = it->first;
72 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
73 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
74 StubsNeeded[Symbol] = Signature;
76 MCP = MF.getConstantPool();
78 // In NaCl, all indirect jump targets must be aligned to bundle size.
79 if (Subtarget->isTargetNaCl())
80 NaClAlignIndirectJumpTargets(MF);
82 AsmPrinter::runOnMachineFunction(MF);
89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
90 MCOp = MCInstLowering.LowerOperand(MO);
91 return MCOp.isValid();
94 #include "MipsGenMCPseudoLowering.inc"
96 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
97 // JALR, or JALR64 as appropriate for the target
98 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
99 const MachineInstr *MI) {
100 bool HasLinkReg = false;
101 bool InMicroMipsMode = Subtarget->inMicroMipsMode();
104 if (Subtarget->hasMips64r6()) {
105 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
106 TmpInst0.setOpcode(Mips::JALR64);
108 } else if (Subtarget->hasMips32r6()) {
109 // MIPS32r6 should use (JALR ZERO, $rs)
111 TmpInst0.setOpcode(Mips::JRC16_MMR6);
113 TmpInst0.setOpcode(Mips::JALR);
116 } else if (Subtarget->inMicroMipsMode())
117 // microMIPS should use (JR_MM $rs)
118 TmpInst0.setOpcode(Mips::JR_MM);
120 // Everything else should use (JR $rs)
121 TmpInst0.setOpcode(Mips::JR);
127 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
128 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
131 lowerOperand(MI->getOperand(0), MCOp);
132 TmpInst0.addOperand(MCOp);
134 EmitToStreamer(OutStreamer, TmpInst0);
137 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
138 MipsTargetStreamer &TS = getTargetStreamer();
139 unsigned Opc = MI->getOpcode();
140 TS.forbidModuleDirective();
142 if (MI->isDebugValue()) {
143 SmallString<128> Str;
144 raw_svector_ostream OS(Str);
146 PrintDebugValueComment(MI, OS);
150 // If we just ended a constant pool, mark it as such.
151 if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
152 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
153 InConstantPool = false;
155 if (Opc == Mips::CONSTPOOL_ENTRY) {
156 // CONSTPOOL_ENTRY - This instruction represents a floating
157 // constant pool in the function. The first operand is the ID#
158 // for this instruction, the second is the index into the
159 // MachineConstantPool that this is, the third is the size in
160 // bytes of this constant pool entry.
161 // The required alignment is specified on the basic block holding this MI.
163 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
164 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
166 // If this is the first entry of the pool, mark it.
167 if (!InConstantPool) {
168 OutStreamer->EmitDataRegion(MCDR_DataRegion);
169 InConstantPool = true;
172 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
174 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
175 if (MCPE.isMachineConstantPoolEntry())
176 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
178 EmitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal);
183 case Mips::PATCHABLE_FUNCTION_ENTER:
184 LowerPATCHABLE_FUNCTION_ENTER(*MI);
186 case Mips::PATCHABLE_FUNCTION_EXIT:
187 LowerPATCHABLE_FUNCTION_EXIT(*MI);
189 case Mips::PATCHABLE_TAIL_CALL:
190 LowerPATCHABLE_TAIL_CALL(*MI);
194 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
195 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
198 // Do any auto-generated pseudo lowerings.
199 if (emitPseudoExpansionLowering(*OutStreamer, &*I))
202 if (I->getOpcode() == Mips::PseudoReturn ||
203 I->getOpcode() == Mips::PseudoReturn64 ||
204 I->getOpcode() == Mips::PseudoIndirectBranch ||
205 I->getOpcode() == Mips::PseudoIndirectBranch64 ||
206 I->getOpcode() == Mips::TAILCALLREG ||
207 I->getOpcode() == Mips::TAILCALLREG64) {
208 emitPseudoIndirectBranch(*OutStreamer, &*I);
212 // The inMips16Mode() test is not permanent.
213 // Some instructions are marked as pseudo right now which
214 // would make the test fail for the wrong reason but
215 // that will be fixed soon. We need this here because we are
216 // removing another test for this situation downstream in the
219 if (I->isPseudo() && !Subtarget->inMips16Mode()
220 && !isLongBranchPseudo(I->getOpcode()))
221 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
224 MCInstLowering.Lower(&*I, TmpInst0);
225 EmitToStreamer(*OutStreamer, TmpInst0);
226 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
229 //===----------------------------------------------------------------------===//
231 // Mips Asm Directives
233 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
234 // Describe the stack frame.
236 // -- Mask directives "(f)mask bitmask, offset"
237 // Tells the assembler which registers are saved and where.
238 // bitmask - contain a little endian bitset indicating which registers are
239 // saved on function prologue (e.g. with a 0x80000000 mask, the
240 // assembler knows the register 31 (RA) is saved at prologue.
241 // offset - the position before stack pointer subtraction indicating where
242 // the first saved register on prologue is located. (e.g. with a
244 // Consider the following function prologue:
247 // .mask 0xc0000000,-8
248 // addiu $sp, $sp, -48
252 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
253 // 30 (FP) are saved at prologue. As the save order on prologue is from
254 // left to right, RA is saved first. A -8 offset means that after the
255 // stack pointer subtration, the first register in the mask (RA) will be
256 // saved at address 48-8=40.
258 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 //===----------------------------------------------------------------------===//
264 // Create a bitmask with all callee saved registers for CPU or Floating Point
265 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
266 void MipsAsmPrinter::printSavedRegsBitmask() {
267 // CPU and FPU Saved Registers Bitmasks
268 unsigned CPUBitmask = 0, FPUBitmask = 0;
269 int CPUTopSavedRegOff, FPUTopSavedRegOff;
271 // Set the CPU and FPU Bitmasks
272 const MachineFrameInfo &MFI = MF->getFrameInfo();
273 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
274 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
275 // size of stack area to which FP callee-saved regs are saved.
276 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
277 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
278 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
279 bool HasAFGR64Reg = false;
280 unsigned CSFPRegsSize = 0;
282 for (const auto &I : CSI) {
283 unsigned Reg = I.getReg();
284 unsigned RegNum = TRI->getEncodingValue(Reg);
286 // If it's a floating point register, set the FPU Bitmask.
287 // If it's a general purpose register, set the CPU Bitmask.
288 if (Mips::FGR32RegClass.contains(Reg)) {
289 FPUBitmask |= (1 << RegNum);
290 CSFPRegsSize += FGR32RegSize;
291 } else if (Mips::AFGR64RegClass.contains(Reg)) {
292 FPUBitmask |= (3 << RegNum);
293 CSFPRegsSize += AFGR64RegSize;
295 } else if (Mips::GPR32RegClass.contains(Reg))
296 CPUBitmask |= (1 << RegNum);
299 // FP Regs are saved right below where the virtual frame pointer points to.
300 FPUTopSavedRegOff = FPUBitmask ?
301 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
303 // CPU Regs are saved below FP Regs.
304 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
306 MipsTargetStreamer &TS = getTargetStreamer();
308 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
311 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
314 //===----------------------------------------------------------------------===//
315 // Frame and Set directives
316 //===----------------------------------------------------------------------===//
319 void MipsAsmPrinter::emitFrameDirective() {
320 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
322 unsigned stackReg = RI.getFrameRegister(*MF);
323 unsigned returnReg = RI.getRARegister();
324 unsigned stackSize = MF->getFrameInfo().getStackSize();
326 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
329 /// Emit Set directives.
330 const char *MipsAsmPrinter::getCurrentABIString() const {
331 switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
332 case MipsABIInfo::ABI::O32: return "abi32";
333 case MipsABIInfo::ABI::N32: return "abiN32";
334 case MipsABIInfo::ABI::N64: return "abi64";
335 default: llvm_unreachable("Unknown Mips ABI");
339 void MipsAsmPrinter::EmitFunctionEntryLabel() {
340 MipsTargetStreamer &TS = getTargetStreamer();
342 // NaCl sandboxing requires that indirect call instructions are masked.
343 // This means that function entry points should be bundle-aligned.
344 if (Subtarget->isTargetNaCl())
345 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
347 if (Subtarget->inMicroMipsMode()) {
348 TS.emitDirectiveSetMicroMips();
349 TS.setUsesMicroMips();
351 TS.emitDirectiveSetNoMicroMips();
353 if (Subtarget->inMips16Mode())
354 TS.emitDirectiveSetMips16();
356 TS.emitDirectiveSetNoMips16();
358 TS.emitDirectiveEnt(*CurrentFnSym);
359 OutStreamer->EmitLabel(CurrentFnSym);
362 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
363 /// the first basic block in the function.
364 void MipsAsmPrinter::EmitFunctionBodyStart() {
365 MipsTargetStreamer &TS = getTargetStreamer();
367 MCInstLowering.Initialize(&MF->getContext());
369 bool IsNakedFunction = MF->getFunction()->hasFnAttribute(Attribute::Naked);
370 if (!IsNakedFunction)
371 emitFrameDirective();
373 if (!IsNakedFunction)
374 printSavedRegsBitmask();
376 if (!Subtarget->inMips16Mode()) {
377 TS.emitDirectiveSetNoReorder();
378 TS.emitDirectiveSetNoMacro();
379 TS.emitDirectiveSetNoAt();
383 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
384 /// the last basic block in the function.
385 void MipsAsmPrinter::EmitFunctionBodyEnd() {
386 MipsTargetStreamer &TS = getTargetStreamer();
388 // There are instruction for this macros, but they must
389 // always be at the function end, and we can't emit and
390 // break with BB logic.
391 if (!Subtarget->inMips16Mode()) {
392 TS.emitDirectiveSetAt();
393 TS.emitDirectiveSetMacro();
394 TS.emitDirectiveSetReorder();
396 TS.emitDirectiveEnd(CurrentFnSym->getName());
397 // Make sure to terminate any constant pools that were at the end
401 InConstantPool = false;
402 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
405 void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) {
406 MipsTargetStreamer &TS = getTargetStreamer();
408 TS.emitDirectiveInsn();
411 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
412 /// exactly one predecessor and the control transfer mechanism between
413 /// the predecessor and this block is a fall-through.
414 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
416 // The predecessor has to be immediately before this block.
417 const MachineBasicBlock *Pred = *MBB->pred_begin();
419 // If the predecessor is a switch statement, assume a jump table
420 // implementation, so it is not a fall through.
421 if (const BasicBlock *bb = Pred->getBasicBlock())
422 if (isa<SwitchInst>(bb->getTerminator()))
425 // If this is a landing pad, it isn't a fall through. If it has no preds,
426 // then nothing falls through to it.
427 if (MBB->isEHPad() || MBB->pred_empty())
430 // If there isn't exactly one predecessor, it can't be a fall through.
431 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
434 if (PI2 != MBB->pred_end())
437 // The predecessor has to be immediately before this block.
438 if (!Pred->isLayoutSuccessor(MBB))
441 // If the block is completely empty, then it definitely does fall through.
445 // Otherwise, check the last instruction.
446 // Check if the last terminator is an unconditional branch.
447 MachineBasicBlock::const_iterator I = Pred->end();
448 while (I != Pred->begin() && !(--I)->isTerminator()) ;
450 return !I->isBarrier();
453 // Print out an operand for an inline asm expression.
454 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
455 unsigned AsmVariant, const char *ExtraCode,
457 // Does this asm operand have a single letter operand modifier?
458 if (ExtraCode && ExtraCode[0]) {
459 if (ExtraCode[1] != 0) return true; // Unknown modifier.
461 const MachineOperand &MO = MI->getOperand(OpNum);
462 switch (ExtraCode[0]) {
464 // See if this is a generic print operand
465 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
466 case 'X': // hex const int
467 if ((MO.getType()) != MachineOperand::MO_Immediate)
469 O << "0x" << Twine::utohexstr(MO.getImm());
471 case 'x': // hex const int (low 16 bits)
472 if ((MO.getType()) != MachineOperand::MO_Immediate)
474 O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
476 case 'd': // decimal const int
477 if ((MO.getType()) != MachineOperand::MO_Immediate)
481 case 'm': // decimal const int minus 1
482 if ((MO.getType()) != MachineOperand::MO_Immediate)
484 O << MO.getImm() - 1;
487 // $0 if zero, regular printing otherwise
488 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
492 // If not, call printOperand as normal.
495 case 'D': // Second part of a double word register operand
496 case 'L': // Low order register of a double word register operand
497 case 'M': // High order register of a double word register operand
501 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
502 if (!FlagsOP.isImm())
504 unsigned Flags = FlagsOP.getImm();
505 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
506 // Number of registers represented by this operand. We are looking
507 // for 2 for 32 bit mode and 1 for 64 bit mode.
509 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
510 unsigned Reg = MO.getReg();
511 O << '$' << MipsInstPrinter::getRegisterName(Reg);
517 unsigned RegOp = OpNum;
518 if (!Subtarget->isGP64bit()){
519 // Endianness reverses which register holds the high or low value
521 switch(ExtraCode[0]) {
523 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
526 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
528 case 'D': // Always the second part
531 if (RegOp >= MI->getNumOperands())
533 const MachineOperand &MO = MI->getOperand(RegOp);
536 unsigned Reg = MO.getReg();
537 O << '$' << MipsInstPrinter::getRegisterName(Reg);
542 // Print MSA registers for the 'f' constraint
543 // In LLVM, the 'w' modifier doesn't need to do anything.
544 // We can just call printOperand as normal.
549 printOperand(MI, OpNum, O);
553 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
554 unsigned OpNum, unsigned AsmVariant,
555 const char *ExtraCode,
557 assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
558 const MachineOperand &BaseMO = MI->getOperand(OpNum);
559 const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
560 assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
561 assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
562 int Offset = OffsetMO.getImm();
564 // Currently we are expecting either no ExtraCode or 'D'
566 if (ExtraCode[0] == 'D')
569 return true; // Unknown modifier.
570 // FIXME: M = high order bits
571 // FIXME: L = low order bits
574 O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")";
579 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
581 const MachineOperand &MO = MI->getOperand(opNum);
584 if (MO.getTargetFlags())
587 switch(MO.getTargetFlags()) {
588 case MipsII::MO_GPREL: O << "%gp_rel("; break;
589 case MipsII::MO_GOT_CALL: O << "%call16("; break;
590 case MipsII::MO_GOT: O << "%got("; break;
591 case MipsII::MO_ABS_HI: O << "%hi("; break;
592 case MipsII::MO_ABS_LO: O << "%lo("; break;
593 case MipsII::MO_HIGHER: O << "%higher("; break;
594 case MipsII::MO_HIGHEST: O << "%highest(("; break;
595 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
596 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
597 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
598 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
599 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
600 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
601 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
602 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
603 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
606 switch (MO.getType()) {
607 case MachineOperand::MO_Register:
609 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
612 case MachineOperand::MO_Immediate:
616 case MachineOperand::MO_MachineBasicBlock:
617 MO.getMBB()->getSymbol()->print(O, MAI);
620 case MachineOperand::MO_GlobalAddress:
621 getSymbol(MO.getGlobal())->print(O, MAI);
624 case MachineOperand::MO_BlockAddress: {
625 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
630 case MachineOperand::MO_ConstantPoolIndex:
631 O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
632 << getFunctionNumber() << "_" << MO.getIndex();
634 O << "+" << MO.getOffset();
638 llvm_unreachable("<unknown operand type>");
641 if (closeP) O << ")";
644 void MipsAsmPrinter::
645 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
646 // Load/Store memory operands -- imm($reg)
647 // If PIC target the target is loaded as the
648 // pattern lw $25,%call16($28)
650 // opNum can be invalid if instruction has reglist as operand.
651 // MemOperand is always last operand of instruction (base + offset).
652 switch (MI->getOpcode()) {
657 opNum = MI->getNumOperands() - 2;
661 printOperand(MI, opNum+1, O);
663 printOperand(MI, opNum, O);
667 void MipsAsmPrinter::
668 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
669 // when using stack locations for not load/store instructions
670 // print the same way as all normal 3 operand instructions.
671 printOperand(MI, opNum, O);
673 printOperand(MI, opNum+1, O);
677 void MipsAsmPrinter::
678 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
679 const char *Modifier) {
680 const MachineOperand &MO = MI->getOperand(opNum);
681 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
684 void MipsAsmPrinter::
685 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
686 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
687 if (i != opNum) O << ", ";
688 printOperand(MI, i, O);
692 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
693 MipsTargetStreamer &TS = getTargetStreamer();
695 // MipsTargetStreamer has an initialization order problem when emitting an
696 // object file directly (see MipsTargetELFStreamer for full details). Work
697 // around it by re-initializing the PIC state here.
698 TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent());
700 // Compute MIPS architecture attributes based on the default subtarget
701 // that we'd have constructed. Module level directives aren't LTO
703 // FIXME: For ifunc related functions we could iterate over and look
704 // for a feature string that doesn't match the default one.
705 const Triple &TT = TM.getTargetTriple();
706 StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
707 StringRef FS = TM.getTargetFeatureString();
708 const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
709 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
711 bool IsABICalls = STI.isABICalls();
712 const MipsABIInfo &ABI = MTM.getABI();
714 TS.emitDirectiveAbiCalls();
715 // FIXME: This condition should be a lot more complicated that it is here.
716 // Ideally it should test for properties of the ABI and not the ABI
718 // For the moment, I'm only correcting enough to make MIPS-IV work.
719 if (!isPositionIndependent() && STI.hasSym32())
720 TS.emitDirectiveOptionPic0();
723 // Tell the assembler which ABI we are using
724 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
725 OutStreamer->SwitchSection(
726 OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
728 // NaN: At the moment we only support:
729 // 1. .nan legacy (default)
731 STI.isNaN2008() ? TS.emitDirectiveNaN2008()
732 : TS.emitDirectiveNaNLegacy();
734 // TODO: handle O64 ABI
736 TS.updateABIInfo(STI);
738 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
739 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
740 // -mfp64) and omit it otherwise.
741 if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
742 TS.emitDirectiveModuleFP();
744 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
745 // accept it. We therefore emit it when it contradicts the default or an
746 // option has changed the default (i.e. FPXX) and omit it otherwise.
747 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
748 TS.emitDirectiveModuleOddSPReg();
751 void MipsAsmPrinter::emitInlineAsmStart() const {
752 MipsTargetStreamer &TS = getTargetStreamer();
754 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
755 // and 'reorder') is different from LLVM's choice for generated code ('noat',
756 // 'nomacro' and 'noreorder').
757 // In order to maintain compatibility with inline assembly code which depends
758 // on GCC's assembler options being used, we have to switch to those options
759 // for the duration of the inline assembly block and then switch back.
760 TS.emitDirectiveSetPush();
761 TS.emitDirectiveSetAt();
762 TS.emitDirectiveSetMacro();
763 TS.emitDirectiveSetReorder();
764 OutStreamer->AddBlankLine();
767 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
768 const MCSubtargetInfo *EndInfo) const {
769 OutStreamer->AddBlankLine();
770 getTargetStreamer().emitDirectiveSetPop();
773 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
775 I.setOpcode(Mips::JAL);
777 MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext)));
778 OutStreamer->EmitInstruction(I, STI);
781 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
785 I.addOperand(MCOperand::createReg(Reg));
786 OutStreamer->EmitInstruction(I, STI);
789 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
790 unsigned Opcode, unsigned Reg1,
794 // Because of the current td files for Mips32, the operands for MTC1
795 // appear backwards from their normal assembly order. It's not a trivial
796 // change to fix this in the td file so we adjust for it here.
798 if (Opcode == Mips::MTC1) {
799 unsigned Temp = Reg1;
804 I.addOperand(MCOperand::createReg(Reg1));
805 I.addOperand(MCOperand::createReg(Reg2));
806 OutStreamer->EmitInstruction(I, STI);
809 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
810 unsigned Opcode, unsigned Reg1,
811 unsigned Reg2, unsigned Reg3) {
814 I.addOperand(MCOperand::createReg(Reg1));
815 I.addOperand(MCOperand::createReg(Reg2));
816 I.addOperand(MCOperand::createReg(Reg3));
817 OutStreamer->EmitInstruction(I, STI);
820 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
821 unsigned MovOpc, unsigned Reg1,
822 unsigned Reg2, unsigned FPReg1,
823 unsigned FPReg2, bool LE) {
825 unsigned temp = Reg1;
829 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
830 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
833 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
834 Mips16HardFloatInfo::FPParamVariant PV,
835 bool LE, bool ToFP) {
836 using namespace Mips16HardFloatInfo;
837 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
840 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
843 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
846 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
847 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
850 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
853 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
854 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
857 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
858 EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
865 void MipsAsmPrinter::EmitSwapFPIntRetval(
866 const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
868 using namespace Mips16HardFloatInfo;
869 unsigned MovOpc = Mips::MFC1;
872 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
875 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
878 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
881 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
882 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
889 void MipsAsmPrinter::EmitFPCallStub(
890 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
891 MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
892 using namespace Mips16HardFloatInfo;
893 bool LE = getDataLayout().isLittleEndian();
894 // Construct a local MCSubtargetInfo here.
895 // This is because the MachineFunction won't exist (but have not yet been
896 // freed) and since we're at the global level we can use the default
897 // constructed subtarget.
898 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
899 TM.getTargetTriple().str(), TM.getTargetCPU(),
900 TM.getTargetFeatureString()));
905 OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
908 // make the comment field identifying the return and parameter
909 // types of the floating point stub
910 // # Stub function to call rettype xxxx (params)
912 switch (Signature->RetSig) {
923 RetType = "double complex";
930 switch (Signature->ParamSig) {
935 Parms = "float, float";
938 Parms = "float, double";
944 Parms = "double, double";
947 Parms = "double, float";
953 OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " +
954 Twine(Symbol) + " (" + Twine(Parms) + ")");
956 // probably not necessary but we save and restore the current section state
958 OutStreamer->PushSection();
960 // .section mips16.call.fpxxxx,"ax",@progbits
962 MCSectionELF *M = OutContext.getELFSection(
963 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
964 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR);
965 OutStreamer->SwitchSection(M, nullptr);
969 OutStreamer->EmitValueToAlignment(4);
970 MipsTargetStreamer &TS = getTargetStreamer();
975 TS.emitDirectiveSetNoMips16();
976 TS.emitDirectiveSetNoMicroMips();
978 // .ent __call_stub_fp_xxxx
979 // .type __call_stub_fp_xxxx,@function
980 // __call_stub_fp_xxxx:
982 std::string x = "__call_stub_fp_" + std::string(Symbol);
984 cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x)));
985 TS.emitDirectiveEnt(*Stub);
987 OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
988 OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
989 OutStreamer->EmitLabel(Stub);
991 // Only handle non-pic for now.
992 assert(!isPositionIndependent() &&
993 "should not be here if we are compiling pic");
994 TS.emitDirectiveSetReorder();
996 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
997 // stubs without raw text but this current patch is for compiler generated
998 // functions and they all return some value.
999 // The calling sequence for non pic is different in that case and we need
1000 // to implement %lo and %hi in order to handle the case of no return value
1001 // See the corresponding method in Mips16HardFloat for details.
1003 // mov the return address to S2.
1004 // we have no stack space to store it and we are about to make another call.
1005 // We need to make sure that the enclosing function knows to save S2
1006 // This should have already been handled.
1010 EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1012 EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
1016 EmitJal(*STI, MSymbol);
1018 // fix return values
1019 EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1022 // if (Signature->RetSig == NoFPRet)
1023 // llvm_unreachable("should not be any stubs here with no return value");
1025 EmitInstrReg(*STI, Mips::JR, Mips::S2);
1027 MCSymbol *Tmp = OutContext.createTempSymbol();
1028 OutStreamer->EmitLabel(Tmp);
1029 const MCSymbolRefExpr *E = MCSymbolRefExpr::create(Stub, OutContext);
1030 const MCSymbolRefExpr *T = MCSymbolRefExpr::create(Tmp, OutContext);
1031 const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext);
1032 OutStreamer->emitELFSize(Stub, T_min_E);
1033 TS.emitDirectiveEnd(x);
1034 OutStreamer->PopSection();
1037 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
1038 // Emit needed stubs
1042 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1043 it = StubsNeeded.begin();
1044 it != StubsNeeded.end(); ++it) {
1045 const char *Symbol = it->first;
1046 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1047 EmitFPCallStub(Symbol, Signature);
1049 // return to the text section
1050 OutStreamer->SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
1053 void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1054 const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 15 : 11;
1055 // For mips32 we want to emit the following pattern:
1060 // 11 NOP instructions (44 bytes)
1064 // We need the 44 bytes (11 instructions) because at runtime, we'd
1065 // be patching over the full 48 bytes (12 instructions) with the following
1072 // LUI T9, %hi(__xray_FunctionEntry/Exit)
1073 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1074 // LUI T0, %hi(function_id)
1076 // ORI T0, T0, %lo(function_id)
1081 // We add 52 bytes to t9 because we want to adjust the function pointer to
1082 // the actual start of function i.e. the address just after the noop sled.
1083 // We do this because gp displacement relocation is emitted at the start of
1084 // of the function i.e after the nop sled and to correctly calculate the
1085 // global offset table address, t9 must hold the address of the instruction
1086 // containing the gp displacement relocation.
1087 // FIXME: Is this correct for the static relocation model?
1089 // For mips64 we want to emit the following pattern:
1094 // 15 NOP instructions (60 bytes)
1097 // We need the 60 bytes (15 instructions) because at runtime, we'd
1098 // be patching over the full 64 bytes (16 instructions) with the following
1101 // DADDIU SP, SP, -16
1105 // LUI T9, %highest(__xray_FunctionEntry/Exit)
1106 // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1108 // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1110 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1111 // LUI T0, %hi(function_id)
1113 // ADDIU T0, T0, %lo(function_id)
1116 // DADDIU SP, SP, 16
1118 OutStreamer->EmitCodeAlignment(4);
1119 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1120 OutStreamer->EmitLabel(CurSled);
1121 auto Target = OutContext.createTempSymbol();
1123 // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1124 // start of function
1125 const MCExpr *TargetExpr = MCSymbolRefExpr::create(
1126 Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext);
1127 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
1130 .addExpr(TargetExpr));
1132 for (int8_t I = 0; I < NoopsInSledCount; I++)
1133 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
1138 OutStreamer->EmitLabel(Target);
1140 if (!Subtarget->isGP64bit()) {
1141 EmitToStreamer(*OutStreamer,
1142 MCInstBuilder(Mips::ADDiu)
1148 recordSled(CurSled, MI, Kind);
1151 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) {
1152 EmitSled(MI, SledKind::FUNCTION_ENTER);
1155 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
1156 EmitSled(MI, SledKind::FUNCTION_EXIT);
1159 void MipsAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
1160 EmitSled(MI, SledKind::TAIL_CALL);
1163 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1168 // Emit .dtprelword or .dtpreldword directive
1169 // and value for debug thread local expression.
1170 void MipsAsmPrinter::EmitDebugThreadLocal(const MCExpr *Value,
1171 unsigned Size) const {
1174 OutStreamer->EmitDTPRel32Value(Value);
1177 OutStreamer->EmitDTPRel64Value(Value);
1180 llvm_unreachable("Unexpected size of expression value.");
1184 // Align all targets of indirect branches on bundle size. Used only if target
1186 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1187 // Align all blocks that are jumped to through jump table.
1188 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1189 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1190 for (unsigned I = 0; I < JT.size(); ++I) {
1191 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1193 for (unsigned J = 0; J < MBBs.size(); ++J)
1194 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1198 // If basic block address is taken, block can be target of indirect branch.
1199 for (auto &MBB : MF) {
1200 if (MBB.hasAddressTaken())
1201 MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1205 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1206 return (Opcode == Mips::LONG_BRANCH_LUi
1207 || Opcode == Mips::LONG_BRANCH_ADDiu
1208 || Opcode == Mips::LONG_BRANCH_DADDiu);
1211 // Force static initialization.
1212 extern "C" void LLVMInitializeMipsAsmPrinter() {
1213 RegisterAsmPrinter<MipsAsmPrinter> X(getTheMipsTarget());
1214 RegisterAsmPrinter<MipsAsmPrinter> Y(getTheMipselTarget());
1215 RegisterAsmPrinter<MipsAsmPrinter> A(getTheMips64Target());
1216 RegisterAsmPrinter<MipsAsmPrinter> B(getTheMips64elTarget());