1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
20 // The inverse of CCIfSubtarget
21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
23 /// Match if the original argument (before lowering) was a float.
24 /// For example, this is true for i32's that were lowered from soft-float.
25 class CCIfOrigArgWasNotFloat<CCAction A>
26 : CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)",
29 /// Match if the original argument (before lowering) was a 128-bit float (i.e.
31 class CCIfOrigArgWasF128<CCAction A>
32 : CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", A>;
34 /// Match if this specific argument is a vararg.
35 /// This is slightly different fro CCIfIsVarArg which matches if any argument is
37 class CCIfArgIsVarArg<CCAction A>
38 : CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>;
41 /// Match if the special calling conv is the specified value.
42 class CCIfSpecialCallingConv<string CC, CCAction A>
43 : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "
44 "MipsCCState::" # CC, A>;
46 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
47 def RetCC_F128SoftFloat : CallingConv<[
48 CCAssignToReg<[V0_64, A0_64]>
51 // For hard-float, f128 values are returned as a pair of f64's rather than a
53 def RetCC_F128HardFloat : CallingConv<[
54 CCBitConvertToType<f64>,
56 // Contrary to the ABI documentation, a struct containing a long double is
57 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
58 // match the de facto ABI as implemented by GCC.
59 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,
61 CCAssignToReg<[D0_64, D2_64]>
64 // Handle F128 specially since we can't identify the original type during the
65 // tablegen-erated code.
66 def RetCC_F128 : CallingConv<[
67 CCIfSubtarget<"useSoftFloat()",
68 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
69 CCIfSubtargetNot<"useSoftFloat()",
70 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
73 //===----------------------------------------------------------------------===//
74 // Mips O32 Calling Convention
75 //===----------------------------------------------------------------------===//
77 def CC_MipsO32 : CallingConv<[
78 // Promote i8/i16 arguments to i32.
79 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
81 // Integer values get stored in stack slots that are 4 bytes in
82 // size and 4-byte aligned.
83 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
85 // Integer values get stored in stack slots that are 8 bytes in
86 // size and 8-byte aligned.
87 CCIfType<[f64], CCAssignToStack<8, 8>>
90 // Only the return rules are defined here for O32. The rules for argument
91 // passing are defined in MipsISelLowering.cpp.
92 def RetCC_MipsO32 : CallingConv<[
93 // Promote i1/i8/i16 return values to i32.
94 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
96 // i32 are returned in registers V0, V1, A0, A1
97 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
99 // f32 are returned in registers F0, F2
100 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
102 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
103 // in D0 and D1 in FP32bit mode.
104 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
105 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
108 def CC_MipsO32_FP32 : CustomCallingConv;
109 def CC_MipsO32_FP64 : CustomCallingConv;
111 def CC_MipsO32_FP : CallingConv<[
112 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>,
113 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>
116 //===----------------------------------------------------------------------===//
117 // Mips N32/64 Calling Convention
118 //===----------------------------------------------------------------------===//
120 def CC_MipsN_SoftFloat : CallingConv<[
121 CCAssignToRegWithShadow<[A0, A1, A2, A3,
123 [D12_64, D13_64, D14_64, D15_64,
124 D16_64, D17_64, D18_64, D19_64]>,
125 CCAssignToStack<4, 8>
128 def CC_MipsN : CallingConv<[
129 CCIfType<[i8, i16, i32, i64],
130 CCIfSubtargetNot<"isLittle()",
131 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
133 // All integers (except soft-float integers) are promoted to 64-bit.
134 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
136 // The only i32's we have left are soft-float arguments.
137 CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>,
139 // Integer arguments are passed in integer registers.
140 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
141 T0_64, T1_64, T2_64, T3_64],
142 [D12_64, D13_64, D14_64, D15_64,
143 D16_64, D17_64, D18_64, D19_64]>>,
145 // f32 arguments are passed in single precision FP registers.
146 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
148 [A0_64, A1_64, A2_64, A3_64,
149 T0_64, T1_64, T2_64, T3_64]>>,
151 // f64 arguments are passed in double precision FP registers.
152 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
153 D16_64, D17_64, D18_64, D19_64],
154 [A0_64, A1_64, A2_64, A3_64,
155 T0_64, T1_64, T2_64, T3_64]>>,
157 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
158 CCIfType<[f32], CCAssignToStack<4, 8>>,
159 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
162 // N32/64 variable arguments.
163 // All arguments are passed in integer registers.
164 def CC_MipsN_VarArg : CallingConv<[
165 CCIfType<[i8, i16, i32, i64],
166 CCIfSubtargetNot<"isLittle()",
167 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
169 // All integers are promoted to 64-bit.
170 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
172 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
174 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
175 T0_64, T1_64, T2_64, T3_64]>>,
177 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
178 CCIfType<[f32], CCAssignToStack<4, 8>>,
179 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
182 def RetCC_MipsN : CallingConv<[
183 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
184 // legal and is lowered to i128 which is further lowered to a pair of i64's.
185 // This presents us with a problem for the calling convention since hard-float
186 // still needs to pass them in FPU registers, and soft-float needs to use $v0,
187 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
188 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
189 // whether the result was originally an f128 into the tablegen-erated code.
191 // f128 should only occur for the N64 ABI where long double is 128-bit. On
192 // N32, long double is equivalent to double.
193 CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>,
195 // Aggregate returns are positioned at the lowest address in the slot for
196 // both little and big-endian targets. When passing in registers, this
197 // requires that big-endian targets shift the value into the upper bits.
198 CCIfSubtarget<"isLittle()",
199 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
200 CCIfSubtargetNot<"isLittle()",
201 CCIfType<[i8, i16, i32, i64],
202 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
204 // i64 are returned in registers V0_64, V1_64
205 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
207 // f32 are returned in registers F0, F2
208 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
210 // f64 are returned in registers D0, D2
211 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
214 //===----------------------------------------------------------------------===//
215 // Mips FastCC Calling Convention
216 //===----------------------------------------------------------------------===//
217 def CC_MipsO32_FastCC : CallingConv<[
218 // f64 arguments are passed in double-precision floating pointer registers.
219 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
220 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
222 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
223 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
224 D4_64, D5_64, D6_64, D7_64,
225 D8_64, D9_64, D10_64, D11_64,
226 D12_64, D13_64, D14_64, D15_64,
227 D16_64, D17_64, D18_64,
229 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
230 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
231 D8_64, D10_64, D12_64, D14_64,
234 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
235 CCIfType<[f64], CCAssignToStack<8, 8>>
238 def CC_MipsN_FastCC : CallingConv<[
239 // Integer arguments are passed in integer registers.
240 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
241 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
244 // f64 arguments are passed in double-precision floating pointer registers.
245 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
246 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
247 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
250 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
252 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
255 def CC_Mips_FastCC : CallingConv<[
256 // Handles byval parameters.
257 CCIfByVal<CCPassByVal<4, 4>>,
259 // Promote i8/i16 arguments to i32.
260 CCIfType<[i8, i16], CCPromoteToType<i32>>,
262 // Integer arguments are passed in integer registers. All scratch registers,
263 // except for AT, V0 and T9, are available to be used as argument registers.
264 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
265 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
267 // In NaCl, T6, T7 and T8 are reserved and not available as argument
268 // registers for fastcc. T6 contains the mask for sandboxing control flow
269 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
270 // accesses (loads and stores). T8 contains the thread pointer.
271 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
272 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
274 // f32 arguments are passed in single-precision floating pointer registers.
275 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
276 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
277 F14, F15, F16, F17, F18, F19]>>>,
279 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
280 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
281 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
283 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
284 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
286 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
287 CCDelegateTo<CC_MipsN_FastCC>
290 //===----------------------------------------------------------------------===//
291 // Mips Calling Convention Dispatch
292 //===----------------------------------------------------------------------===//
294 def RetCC_Mips : CallingConv<[
295 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
296 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
297 CCDelegateTo<RetCC_MipsO32>
300 def CC_Mips_ByVal : CallingConv<[
301 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,
302 CCIfByVal<CCPassByVal<8, 8>>
305 def CC_Mips16RetHelper : CallingConv<[
306 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
308 // Integer arguments are passed in integer registers.
309 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
312 def CC_Mips_FixedArg : CallingConv<[
313 // Mips16 needs special handling on some functions.
314 CCIf<"State.getCallingConv() != CallingConv::Fast",
315 CCIfSpecialCallingConv<"Mips16RetHelperConv",
316 CCDelegateTo<CC_Mips16RetHelper>>>,
318 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
320 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
321 // f128 is not legal and is lowered to i128 which is further lowered to a pair
323 // This presents us with a problem for the calling convention since hard-float
324 // still needs to pass them in FPU registers. We therefore resort to a
325 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
326 // whether the argument was originally an f128 into the tablegen-erated code.
328 // f128 should only occur for the N64 ABI where long double is 128-bit. On
329 // N32, long double is equivalent to double.
331 CCIfSubtargetNot<"useSoftFloat()",
332 CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>,
334 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
336 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
337 CCDelegateTo<CC_MipsN>
340 def CC_Mips_VarArg : CallingConv<[
341 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
343 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
344 CCDelegateTo<CC_MipsN_VarArg>
347 def CC_Mips : CallingConv<[
348 CCIfVarArg<CCIfArgIsVarArg<CCDelegateTo<CC_Mips_VarArg>>>,
349 CCDelegateTo<CC_Mips_FixedArg>
352 //===----------------------------------------------------------------------===//
353 // Callee-saved register lists.
354 //===----------------------------------------------------------------------===//
356 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
357 (sequence "S%u", 7, 0))>;
359 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
360 (sequence "S%u", 7, 0))> {
361 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
364 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
365 (sequence "S%u", 7, 0))>;
368 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
369 (sequence "S%u", 7, 0))>;
371 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
372 D30_64, RA_64, FP_64, GP_64,
373 (sequence "S%u_64", 7, 0))>;
375 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
376 GP_64, (sequence "S%u_64", 7, 0))>;
378 def CSR_Mips16RetHelper :
379 CalleeSavedRegs<(add V0, V1, FP,
380 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
381 (sequence "D%u", 15, 10))>;
383 def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
384 (sequence "S%u", 7, 0),
385 (sequence "V%u", 1, 0),
386 (sequence "T%u", 9, 0),
389 def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
390 (sequence "S%u", 7, 0),
391 (sequence "V%u", 1, 0),
392 (sequence "T%u", 9, 0),
393 RA, FP, GP, AT, LO0, HI0)>;
395 def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
396 (sequence "V%u_64", 1, 0),
397 (sequence "S%u_64", 7, 0),
398 (sequence "T%u_64", 9, 0),
399 RA_64, FP_64, GP_64, AT_64)>;
401 def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
402 (sequence "S%u_64", 7, 0),
403 (sequence "T%u_64", 9, 0),
404 (sequence "V%u_64", 1, 0),
405 RA_64, FP_64, GP_64, AT_64,