contrib/llvm/lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  22
  23 // Mips-specific dsp nodes
  24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  25                                         SDTCisVT<2, untyped>]>;
  26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  27                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  29                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  31                                              SDTCisVT<2, i32>]>;
  32
  33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  35
  36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  37   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  38
  39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  45
  46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  48
  49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  54
  55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  63
  64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  73
  74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  85
  86 // Flags.
  87 class Uses<list<Register> Regs> {
  88   list<Register> Uses = Regs;
  89 }
  90
  91 class Defs<list<Register> Regs> {
  92   list<Register> Defs = Regs;
  93 }
  94
  95 // Instruction encoding.
  96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 152 class MFHI_ENC : MFHI_FMT<0b010000>;
 153 class MFLO_ENC : MFHI_FMT<0b010010>;
 154 class MTHI_ENC : MTHI_FMT<0b010001>;
 155 class MTLO_ENC : MTHI_FMT<0b010011>;
 156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 181 class REPL_QB_ENC : REPL_FMT<0b00010>;
 182 class REPL_PH_ENC : REPL_FMT<0b01010>;
 183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 187 class LWX_ENC : LX_FMT<0b00000>;
 188 class LHX_ENC : LX_FMT<0b00100>;
 189 class LBUX_ENC : LX_FMT<0b00110>;
 190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 191 class INSV_ENC : INSV_FMT<0b001100>;
 192
 193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 208
 209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 254 class APPEND_ENC : APPEND_FMT<0b00000>;
 255 class BALIGN_ENC : APPEND_FMT<0b10000>;
 256 class PREPEND_ENC : APPEND_FMT<0b00001>;
 257
 258 // Instruction desc.
 259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 260                         InstrItinClass itin, RegisterOperand ROD,
 261                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 262   dag OutOperandList = (outs ROD:$rd);
 263   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 264   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 265   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 266   InstrItinClass Itinerary = itin;
 267   string BaseOpcode = instr_asm;
 268 }
 269
 270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 271                            InstrItinClass itin, RegisterOperand ROD,
 272                            RegisterOperand ROS = ROD> {
 273   dag OutOperandList = (outs ROD:$rd);
 274   dag InOperandList = (ins ROS:$rs);
 275   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 276   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 277   InstrItinClass Itinerary = itin;
 278   string BaseOpcode = instr_asm;
 279 }
 280
 281 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 282                              InstrItinClass itin, RegisterOperand ROS,
 283                              RegisterOperand ROT = ROS> {
 284   dag OutOperandList = (outs);
 285   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 286   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 287   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 288   InstrItinClass Itinerary = itin;
 289   string BaseOpcode = instr_asm;
 290 }
 291
 292 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 293                              InstrItinClass itin, RegisterOperand ROD,
 294                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 295   dag OutOperandList = (outs ROD:$rd);
 296   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 297   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 298   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 299   InstrItinClass Itinerary = itin;
 300   string BaseOpcode = instr_asm;
 301 }
 302
 303 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 304                                InstrItinClass itin, RegisterOperand ROT,
 305                                RegisterOperand ROS = ROT> {
 306   dag OutOperandList = (outs ROT:$rt);
 307   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 308   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 309   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 310   InstrItinClass Itinerary = itin;
 311   string Constraints = "$src = $rt";
 312   string BaseOpcode = instr_asm;
 313 }
 314
 315 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 316                              InstrItinClass itin, RegisterOperand ROD,
 317                              RegisterOperand ROT = ROD> {
 318   dag OutOperandList = (outs ROD:$rd);
 319   dag InOperandList = (ins ROT:$rt);
 320   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 321   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 322   InstrItinClass Itinerary = itin;
 323   string BaseOpcode = instr_asm;
 324 }
 325
 326 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 327                      Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,
 328                      RegisterOperand RO> {
 329   dag OutOperandList = (outs RO:$rd);
 330   dag InOperandList = (ins ImmOp:$imm);
 331   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 332   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 333   InstrItinClass Itinerary = itin;
 334   string BaseOpcode = instr_asm;
 335 }
 336
 337 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 338                            InstrItinClass itin, RegisterOperand RO> {
 339   dag OutOperandList = (outs RO:$rd);
 340   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 341   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 342   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 343   InstrItinClass Itinerary = itin;
 344   string BaseOpcode = instr_asm;
 345 }
 346
 347 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 348                            SDPatternOperator ImmPat, InstrItinClass itin,
 349                            RegisterOperand RO, Operand ImmOpnd> {
 350   dag OutOperandList = (outs RO:$rd);
 351   dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
 352   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 353   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 354   InstrItinClass Itinerary = itin;
 355   bit hasSideEffects = 1;
 356   string BaseOpcode = instr_asm;
 357 }
 358
 359 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 360                    InstrItinClass itin> {
 361   dag OutOperandList = (outs GPR32Opnd:$rd);
 362   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 363   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 364   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 365   InstrItinClass Itinerary = itin;
 366   bit mayLoad = 1;
 367   string BaseOpcode = instr_asm;
 368 }
 369
 370 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 371                          InstrItinClass itin, RegisterOperand ROD,
 372                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 373   dag OutOperandList = (outs ROD:$rd);
 374   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 375   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 376   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 377   InstrItinClass Itinerary = itin;
 378   string BaseOpcode = instr_asm;
 379 }
 380
 381 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 382                        Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
 383   dag OutOperandList = (outs GPR32Opnd:$rt);
 384   dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
 385   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 386   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 387                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
 388   InstrItinClass Itinerary = itin;
 389   string Constraints = "$src = $rt";
 390   string BaseOpcode = instr_asm;
 391 }
 392
 393 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 394                               InstrItinClass itin> {
 395   dag OutOperandList = (outs GPR32Opnd:$rt);
 396   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 397   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 398   InstrItinClass Itinerary = itin;
 399   string BaseOpcode = instr_asm;
 400 }
 401
 402 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 403                               InstrItinClass itin> {
 404   dag OutOperandList = (outs GPR32Opnd:$rt);
 405   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
 406   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 407   InstrItinClass Itinerary = itin;
 408   string BaseOpcode = instr_asm;
 409 }
 410
 411 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 412   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 413   dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin);
 414   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 415   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 416                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 417   string Constraints = "$acin = $ac";
 418   string BaseOpcode = instr_asm;
 419 }
 420
 421 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 422   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 423   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 424   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 425   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 426                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 427   string Constraints = "$acin = $ac";
 428   string BaseOpcode = instr_asm;
 429 }
 430
 431 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 432   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 433   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 434   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 435   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 436                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 437   string Constraints = "$acin = $ac";
 438   string BaseOpcode = instr_asm;
 439 }
 440
 441 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 442                       InstrItinClass itin> {
 443   dag OutOperandList = (outs GPR32Opnd:$rd);
 444   dag InOperandList = (ins uimm10:$mask);
 445   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 446   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 447   InstrItinClass Itinerary = itin;
 448   string BaseOpcode = instr_asm;
 449 }
 450
 451 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 452                       InstrItinClass itin> {
 453   dag OutOperandList = (outs);
 454   dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);
 455   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 456   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 457   InstrItinClass Itinerary = itin;
 458   string BaseOpcode = instr_asm;
 459 }
 460
 461 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 462   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 463   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 464   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 465   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 466                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 467   string Constraints = "$acin = $ac";
 468   string BaseOpcode = instr_asm;
 469 }
 470
 471 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 472                      InstrItinClass itin> {
 473   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 474   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 475   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 476   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 477   InstrItinClass Itinerary = itin;
 478   bit isCommutable = 1;
 479   string BaseOpcode = instr_asm;
 480 }
 481
 482 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 483                      InstrItinClass itin> {
 484   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 485   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 486   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 487   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 488                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 489   InstrItinClass Itinerary = itin;
 490   string Constraints = "$acin = $ac";
 491   string BaseOpcode = instr_asm;
 492 }
 493
 494 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 495                      InstrItinClass itin> {
 496   dag OutOperandList = (outs GPR32Opnd:$rd);
 497   dag InOperandList = (ins RO:$ac);
 498   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 499   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 500   InstrItinClass Itinerary = itin;
 501   string BaseOpcode = instr_asm;
 502 }
 503
 504 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 505   dag OutOperandList = (outs RO:$ac);
 506   dag InOperandList = (ins GPR32Opnd:$rs);
 507   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 508   InstrItinClass Itinerary = itin;
 509   string BaseOpcode = instr_asm;
 510 }
 511
 512 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 513   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 514   bit usesCustomInserter = 1;
 515 }
 516
 517 class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
 518                          InstrItinClass itin> {
 519   dag OutOperandList = (outs);
 520   dag InOperandList = (ins opnd:$offset);
 521   string AsmString = !strconcat(instr_asm, "\t$offset");
 522   InstrItinClass Itinerary = itin;
 523   bit isBranch = 1;
 524   bit isTerminator = 1;
 525   bit hasDelaySlot = 1;
 526   string BaseOpcode = instr_asm;
 527 }
 528
 529 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 530                      InstrItinClass itin> {
 531   dag OutOperandList = (outs GPR32Opnd:$rt);
 532   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 533   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 534   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 535   InstrItinClass Itinerary = itin;
 536   string Constraints = "$src = $rt";
 537   string BaseOpcode = instr_asm;
 538 }
 539
 540 //===----------------------------------------------------------------------===//
 541 // MIPS DSP Rev 1
 542 //===----------------------------------------------------------------------===//
 543
 544 // Addition/subtraction
 545 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 546                                        DSPROpnd, DSPROpnd>, IsCommutable,
 547                      Defs<[DSPOutFlag20]>;
 548
 549 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 550                                          NoItinerary, DSPROpnd, DSPROpnd>,
 551                        IsCommutable, Defs<[DSPOutFlag20]>;
 552
 553 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 554                                        DSPROpnd, DSPROpnd>,
 555                      Defs<[DSPOutFlag20]>;
 556
 557 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 558                                          NoItinerary, DSPROpnd, DSPROpnd>,
 559                        Defs<[DSPOutFlag20]>;
 560
 561 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 562                                        DSPROpnd, DSPROpnd>, IsCommutable,
 563                      Defs<[DSPOutFlag20]>;
 564
 565 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 566                                          NoItinerary, DSPROpnd, DSPROpnd>,
 567                        IsCommutable, Defs<[DSPOutFlag20]>;
 568
 569 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 570                                        DSPROpnd, DSPROpnd>,
 571                      Defs<[DSPOutFlag20]>;
 572
 573 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 574                                          NoItinerary, DSPROpnd, DSPROpnd>,
 575                        Defs<[DSPOutFlag20]>;
 576
 577 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 578                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 579                       IsCommutable, Defs<[DSPOutFlag20]>;
 580
 581 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 582                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 583                       Defs<[DSPOutFlag20]>;
 584
 585 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 586                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 587                    Defs<[DSPCarry]>;
 588
 589 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 590                                      GPR32Opnd, GPR32Opnd>,
 591                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 592
 593 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 594                                       GPR32Opnd, GPR32Opnd>;
 595
 596 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 597                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 598
 599 // Absolute value
 600 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 601                                               NoItinerary, DSPROpnd>,
 602                        Defs<[DSPOutFlag20]>;
 603
 604 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 605                                              NoItinerary, GPR32Opnd>,
 606                       Defs<[DSPOutFlag20]>;
 607
 608 // Precision reduce/expand
 609 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 610                                                  int_mips_precrq_qb_ph,
 611                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 612
 613 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 614                                                 int_mips_precrq_ph_w,
 615                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 616
 617 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 618                                                    int_mips_precrq_rs_ph_w,
 619                                                    NoItinerary, DSPROpnd,
 620                                                    GPR32Opnd>,
 621                             Defs<[DSPOutFlag22]>;
 622
 623 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 624                                                     int_mips_precrqu_s_qb_ph,
 625                                                     NoItinerary, DSPROpnd,
 626                                                     DSPROpnd>,
 627                              Defs<[DSPOutFlag22]>;
 628
 629 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 630                                                  int_mips_preceq_w_phl,
 631                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 632
 633 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 634                                                  int_mips_preceq_w_phr,
 635                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 636
 637 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 638                                                    int_mips_precequ_ph_qbl,
 639                                                    NoItinerary, DSPROpnd>;
 640
 641 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 642                                                    int_mips_precequ_ph_qbr,
 643                                                    NoItinerary, DSPROpnd>;
 644
 645 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 646                                                     int_mips_precequ_ph_qbla,
 647                                                     NoItinerary, DSPROpnd>;
 648
 649 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 650                                                     int_mips_precequ_ph_qbra,
 651                                                     NoItinerary, DSPROpnd>;
 652
 653 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 654                                                   int_mips_preceu_ph_qbl,
 655                                                   NoItinerary, DSPROpnd>;
 656
 657 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 658                                                   int_mips_preceu_ph_qbr,
 659                                                   NoItinerary, DSPROpnd>;
 660
 661 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 662                                                    int_mips_preceu_ph_qbla,
 663                                                    NoItinerary, DSPROpnd>;
 664
 665 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 666                                                    int_mips_preceu_ph_qbra,
 667                                                    NoItinerary, DSPROpnd>;
 668
 669 // Shift
 670 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 671                                           NoItinerary, DSPROpnd, uimm3>,
 672                      Defs<[DSPOutFlag22]>;
 673
 674 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 675                                            NoItinerary, DSPROpnd>,
 676                       Defs<[DSPOutFlag22]>;
 677
 678 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 679                                           NoItinerary, DSPROpnd, uimm3>;
 680
 681 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 682                                            NoItinerary, DSPROpnd>;
 683
 684 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 685                                           NoItinerary, DSPROpnd, uimm4>,
 686                      Defs<[DSPOutFlag22]>;
 687
 688 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 689                                            NoItinerary, DSPROpnd>,
 690                       Defs<[DSPOutFlag22]>;
 691
 692 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 693                                             immZExt4, NoItinerary, DSPROpnd,
 694                                             uimm4>,
 695                        Defs<[DSPOutFlag22]>;
 696
 697 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 698                                              NoItinerary, DSPROpnd>,
 699                         Defs<[DSPOutFlag22]>;
 700
 701 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 702                                           NoItinerary, DSPROpnd, uimm4>;
 703
 704 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 705                                            NoItinerary, DSPROpnd>;
 706
 707 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 708                                             immZExt4, NoItinerary, DSPROpnd,
 709                                             uimm4>;
 710
 711 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 712                                              NoItinerary, DSPROpnd>;
 713
 714 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 715                                            immZExt5, NoItinerary, GPR32Opnd,
 716                                            uimm5>,
 717                       Defs<[DSPOutFlag22]>;
 718
 719 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 720                                             NoItinerary, GPR32Opnd>,
 721                        Defs<[DSPOutFlag22]>;
 722
 723 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 724                                            immZExt5, NoItinerary, GPR32Opnd,
 725                                            uimm5>;
 726
 727 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 728                                             NoItinerary, GPR32Opnd>;
 729
 730 // Multiplication
 731 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 732                                               int_mips_muleu_s_ph_qbl,
 733                                               NoItinerary, DSPROpnd, DSPROpnd>,
 734                             Defs<[DSPOutFlag21]>;
 735
 736 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 737                                               int_mips_muleu_s_ph_qbr,
 738                                               NoItinerary, DSPROpnd, DSPROpnd>,
 739                             Defs<[DSPOutFlag21]>;
 740
 741 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 742                                              int_mips_muleq_s_w_phl,
 743                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 744                            IsCommutable, Defs<[DSPOutFlag21]>;
 745
 746 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 747                                              int_mips_muleq_s_w_phr,
 748                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 749                            IsCommutable, Defs<[DSPOutFlag21]>;
 750
 751 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 752                                           NoItinerary, DSPROpnd, DSPROpnd>,
 753                         IsCommutable, Defs<[DSPOutFlag21]>;
 754
 755 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 756                                               MipsMULSAQ_S_W_PH>,
 757                            Defs<[DSPOutFlag16_19]>;
 758
 759 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 760                          Defs<[DSPOutFlag16_19]>;
 761
 762 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 763                          Defs<[DSPOutFlag16_19]>;
 764
 765 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 766                           Defs<[DSPOutFlag16_19]>;
 767
 768 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 769                           Defs<[DSPOutFlag16_19]>;
 770
 771 // Move from/to hi/lo.
 772 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 773 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 774 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 775 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 776
 777 // Dot product with accumulate/subtract
 778 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 779
 780 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 781
 782 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 783
 784 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 785
 786 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 787                          Defs<[DSPOutFlag16_19]>;
 788
 789 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 790                          Defs<[DSPOutFlag16_19]>;
 791
 792 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 793                          Defs<[DSPOutFlag16_19]>;
 794
 795 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 796                          Defs<[DSPOutFlag16_19]>;
 797
 798 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 799 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 800 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 801 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 802 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 803 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 804
 805 // Comparison
 806 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 807                                                int_mips_cmpu_eq_qb, NoItinerary,
 808                                                DSPROpnd>,
 809                         IsCommutable, Defs<[DSPCCond]>;
 810
 811 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 812                                                int_mips_cmpu_lt_qb, NoItinerary,
 813                                                DSPROpnd>, Defs<[DSPCCond]>;
 814
 815 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 816                                                int_mips_cmpu_le_qb, NoItinerary,
 817                                                DSPROpnd>, Defs<[DSPCCond]>;
 818
 819 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 820                                                 int_mips_cmpgu_eq_qb,
 821                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 822                          IsCommutable;
 823
 824 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 825                                                 int_mips_cmpgu_lt_qb,
 826                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 827
 828 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 829                                                 int_mips_cmpgu_le_qb,
 830                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 831
 832 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 833                                               NoItinerary, DSPROpnd>,
 834                        IsCommutable, Defs<[DSPCCond]>;
 835
 836 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 837                                               NoItinerary, DSPROpnd>,
 838                        Defs<[DSPCCond]>;
 839
 840 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 841                                               NoItinerary, DSPROpnd>,
 842                        Defs<[DSPCCond]>;
 843
 844 // Misc
 845 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 846                                            NoItinerary, GPR32Opnd>;
 847
 848 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 849                                               NoItinerary, DSPROpnd, DSPROpnd>;
 850
 851 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
 852                                     immZExt8, NoItinerary, DSPROpnd>;
 853
 854 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, uimm10,
 855                                     immZExt10, NoItinerary, DSPROpnd>;
 856
 857 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 858                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 859
 860 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 861                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 862
 863 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 864                                             NoItinerary, DSPROpnd, DSPROpnd>,
 865                      Uses<[DSPCCond]>;
 866
 867 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 868                                             NoItinerary, DSPROpnd, DSPROpnd>,
 869                      Uses<[DSPCCond]>;
 870
 871 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 872
 873 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 874
 875 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 876
 877 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
 878
 879 // Extr
 880 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 881                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 882
 883 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 884                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 885
 886 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 887                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 888
 889 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 890                                              NoItinerary>,
 891                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 892
 893 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 894                     Defs<[DSPOutFlag23]>;
 895
 896 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 897                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 898
 899 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 900                                               NoItinerary>,
 901                       Defs<[DSPOutFlag23]>;
 902
 903 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 904                                                NoItinerary>,
 905                        Defs<[DSPOutFlag23]>;
 906
 907 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 908                                                NoItinerary>,
 909                        Defs<[DSPOutFlag23]>;
 910
 911 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 912                                                 NoItinerary>,
 913                         Defs<[DSPOutFlag23]>;
 914
 915 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 916                                               NoItinerary>,
 917                       Defs<[DSPOutFlag23]>;
 918
 919 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 920                                                NoItinerary>,
 921                        Defs<[DSPOutFlag23]>;
 922
 923 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 924
 925 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 926
 927 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 928
 929 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 930
 931 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 932
 933 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 934                   Uses<[DSPPos, DSPSCount]>;
 935
 936 //===----------------------------------------------------------------------===//
 937 // MIPS DSP Rev 2
 938 // Addition/subtraction
 939 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 940                                        DSPROpnd, DSPROpnd>, IsCommutable,
 941                      Defs<[DSPOutFlag20]>;
 942
 943 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 944                                          NoItinerary, DSPROpnd, DSPROpnd>,
 945                        IsCommutable, Defs<[DSPOutFlag20]>;
 946
 947 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 948                                        DSPROpnd, DSPROpnd>,
 949                      Defs<[DSPOutFlag20]>;
 950
 951 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 952                                          NoItinerary, DSPROpnd, DSPROpnd>,
 953                        Defs<[DSPOutFlag20]>;
 954
 955 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 956                                          NoItinerary, DSPROpnd>, IsCommutable;
 957
 958 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 959                                            NoItinerary, DSPROpnd>, IsCommutable;
 960
 961 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 962                                          NoItinerary, DSPROpnd>;
 963
 964 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 965                                            NoItinerary, DSPROpnd>;
 966
 967 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 968                                          NoItinerary, DSPROpnd>, IsCommutable;
 969
 970 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 971                                            NoItinerary, DSPROpnd>, IsCommutable;
 972
 973 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 974                                          NoItinerary, DSPROpnd>;
 975
 976 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 977                                            NoItinerary, DSPROpnd>;
 978
 979 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 980                                         NoItinerary, GPR32Opnd>, IsCommutable;
 981
 982 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 983                                           NoItinerary, GPR32Opnd>, IsCommutable;
 984
 985 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 986                                         NoItinerary, GPR32Opnd>;
 987
 988 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 989                                           NoItinerary, GPR32Opnd>;
 990
 991 // Comparison
 992 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 993                                                  int_mips_cmpgdu_eq_qb,
 994                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 995                           IsCommutable, Defs<[DSPCCond]>;
 996
 997 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 998                                                  int_mips_cmpgdu_lt_qb,
 999                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1000                           Defs<[DSPCCond]>;
1001
1002 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
1003                                                  int_mips_cmpgdu_le_qb,
1004                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
1005                           Defs<[DSPCCond]>;
1006
1007 // Absolute
1008 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
1009                                               NoItinerary, DSPROpnd>,
1010                        Defs<[DSPOutFlag20]>;
1011
1012 // Multiplication
1013 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
1014                                        DSPROpnd>, IsCommutable,
1015                     Defs<[DSPOutFlag21]>;
1016
1017 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1018                                          NoItinerary, DSPROpnd>, IsCommutable,
1019                       Defs<[DSPOutFlag21]>;
1020
1021 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1022                                          NoItinerary, GPR32Opnd>, IsCommutable,
1023                       Defs<[DSPOutFlag21]>;
1024
1025 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1026                                           NoItinerary, GPR32Opnd>, IsCommutable,
1027                        Defs<[DSPOutFlag21]>;
1028
1029 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1030                                          NoItinerary, DSPROpnd, DSPROpnd>,
1031                        IsCommutable, Defs<[DSPOutFlag21]>;
1032
1033 // Dot product with accumulate/subtract
1034 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1035
1036 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1037
1038 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1039                           Defs<[DSPOutFlag16_19]>;
1040
1041 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1042                                               MipsDPAQX_SA_W_PH>,
1043                            Defs<[DSPOutFlag16_19]>;
1044
1045 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1046
1047 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1048
1049 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1050                           Defs<[DSPOutFlag16_19]>;
1051
1052 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1053                                               MipsDPSQX_SA_W_PH>,
1054                            Defs<[DSPOutFlag16_19]>;
1055
1056 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1057
1058 // Precision reduce/expand
1059 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1060                                                 int_mips_precr_qb_ph,
1061                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1062
1063 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1064                                                      int_mips_precr_sra_ph_w,
1065                                                      NoItinerary, DSPROpnd,
1066                                                      GPR32Opnd>;
1067
1068 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1069                                                       int_mips_precr_sra_r_ph_w,
1070                                                        NoItinerary, DSPROpnd,
1071                                                        GPR32Opnd>;
1072
1073 // Shift
1074 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1075                                           NoItinerary, DSPROpnd, uimm3>;
1076
1077 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1078                                            NoItinerary, DSPROpnd>;
1079
1080 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1081                                             immZExt3, NoItinerary, DSPROpnd,
1082                                             uimm3>;
1083
1084 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1085                                              NoItinerary, DSPROpnd>;
1086
1087 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1088                                           NoItinerary, DSPROpnd, uimm4>;
1089
1090 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1091                                            NoItinerary, DSPROpnd>;
1092
1093 // Misc
1094 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5,
1095                                      NoItinerary>;
1096
1097 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2,
1098                                      NoItinerary>;
1099
1100 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1101                                       immZExt5, NoItinerary>;
1102
1103 // Pseudos.
1104 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1105                                                 NoItinerary>, Uses<[DSPPos]>;
1106
1107 // Instruction defs.
1108 // MIPS DSP Rev 1
1109 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1110 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1111 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1112 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1113 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1114 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1115 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1116 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1117 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1118 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1119 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1120 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1121 def MODSUB : DspMMRel, MODSUB_ENC, MODSUB_DESC;
1122 def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1123 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1124 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1125 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1126 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1127 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1128 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1129 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1130 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1131 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1132 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1133 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1134 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1135 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1136 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1137 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1138 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1139 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1140 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1141 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1142 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1143 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1144 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1145 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1146 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1147 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1148 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1149 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1150 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1151 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1152 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1153 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1154 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1155 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1156 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1157 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1158 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1159 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1160 def MULSAQ_S_W_PH : DspMMRel, MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1161 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1162 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1163 def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1164 def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1165 def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;
1166 def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;
1167 def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;
1168 def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;
1169 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1170 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1171 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1172 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1173 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1174 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1175 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1176 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1177 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1178 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1179 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1180 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1181 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1182 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1183 def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1184 def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1185 def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1186 def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1187 def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1188 def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1189 def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1190 def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1191 def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1192 def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;
1193 def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
1194 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
1195 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
1196 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
1197 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
1198 def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;
1199 def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
1200 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
1201 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
1202 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
1203 let AdditionalPredicates = [NotInMicroMips] in {
1204   def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
1205 }
1206 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1207 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1208 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1209 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1210 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1211 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1212 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1213 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1214 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1215 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1216 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1217 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1218 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1219 def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC;
1220 def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC;
1221 def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
1222 def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
1223 let AdditionalPredicates = [NotInMicroMips] in {
1224   def WRDSP : WRDSP_ENC, WRDSP_DESC;
1225 }
1226
1227 // MIPS DSP Rev 2
1228 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
1229 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
1230 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
1231 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
1232 def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
1233 def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
1234 def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
1235 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
1236 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
1237 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
1238 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;
1239 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
1240 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;
1241 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
1242 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;
1243 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
1244 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2;
1245 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
1246 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2;
1247 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
1248 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2;
1249 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2;
1250 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2;
1251 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
1252 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
1253 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2;
1254 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2;
1255 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2;
1256 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2;
1257 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
1258 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
1259 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
1260 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
1261 def MULSA_W_PH : DspMMRel, MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
1262 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;
1263 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;
1264 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
1265 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;
1266 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;
1267 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
1268 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
1269 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
1270 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
1271 def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
1272 def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
1273 def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
1274
1275 // Pseudos.
1276 let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
1277   // Pseudo instructions for loading and storing accumulator registers.
1278   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1279   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1280
1281   // Pseudos for loading and storing ccond field of DSP control register.
1282   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1283   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1284 }
1285
1286 // Pseudo CMP and PICK instructions.
1287 class PseudoCMP<Instruction RealInst> :
1288   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1289   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1290
1291 class PseudoPICK<Instruction RealInst> :
1292   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1293   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1294   NeverHasSideEffects;
1295
1296 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1297 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1298 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1299 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1300 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1301 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1302
1303 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1304 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1305
1306 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1307
1308 // Patterns.
1309 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1310   Pat<pattern, result>, Requires<[pred]>;
1311
1312 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1313                     RegisterClass SrcRC> :
1314    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1315           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1316
1317 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1318 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1319 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1320 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1321
1322 def : DSPPat<(v2i16 (load addr:$a)),
1323              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1324 def : DSPPat<(v4i8 (load addr:$a)),
1325              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1326 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1327              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1328 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1329              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1330
1331 // Binary operations.
1332 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1333                 Predicate Pred = HasDSP> :
1334   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1335
1336 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1337 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1338 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1339 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1340 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1341 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1342 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1343 def : DSPBinPat<ADDU_QB, v4i8, add>;
1344 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1345 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1346 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1347 def : DSPBinPat<ADDSC, i32, addc>;
1348 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1349 def : DSPBinPat<ADDWC, i32, adde>;
1350
1351 // Shift immediate patterns.
1352 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1353                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1354   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1355
1356 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1357 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1358 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1359 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1360 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1361 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1362 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1363 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1364 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1365 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1366 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1367 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1368
1369 // SETCC/SELECT_CC patterns.
1370 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1371                   CondCode CC> :
1372   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1373          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1374                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1375                       (ValTy ZERO)))>;
1376
1377 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1378                      CondCode CC> :
1379   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1380          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1381                       (ValTy ZERO),
1382                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1383
1384 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1385                      CondCode CC> :
1386   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1387          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1388
1389 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1390                         CondCode CC> :
1391   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1392          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1393
1394 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1395 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1396 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1397 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1398 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1399 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1400 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1401 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1402 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1403 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1404 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1405 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1406
1407 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1408 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1409 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1410 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1411 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1412 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1413 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1414 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1415 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1416 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1417 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1418 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1419
1420 // Extr patterns.
1421 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1422   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1423          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1424
1425 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1426   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1427          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1428
1429 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1430 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1431 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1432 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1433 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1434 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1435 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1436 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1437 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1438 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1439 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1440 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1441
1442 // Indexed load patterns.
1443 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1444   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1445          (Instr i32:$base, i32:$index)>;
1446
1447 let AddedComplexity = 20 in {
1448   def : IndexedLoadPat<zextloadi8, LBUX>;
1449   def : IndexedLoadPat<sextloadi16, LHX>;
1450   def : IndexedLoadPat<load, LWX>;
1451 }
1452
1453 // Instruction alias.
1454 let AdditionalPredicates = [NotInMicroMips] in {
1455   def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;
1456 }