1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips DSP ASE instructions.
12 //===----------------------------------------------------------------------===//
15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
22 def immSExt10 : ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
24 // Mips-specific dsp nodes
25 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
26 SDTCisVT<2, untyped>]>;
27 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
29 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
30 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
31 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
34 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
35 SDNode<!strconcat("MipsISD::", Opc), Prof>;
37 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
38 SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
40 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
41 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
42 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
43 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
44 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
45 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
47 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
48 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
50 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
51 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
52 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
53 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
54 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
56 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
57 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
58 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
59 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
60 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
61 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
62 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
63 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
65 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
66 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
67 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
68 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
69 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
70 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
71 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
72 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
73 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
75 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
76 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
77 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
78 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
79 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
80 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
81 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
82 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
83 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
84 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
85 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
88 class Uses<list<Register> Regs> {
89 list<Register> Uses = Regs;
92 class Defs<list<Register> Regs> {
93 list<Register> Defs = Regs;
96 // Instruction encoding.
97 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
98 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
99 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
100 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
101 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
102 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
103 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
104 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
105 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
106 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
107 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
108 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
109 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
110 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
111 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
112 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
113 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
114 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
115 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
116 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
117 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
118 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
119 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
120 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
121 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
122 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
123 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
124 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
125 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
126 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
127 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
128 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
129 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
130 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
131 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
132 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
133 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
134 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
135 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
136 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
137 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
138 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
139 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
140 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
141 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
142 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
143 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
144 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
145 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
146 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
147 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
148 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
149 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
150 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
151 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
152 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
153 class MFHI_ENC : MFHI_FMT<0b010000>;
154 class MFLO_ENC : MFHI_FMT<0b010010>;
155 class MTHI_ENC : MTHI_FMT<0b010001>;
156 class MTLO_ENC : MTHI_FMT<0b010011>;
157 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
158 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
159 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
160 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
161 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
162 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
163 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
164 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
165 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
166 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
167 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
168 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
169 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
170 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
171 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
172 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
173 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
174 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
175 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
176 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
177 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
178 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
179 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
180 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
181 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
182 class REPL_QB_ENC : REPL_FMT<0b00010>;
183 class REPL_PH_ENC : REPL_FMT<0b01010>;
184 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
185 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
186 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
187 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
188 class LWX_ENC : LX_FMT<0b00000>;
189 class LHX_ENC : LX_FMT<0b00100>;
190 class LBUX_ENC : LX_FMT<0b00110>;
191 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
192 class INSV_ENC : INSV_FMT<0b001100>;
194 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
195 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
196 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
197 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
198 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
199 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
200 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
201 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
202 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
203 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
204 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
205 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
206 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
207 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
208 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
210 class RDDSP_ENC : RDDSP_FMT<0b10010>;
211 class WRDSP_ENC : WRDSP_FMT<0b10011>;
212 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
213 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
214 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
215 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
216 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
217 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
218 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
219 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
220 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
221 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
222 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
223 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
224 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
225 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
226 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
227 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
228 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
229 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
230 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
231 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
232 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
233 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
234 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
235 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
236 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
237 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
238 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
239 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
240 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
241 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
242 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
243 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
244 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
245 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
246 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
247 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
248 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
249 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
250 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
251 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
252 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
253 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
254 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
255 class APPEND_ENC : APPEND_FMT<0b00000>;
256 class BALIGN_ENC : APPEND_FMT<0b10000>;
257 class PREPEND_ENC : APPEND_FMT<0b00001>;
260 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
261 InstrItinClass itin, RegisterOperand ROD,
262 RegisterOperand ROS, RegisterOperand ROT = ROS> {
263 dag OutOperandList = (outs ROD:$rd);
264 dag InOperandList = (ins ROS:$rs, ROT:$rt);
265 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
266 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
267 InstrItinClass Itinerary = itin;
268 string BaseOpcode = instr_asm;
271 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
272 InstrItinClass itin, RegisterOperand ROD,
273 RegisterOperand ROS = ROD> {
274 dag OutOperandList = (outs ROD:$rd);
275 dag InOperandList = (ins ROS:$rs);
276 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
277 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
278 InstrItinClass Itinerary = itin;
279 string BaseOpcode = instr_asm;
282 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
283 InstrItinClass itin, RegisterOperand ROS,
284 RegisterOperand ROT = ROS> {
285 dag OutOperandList = (outs);
286 dag InOperandList = (ins ROS:$rs, ROT:$rt);
287 string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
288 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
289 InstrItinClass Itinerary = itin;
290 string BaseOpcode = instr_asm;
293 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 InstrItinClass itin, RegisterOperand ROD,
295 RegisterOperand ROS, RegisterOperand ROT = ROS> {
296 dag OutOperandList = (outs ROD:$rd);
297 dag InOperandList = (ins ROS:$rs, ROT:$rt);
298 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
299 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
300 InstrItinClass Itinerary = itin;
301 string BaseOpcode = instr_asm;
304 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
305 InstrItinClass itin, RegisterOperand ROT,
306 RegisterOperand ROS = ROT> {
307 dag OutOperandList = (outs ROT:$rt);
308 dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
309 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
310 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
311 InstrItinClass Itinerary = itin;
312 string Constraints = "$src = $rt";
313 string BaseOpcode = instr_asm;
316 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
317 InstrItinClass itin, RegisterOperand ROD,
318 RegisterOperand ROT = ROD> {
319 dag OutOperandList = (outs ROD:$rd);
320 dag InOperandList = (ins ROT:$rt);
321 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
322 list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
323 InstrItinClass Itinerary = itin;
324 string BaseOpcode = instr_asm;
327 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
328 Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,
329 RegisterOperand RO> {
330 dag OutOperandList = (outs RO:$rd);
331 dag InOperandList = (ins ImmOp:$imm);
332 string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
333 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
334 InstrItinClass Itinerary = itin;
335 string BaseOpcode = instr_asm;
338 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
339 InstrItinClass itin, RegisterOperand RO> {
340 dag OutOperandList = (outs RO:$rd);
341 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
342 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
343 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
344 InstrItinClass Itinerary = itin;
345 string BaseOpcode = instr_asm;
348 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
349 SDPatternOperator ImmPat, InstrItinClass itin,
350 RegisterOperand RO, Operand ImmOpnd> {
351 dag OutOperandList = (outs RO:$rd);
352 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
353 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
354 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
355 InstrItinClass Itinerary = itin;
356 bit hasSideEffects = 1;
357 string BaseOpcode = instr_asm;
360 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
361 InstrItinClass itin> {
362 dag OutOperandList = (outs GPR32Opnd:$rd);
363 dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
364 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
365 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
366 InstrItinClass Itinerary = itin;
368 string BaseOpcode = instr_asm;
371 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
372 InstrItinClass itin, RegisterOperand ROD,
373 RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {
374 dag OutOperandList = (outs ROD:$rd);
375 dag InOperandList = (ins ROS:$rs, ROT:$rt);
376 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
377 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
378 InstrItinClass Itinerary = itin;
379 string BaseOpcode = instr_asm;
382 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
383 Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
384 dag OutOperandList = (outs GPR32Opnd:$rt);
385 dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
386 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
387 list<dag> Pattern = [(set GPR32Opnd:$rt,
388 (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
389 InstrItinClass Itinerary = itin;
390 string Constraints = "$src = $rt";
391 string BaseOpcode = instr_asm;
394 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
395 InstrItinClass itin> {
396 dag OutOperandList = (outs GPR32Opnd:$rt);
397 dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
398 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
399 InstrItinClass Itinerary = itin;
400 string BaseOpcode = instr_asm;
403 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
404 InstrItinClass itin> {
405 dag OutOperandList = (outs GPR32Opnd:$rt);
406 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
407 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
408 InstrItinClass Itinerary = itin;
409 string BaseOpcode = instr_asm;
412 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
413 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
414 dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin);
415 string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
416 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
417 (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
418 string Constraints = "$acin = $ac";
419 string BaseOpcode = instr_asm;
422 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
423 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
424 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
425 string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
426 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
427 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
428 string Constraints = "$acin = $ac";
429 string BaseOpcode = instr_asm;
432 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
433 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
434 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
435 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
436 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
437 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
438 string Constraints = "$acin = $ac";
439 string BaseOpcode = instr_asm;
442 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
443 InstrItinClass itin> {
444 dag OutOperandList = (outs GPR32Opnd:$rd);
445 dag InOperandList = (ins uimm10:$mask);
446 string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
447 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
448 InstrItinClass Itinerary = itin;
449 string BaseOpcode = instr_asm;
452 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
453 InstrItinClass itin> {
454 dag OutOperandList = (outs);
455 dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);
456 string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
457 list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
458 InstrItinClass Itinerary = itin;
459 string BaseOpcode = instr_asm;
462 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
463 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
464 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
465 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
466 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
467 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
468 string Constraints = "$acin = $ac";
469 string BaseOpcode = instr_asm;
472 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
473 InstrItinClass itin> {
474 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
475 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
476 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
477 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
478 InstrItinClass Itinerary = itin;
479 bit isCommutable = 1;
480 string BaseOpcode = instr_asm;
483 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
484 InstrItinClass itin> {
485 dag OutOperandList = (outs ACC64DSPOpnd:$ac);
486 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
487 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
488 list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
489 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
490 InstrItinClass Itinerary = itin;
491 string Constraints = "$acin = $ac";
492 string BaseOpcode = instr_asm;
495 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
496 InstrItinClass itin> {
497 dag OutOperandList = (outs GPR32Opnd:$rd);
498 dag InOperandList = (ins RO:$ac);
499 string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
500 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
501 InstrItinClass Itinerary = itin;
502 string BaseOpcode = instr_asm;
505 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
506 dag OutOperandList = (outs RO:$ac);
507 dag InOperandList = (ins GPR32Opnd:$rs);
508 string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
509 InstrItinClass Itinerary = itin;
510 string BaseOpcode = instr_asm;
513 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
514 MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
515 bit usesCustomInserter = 1;
518 class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
519 InstrItinClass itin> {
520 dag OutOperandList = (outs);
521 dag InOperandList = (ins opnd:$offset);
522 string AsmString = !strconcat(instr_asm, "\t$offset");
523 InstrItinClass Itinerary = itin;
525 bit isTerminator = 1;
526 bit hasDelaySlot = 1;
527 string BaseOpcode = instr_asm;
530 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
531 InstrItinClass itin> {
532 dag OutOperandList = (outs GPR32Opnd:$rt);
533 dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
534 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
535 list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
536 InstrItinClass Itinerary = itin;
537 string Constraints = "$src = $rt";
538 string BaseOpcode = instr_asm;
541 //===----------------------------------------------------------------------===//
543 //===----------------------------------------------------------------------===//
545 // Addition/subtraction
546 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
547 DSPROpnd, DSPROpnd>, IsCommutable,
548 Defs<[DSPOutFlag20]>;
550 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
551 NoItinerary, DSPROpnd, DSPROpnd>,
552 IsCommutable, Defs<[DSPOutFlag20]>;
554 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
556 Defs<[DSPOutFlag20]>;
558 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
559 NoItinerary, DSPROpnd, DSPROpnd>,
560 Defs<[DSPOutFlag20]>;
562 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
563 DSPROpnd, DSPROpnd>, IsCommutable,
564 Defs<[DSPOutFlag20]>;
566 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
567 NoItinerary, DSPROpnd, DSPROpnd>,
568 IsCommutable, Defs<[DSPOutFlag20]>;
570 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
572 Defs<[DSPOutFlag20]>;
574 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
575 NoItinerary, DSPROpnd, DSPROpnd>,
576 Defs<[DSPOutFlag20]>;
578 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
579 NoItinerary, GPR32Opnd, GPR32Opnd>,
580 IsCommutable, Defs<[DSPOutFlag20]>;
582 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
583 NoItinerary, GPR32Opnd, GPR32Opnd>,
584 Defs<[DSPOutFlag20]>;
586 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
587 GPR32Opnd, GPR32Opnd>, IsCommutable,
590 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
591 GPR32Opnd, GPR32Opnd>,
592 IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
594 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
595 GPR32Opnd, GPR32Opnd>;
597 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
598 NoItinerary, GPR32Opnd, DSPROpnd>;
601 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
602 NoItinerary, DSPROpnd>,
603 Defs<[DSPOutFlag20]>;
605 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
606 NoItinerary, GPR32Opnd>,
607 Defs<[DSPOutFlag20]>;
609 // Precision reduce/expand
610 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
611 int_mips_precrq_qb_ph,
612 NoItinerary, DSPROpnd, DSPROpnd>;
614 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
615 int_mips_precrq_ph_w,
616 NoItinerary, DSPROpnd, GPR32Opnd>;
618 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
619 int_mips_precrq_rs_ph_w,
620 NoItinerary, DSPROpnd,
622 Defs<[DSPOutFlag22]>;
624 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
625 int_mips_precrqu_s_qb_ph,
626 NoItinerary, DSPROpnd,
628 Defs<[DSPOutFlag22]>;
630 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
631 int_mips_preceq_w_phl,
632 NoItinerary, GPR32Opnd, DSPROpnd>;
634 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
635 int_mips_preceq_w_phr,
636 NoItinerary, GPR32Opnd, DSPROpnd>;
638 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
639 int_mips_precequ_ph_qbl,
640 NoItinerary, DSPROpnd>;
642 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
643 int_mips_precequ_ph_qbr,
644 NoItinerary, DSPROpnd>;
646 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
647 int_mips_precequ_ph_qbla,
648 NoItinerary, DSPROpnd>;
650 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
651 int_mips_precequ_ph_qbra,
652 NoItinerary, DSPROpnd>;
654 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
655 int_mips_preceu_ph_qbl,
656 NoItinerary, DSPROpnd>;
658 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
659 int_mips_preceu_ph_qbr,
660 NoItinerary, DSPROpnd>;
662 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
663 int_mips_preceu_ph_qbla,
664 NoItinerary, DSPROpnd>;
666 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
667 int_mips_preceu_ph_qbra,
668 NoItinerary, DSPROpnd>;
671 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
672 NoItinerary, DSPROpnd, uimm3>,
673 Defs<[DSPOutFlag22]>;
675 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
676 NoItinerary, DSPROpnd>,
677 Defs<[DSPOutFlag22]>;
679 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
680 NoItinerary, DSPROpnd, uimm3>;
682 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
683 NoItinerary, DSPROpnd>;
685 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
686 NoItinerary, DSPROpnd, uimm4>,
687 Defs<[DSPOutFlag22]>;
689 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
690 NoItinerary, DSPROpnd>,
691 Defs<[DSPOutFlag22]>;
693 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
694 immZExt4, NoItinerary, DSPROpnd,
696 Defs<[DSPOutFlag22]>;
698 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
699 NoItinerary, DSPROpnd>,
700 Defs<[DSPOutFlag22]>;
702 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
703 NoItinerary, DSPROpnd, uimm4>;
705 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
706 NoItinerary, DSPROpnd>;
708 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
709 immZExt4, NoItinerary, DSPROpnd,
712 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
713 NoItinerary, DSPROpnd>;
715 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
716 immZExt5, NoItinerary, GPR32Opnd,
718 Defs<[DSPOutFlag22]>;
720 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
721 NoItinerary, GPR32Opnd>,
722 Defs<[DSPOutFlag22]>;
724 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
725 immZExt5, NoItinerary, GPR32Opnd,
728 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
729 NoItinerary, GPR32Opnd>;
732 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
733 int_mips_muleu_s_ph_qbl,
734 NoItinerary, DSPROpnd, DSPROpnd>,
735 Defs<[DSPOutFlag21]>;
737 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
738 int_mips_muleu_s_ph_qbr,
739 NoItinerary, DSPROpnd, DSPROpnd>,
740 Defs<[DSPOutFlag21]>;
742 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
743 int_mips_muleq_s_w_phl,
744 NoItinerary, GPR32Opnd, DSPROpnd>,
745 IsCommutable, Defs<[DSPOutFlag21]>;
747 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
748 int_mips_muleq_s_w_phr,
749 NoItinerary, GPR32Opnd, DSPROpnd>,
750 IsCommutable, Defs<[DSPOutFlag21]>;
752 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
753 NoItinerary, DSPROpnd, DSPROpnd>,
754 IsCommutable, Defs<[DSPOutFlag21]>;
756 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
758 Defs<[DSPOutFlag16_19]>;
760 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
761 Defs<[DSPOutFlag16_19]>;
763 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
764 Defs<[DSPOutFlag16_19]>;
766 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
767 Defs<[DSPOutFlag16_19]>;
769 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
770 Defs<[DSPOutFlag16_19]>;
772 // Move from/to hi/lo.
773 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
774 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
775 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
776 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
778 // Dot product with accumulate/subtract
779 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
781 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
783 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
785 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
787 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
788 Defs<[DSPOutFlag16_19]>;
790 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
791 Defs<[DSPOutFlag16_19]>;
793 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
794 Defs<[DSPOutFlag16_19]>;
796 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
797 Defs<[DSPOutFlag16_19]>;
799 class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
800 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
801 class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
802 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
803 class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
804 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
807 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
808 int_mips_cmpu_eq_qb, NoItinerary,
810 IsCommutable, Defs<[DSPCCond]>;
812 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
813 int_mips_cmpu_lt_qb, NoItinerary,
814 DSPROpnd>, Defs<[DSPCCond]>;
816 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
817 int_mips_cmpu_le_qb, NoItinerary,
818 DSPROpnd>, Defs<[DSPCCond]>;
820 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
821 int_mips_cmpgu_eq_qb,
822 NoItinerary, GPR32Opnd, DSPROpnd>,
825 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
826 int_mips_cmpgu_lt_qb,
827 NoItinerary, GPR32Opnd, DSPROpnd>;
829 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
830 int_mips_cmpgu_le_qb,
831 NoItinerary, GPR32Opnd, DSPROpnd>;
833 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
834 NoItinerary, DSPROpnd>,
835 IsCommutable, Defs<[DSPCCond]>;
837 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
838 NoItinerary, DSPROpnd>,
841 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
842 NoItinerary, DSPROpnd>,
846 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
847 NoItinerary, GPR32Opnd>;
849 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
850 NoItinerary, DSPROpnd, DSPROpnd>;
852 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
853 immZExt8, NoItinerary, DSPROpnd>;
855 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10,
856 immSExt10, NoItinerary, DSPROpnd>;
858 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
859 NoItinerary, DSPROpnd, GPR32Opnd>;
861 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
862 NoItinerary, DSPROpnd, GPR32Opnd>;
864 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
865 NoItinerary, DSPROpnd, DSPROpnd>,
868 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
869 NoItinerary, DSPROpnd, DSPROpnd>,
872 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
874 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
876 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
878 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
881 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
882 Uses<[DSPPos]>, Defs<[DSPEFI]>;
884 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
885 Uses<[DSPPos]>, Defs<[DSPEFI]>;
887 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
888 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
890 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
892 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
894 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
895 Defs<[DSPOutFlag23]>;
897 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
898 NoItinerary>, Defs<[DSPOutFlag23]>;
900 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
902 Defs<[DSPOutFlag23]>;
904 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
906 Defs<[DSPOutFlag23]>;
908 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
910 Defs<[DSPOutFlag23]>;
912 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
914 Defs<[DSPOutFlag23]>;
916 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
918 Defs<[DSPOutFlag23]>;
920 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
922 Defs<[DSPOutFlag23]>;
924 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
926 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
928 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
930 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
932 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
934 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
935 Uses<[DSPPos, DSPSCount]>;
937 //===----------------------------------------------------------------------===//
939 // Addition/subtraction
940 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
941 DSPROpnd, DSPROpnd>, IsCommutable,
942 Defs<[DSPOutFlag20]>;
944 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
945 NoItinerary, DSPROpnd, DSPROpnd>,
946 IsCommutable, Defs<[DSPOutFlag20]>;
948 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
950 Defs<[DSPOutFlag20]>;
952 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
953 NoItinerary, DSPROpnd, DSPROpnd>,
954 Defs<[DSPOutFlag20]>;
956 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
957 NoItinerary, DSPROpnd>, IsCommutable;
959 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
960 NoItinerary, DSPROpnd>, IsCommutable;
962 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
963 NoItinerary, DSPROpnd>;
965 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
966 NoItinerary, DSPROpnd>;
968 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
969 NoItinerary, DSPROpnd>, IsCommutable;
971 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
972 NoItinerary, DSPROpnd>, IsCommutable;
974 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
975 NoItinerary, DSPROpnd>;
977 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
978 NoItinerary, DSPROpnd>;
980 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
981 NoItinerary, GPR32Opnd>, IsCommutable;
983 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
984 NoItinerary, GPR32Opnd>, IsCommutable;
986 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
987 NoItinerary, GPR32Opnd>;
989 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
990 NoItinerary, GPR32Opnd>;
993 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
994 int_mips_cmpgdu_eq_qb,
995 NoItinerary, GPR32Opnd, DSPROpnd>,
996 IsCommutable, Defs<[DSPCCond]>;
998 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
999 int_mips_cmpgdu_lt_qb,
1000 NoItinerary, GPR32Opnd, DSPROpnd>,
1003 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
1004 int_mips_cmpgdu_le_qb,
1005 NoItinerary, GPR32Opnd, DSPROpnd>,
1009 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
1010 NoItinerary, DSPROpnd>,
1011 Defs<[DSPOutFlag20]>;
1014 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
1015 DSPROpnd>, IsCommutable,
1016 Defs<[DSPOutFlag21]>;
1018 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
1019 NoItinerary, DSPROpnd>, IsCommutable,
1020 Defs<[DSPOutFlag21]>;
1022 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
1023 NoItinerary, GPR32Opnd>, IsCommutable,
1024 Defs<[DSPOutFlag21]>;
1026 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1027 NoItinerary, GPR32Opnd>, IsCommutable,
1028 Defs<[DSPOutFlag21]>;
1030 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1031 NoItinerary, DSPROpnd, DSPROpnd>,
1032 IsCommutable, Defs<[DSPOutFlag21]>;
1034 // Dot product with accumulate/subtract
1035 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1037 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1039 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1040 Defs<[DSPOutFlag16_19]>;
1042 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1044 Defs<[DSPOutFlag16_19]>;
1046 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1048 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1050 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1051 Defs<[DSPOutFlag16_19]>;
1053 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1055 Defs<[DSPOutFlag16_19]>;
1057 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1059 // Precision reduce/expand
1060 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1061 int_mips_precr_qb_ph,
1062 NoItinerary, DSPROpnd, DSPROpnd>;
1064 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1065 int_mips_precr_sra_ph_w,
1066 NoItinerary, DSPROpnd,
1069 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1070 int_mips_precr_sra_r_ph_w,
1071 NoItinerary, DSPROpnd,
1075 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1076 NoItinerary, DSPROpnd, uimm3>;
1078 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1079 NoItinerary, DSPROpnd>;
1081 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1082 immZExt3, NoItinerary, DSPROpnd,
1085 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1086 NoItinerary, DSPROpnd>;
1088 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1089 NoItinerary, DSPROpnd, uimm4>;
1091 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1092 NoItinerary, DSPROpnd>;
1095 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5,
1098 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2,
1101 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
1102 immZExt5, NoItinerary>;
1105 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1106 NoItinerary>, Uses<[DSPPos]>;
1108 // Instruction defs.
1110 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1111 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1112 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
1113 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1114 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1115 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1116 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
1117 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1118 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1119 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1120 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1121 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1122 def MODSUB : DspMMRel, MODSUB_ENC, MODSUB_DESC;
1123 def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1124 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1125 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1126 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1127 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1128 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1129 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1130 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1131 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1132 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1133 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1134 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1135 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1136 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1137 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1138 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1139 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1140 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1141 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1142 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
1143 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
1144 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1145 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1146 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1147 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1148 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC;
1149 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC;
1150 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1151 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1152 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1153 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1154 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC;
1155 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1156 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1157 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1158 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1159 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1160 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1161 def MULSAQ_S_W_PH : DspMMRel, MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1162 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1163 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1164 def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1165 def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1166 def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC;
1167 def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC;
1168 def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC;
1169 def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC;
1170 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1171 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1172 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1173 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1174 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1175 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1176 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1177 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1178 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1179 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1180 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1181 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1182 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1183 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1184 def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1185 def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1186 def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1187 def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1188 def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1189 def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1190 def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1191 def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1192 def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1193 def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;
1194 def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
1195 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
1196 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
1197 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
1198 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
1199 def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC;
1200 def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
1201 def LWX : DspMMRel, LWX_ENC, LWX_DESC;
1202 def LHX : DspMMRel, LHX_ENC, LHX_DESC;
1203 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
1204 let AdditionalPredicates = [NotInMicroMips] in {
1205 def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
1207 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1208 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
1209 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
1210 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
1211 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
1212 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1213 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
1214 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
1215 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1216 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1217 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1218 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
1219 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1220 def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC;
1221 def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC;
1222 def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
1223 def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
1224 let AdditionalPredicates = [NotInMicroMips] in {
1225 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1229 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
1230 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
1231 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
1232 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
1233 def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
1234 def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
1235 def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
1236 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
1237 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
1238 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
1239 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2;
1240 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
1241 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2;
1242 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
1243 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2;
1244 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
1245 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2;
1246 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
1247 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2;
1248 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
1249 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2;
1250 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2;
1251 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2;
1252 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2;
1253 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2;
1254 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2;
1255 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2;
1256 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2;
1257 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2;
1258 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
1259 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2;
1260 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2;
1261 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2;
1262 def MULSA_W_PH : DspMMRel, MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2;
1263 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2;
1264 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2;
1265 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
1266 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2;
1267 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2;
1268 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2;
1269 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
1270 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
1271 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
1272 def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
1273 def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
1274 def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
1277 let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
1278 // Pseudo instructions for loading and storing accumulator registers.
1279 def LOAD_ACC64DSP : Load<"", ACC64DSPOpnd>;
1280 def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1282 // Pseudos for loading and storing ccond field of DSP control register.
1283 def LOAD_CCOND_DSP : Load<"load_ccond_dsp", DSPCC>;
1284 def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1287 let DecoderNamespace = "MipsDSP", Arch = "dsp",
1288 AdditionalPredicates = [HasDSP] in {
1289 def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
1290 def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
1293 // Pseudo CMP and PICK instructions.
1294 class PseudoCMP<Instruction RealInst> :
1295 PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1296 PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1298 class PseudoPICK<Instruction RealInst> :
1299 PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1300 PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1301 NeverHasSideEffects;
1303 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1304 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1305 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1306 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1307 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1308 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1310 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1311 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1313 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1316 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1317 Pat<pattern, result>, Requires<[pred]>;
1319 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1320 RegisterClass SrcRC> :
1321 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1322 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1324 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1325 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1326 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1327 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1328 def : BitconvertPat<f32, v2i16, FGR32, DSPR>;
1329 def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1330 def : BitconvertPat<v2i16, f32, DSPR, FGR32>;
1331 def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1333 def : DSPPat<(v2i16 (load addr:$a)),
1334 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1335 def : DSPPat<(v4i8 (load addr:$a)),
1336 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1337 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1338 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1339 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1340 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1342 // Binary operations.
1343 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1344 Predicate Pred = HasDSP> :
1345 DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1347 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1348 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1349 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1350 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1351 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1352 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1353 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1354 def : DSPBinPat<ADDU_QB, v4i8, add>;
1355 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1356 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1357 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1358 def : DSPBinPat<ADDSC, i32, addc>;
1359 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1360 def : DSPBinPat<ADDWC, i32, adde>;
1362 // Shift immediate patterns.
1363 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1364 SDPatternOperator Imm, Predicate Pred = HasDSP> :
1365 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1367 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1368 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1369 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1370 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1371 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1372 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1373 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1374 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1375 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1376 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1377 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1378 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1380 // SETCC/SELECT_CC patterns.
1381 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1383 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1384 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1385 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1388 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1390 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1391 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1393 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1395 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1397 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1398 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1400 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1402 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1403 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1405 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1406 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1407 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1408 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1409 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1410 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1411 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1412 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1413 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1414 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1415 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1416 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1418 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1419 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1420 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1421 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1422 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1423 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1424 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1425 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1426 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1427 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1428 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1429 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1432 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1433 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1434 (Instr ACC64DSP:$ac, GPR32:$rs)>;
1436 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1437 DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1438 (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1440 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1441 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1442 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1443 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1444 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1445 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1446 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1447 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1448 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1449 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1450 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1451 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1453 // Indexed load patterns.
1454 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1455 DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1456 (Instr i32:$base, i32:$index)>;
1458 let AddedComplexity = 20 in {
1459 def : IndexedLoadPat<zextloadi8, LBUX>;
1460 def : IndexedLoadPat<sextloadi16, LHX>;
1461 def : IndexedLoadPat<load, LWX>;
1464 // Instruction alias.
1465 let AdditionalPredicates = [NotInMicroMips] in {
1466 def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;