1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fill delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/MipsMCNaCl.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/PointerUnion.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Analysis/ValueTracking.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCInstrDesc.h"
38 #include "llvm/MC/MCRegisterInfo.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
53 #define DEBUG_TYPE "delay-slot-filler"
55 STATISTIC(FilledSlots, "Number of delay slots filled");
56 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
59 static cl::opt<bool> DisableDelaySlotFiller(
60 "disable-mips-delay-filler",
62 cl::desc("Fill all delay slots with NOPs."),
65 static cl::opt<bool> DisableForwardSearch(
66 "disable-mips-df-forward-search",
68 cl::desc("Disallow MIPS delay filler to search forward."),
71 static cl::opt<bool> DisableSuccBBSearch(
72 "disable-mips-df-succbb-search",
74 cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
77 static cl::opt<bool> DisableBackwardSearch(
78 "disable-mips-df-backward-search",
80 cl::desc("Disallow MIPS delay filler to search backward."),
83 enum CompactBranchPolicy {
84 CB_Never, ///< The policy 'never' may in some circumstances or for some
85 ///< ISAs not be absolutely adhered to.
86 CB_Optimal, ///< Optimal is the default and will produce compact branches
87 ///< when delay slots cannot be filled.
88 CB_Always ///< 'always' may in some circumstances may not be
89 ///< absolutely adhered to there may not be a corresponding
90 ///< compact form of a branch.
93 static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
94 "mips-compact-branches",cl::Optional,
96 cl::desc("MIPS Specific: Compact branch policy."),
98 clEnumValN(CB_Never, "never", "Do not use compact branches if possible."),
99 clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropiate (default)."),
100 clEnumValN(CB_Always, "always", "Always use compact branches if possible.")
106 typedef MachineBasicBlock::iterator Iter;
107 typedef MachineBasicBlock::reverse_iterator ReverseIter;
108 typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
112 RegDefsUses(const TargetRegisterInfo &TRI);
114 void init(const MachineInstr &MI);
116 /// This function sets all caller-saved registers in Defs.
117 void setCallerSaved(const MachineInstr &MI);
119 /// This function sets all unallocatable registers in Defs.
120 void setUnallocatableRegs(const MachineFunction &MF);
122 /// Set bits in Uses corresponding to MBB's live-out registers except for
123 /// the registers that are live-in to SuccBB.
124 void addLiveOut(const MachineBasicBlock &MBB,
125 const MachineBasicBlock &SuccBB);
127 bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
130 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
133 /// Returns true if Reg or its alias is in RegSet.
134 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
136 const TargetRegisterInfo &TRI;
137 BitVector Defs, Uses;
140 /// Base class for inspecting loads and stores.
141 class InspectMemInstr {
143 InspectMemInstr(bool ForbidMemInstr_) : ForbidMemInstr(ForbidMemInstr_) {}
144 virtual ~InspectMemInstr() = default;
146 /// Return true if MI cannot be moved to delay slot.
147 bool hasHazard(const MachineInstr &MI);
150 /// Flags indicating whether loads or stores have been seen.
151 bool OrigSeenLoad = false;
152 bool OrigSeenStore = false;
153 bool SeenLoad = false;
154 bool SeenStore = false;
156 /// Memory instructions are not allowed to move to delay slot if this flag
161 virtual bool hasHazard_(const MachineInstr &MI) = 0;
164 /// This subclass rejects any memory instructions.
165 class NoMemInstr : public InspectMemInstr {
167 NoMemInstr() : InspectMemInstr(true) {}
170 bool hasHazard_(const MachineInstr &MI) override { return true; }
173 /// This subclass accepts loads from stacks and constant loads.
174 class LoadFromStackOrConst : public InspectMemInstr {
176 LoadFromStackOrConst() : InspectMemInstr(false) {}
179 bool hasHazard_(const MachineInstr &MI) override;
182 /// This subclass uses memory dependence information to determine whether a
183 /// memory instruction can be moved to a delay slot.
184 class MemDefsUses : public InspectMemInstr {
186 MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI);
189 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
191 bool hasHazard_(const MachineInstr &MI) override;
193 /// Update Defs and Uses. Return true if there exist dependences that
194 /// disqualify the delay slot candidate between V and values in Uses and
196 bool updateDefsUses(ValueType V, bool MayStore);
198 /// Get the list of underlying objects of MI's memory operand.
199 bool getUnderlyingObjects(const MachineInstr &MI,
200 SmallVectorImpl<ValueType> &Objects) const;
202 const MachineFrameInfo *MFI;
203 SmallPtrSet<ValueType, 4> Uses, Defs;
204 const DataLayout &DL;
206 /// Flags indicating whether loads or stores with no underlying objects have
208 bool SeenNoObjLoad = false;
209 bool SeenNoObjStore = false;
212 class Filler : public MachineFunctionPass {
214 Filler() : MachineFunctionPass(ID), TM(nullptr) {}
216 StringRef getPassName() const override { return "Mips Delay Slot Filler"; }
218 bool runOnMachineFunction(MachineFunction &F) override {
220 bool Changed = false;
221 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
223 Changed |= runOnMachineBasicBlock(*FI);
225 // This pass invalidates liveness information when it reorders
226 // instructions to fill delay slot. Without this, -verify-machineinstrs
229 F.getRegInfo().invalidateLiveness();
234 MachineFunctionProperties getRequiredProperties() const override {
235 return MachineFunctionProperties().set(
236 MachineFunctionProperties::Property::NoVRegs);
239 void getAnalysisUsage(AnalysisUsage &AU) const override {
240 AU.addRequired<MachineBranchProbabilityInfo>();
241 MachineFunctionPass::getAnalysisUsage(AU);
245 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
247 Iter replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch,
250 /// This function checks if it is valid to move Candidate to the delay slot
251 /// and returns true if it isn't. It also updates memory and register
252 /// dependence information.
253 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
254 InspectMemInstr &IM) const;
256 /// This function searches range [Begin, End) for an instruction that can be
257 /// moved to the delay slot. Returns true on success.
258 template<typename IterTy>
259 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
260 RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot,
261 IterTy &Filler) const;
263 /// This function searches in the backward direction for an instruction that
264 /// can be moved to the delay slot. Returns true on success.
265 bool searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const;
267 /// This function searches MBB in the forward direction for an instruction
268 /// that can be moved to the delay slot. Returns true on success.
269 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
271 /// This function searches one of MBB's successor blocks for an instruction
272 /// that can be moved to the delay slot and inserts clones of the
273 /// instruction into the successor's predecessor blocks.
274 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
276 /// Pick a successor block of MBB. Return NULL if MBB doesn't have a
277 /// successor block that is not a landing pad.
278 MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
280 /// This function analyzes MBB and returns an instruction with an unoccupied
281 /// slot that branches to Dst.
282 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
283 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
285 /// Examine Pred and see if it is possible to insert an instruction into
286 /// one of its branches delay slot or its end.
287 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
288 RegDefsUses &RegDU, bool &HasMultipleSuccs,
289 BB2BrMap &BrMap) const;
291 bool terminateSearch(const MachineInstr &Candidate) const;
293 const TargetMachine *TM;
300 } // end anonymous namespace
302 static bool hasUnoccupiedSlot(const MachineInstr *MI) {
303 return MI->hasDelaySlot() && !MI->isBundledWithSucc();
306 /// This function inserts clones of Filler into predecessor blocks.
307 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
308 MachineFunction *MF = Filler->getParent()->getParent();
310 for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
312 MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
315 I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
320 /// This function adds registers Filler defines to MBB's live-in register list.
321 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
322 for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
323 const MachineOperand &MO = Filler->getOperand(I);
326 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
330 const MachineFunction &MF = *MBB.getParent();
331 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
332 "Shouldn't move an instruction with unallocatable registers across "
333 "basic block boundaries.");
336 if (!MBB.isLiveIn(R))
341 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI)
342 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
344 void RegDefsUses::init(const MachineInstr &MI) {
345 // Add all register operands which are explicit and non-variadic.
346 update(MI, 0, MI.getDesc().getNumOperands());
348 // If MI is a call, add RA to Defs to prevent users of RA from going into
353 // Add all implicit register operands of branch instructions except
356 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
357 Defs.reset(Mips::AT);
361 void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
364 // Add RA/RA_64 to Defs to prevent users of RA/RA_64 from going into
365 // the delay slot. The reason is that RA/RA_64 must not be changed
366 // in the delay slot so that the callee can return to the caller.
367 if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) {
369 Defs.set(Mips::RA_64);
372 // If MI is a call, add all caller-saved registers to Defs.
373 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
375 CallerSavedRegs.reset(Mips::ZERO);
376 CallerSavedRegs.reset(Mips::ZERO_64);
378 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent());
380 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
381 CallerSavedRegs.reset(*AI);
383 Defs |= CallerSavedRegs;
386 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
387 BitVector AllocSet = TRI.getAllocatableSet(MF);
389 for (unsigned R : AllocSet.set_bits())
390 for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
393 AllocSet.set(Mips::ZERO);
394 AllocSet.set(Mips::ZERO_64);
396 Defs |= AllocSet.flip();
399 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
400 const MachineBasicBlock &SuccBB) {
401 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
402 SE = MBB.succ_end(); SI != SE; ++SI)
404 for (const auto &LI : (*SI)->liveins())
405 Uses.set(LI.PhysReg);
408 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
409 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
410 bool HasHazard = false;
412 for (unsigned I = Begin; I != End; ++I) {
413 const MachineOperand &MO = MI.getOperand(I);
415 if (MO.isReg() && MO.getReg())
416 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
425 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
426 unsigned Reg, bool IsDef) const {
429 // check whether Reg has already been defined or used.
430 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
434 // check whether Reg has already been defined.
435 return isRegInSet(Defs, Reg);
438 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
439 // Check Reg and all aliased Registers.
440 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
441 if (RegSet.test(*AI))
446 bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
447 if (!MI.mayStore() && !MI.mayLoad())
453 OrigSeenLoad = SeenLoad;
454 OrigSeenStore = SeenStore;
455 SeenLoad |= MI.mayLoad();
456 SeenStore |= MI.mayStore();
458 // If MI is an ordered or volatile memory reference, disallow moving
459 // subsequent loads and stores to delay slot.
460 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
461 ForbidMemInstr = true;
465 return hasHazard_(MI);
468 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
472 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue())
475 if (const PseudoSourceValue *PSV =
476 (*MI.memoperands_begin())->getPseudoValue()) {
477 if (isa<FixedStackPseudoSourceValue>(PSV))
479 return !PSV->isConstant(nullptr) && !PSV->isStack();
485 MemDefsUses::MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI_)
486 : InspectMemInstr(false), MFI(MFI_), DL(DL) {}
488 bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
489 bool HasHazard = false;
490 SmallVector<ValueType, 4> Objs;
492 // Check underlying object list.
493 if (getUnderlyingObjects(MI, Objs)) {
494 for (SmallVectorImpl<ValueType>::const_iterator I = Objs.begin();
495 I != Objs.end(); ++I)
496 HasHazard |= updateDefsUses(*I, MI.mayStore());
501 // No underlying objects found.
502 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
503 HasHazard |= MI.mayLoad() || OrigSeenStore;
505 SeenNoObjLoad |= MI.mayLoad();
506 SeenNoObjStore |= MI.mayStore();
511 bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) {
513 return !Defs.insert(V).second || Uses.count(V) || SeenNoObjStore ||
517 return Defs.count(V) || SeenNoObjStore;
521 getUnderlyingObjects(const MachineInstr &MI,
522 SmallVectorImpl<ValueType> &Objects) const {
523 if (!MI.hasOneMemOperand() ||
524 (!(*MI.memoperands_begin())->getValue() &&
525 !(*MI.memoperands_begin())->getPseudoValue()))
528 if (const PseudoSourceValue *PSV =
529 (*MI.memoperands_begin())->getPseudoValue()) {
530 if (!PSV->isAliased(MFI))
532 Objects.push_back(PSV);
536 const Value *V = (*MI.memoperands_begin())->getValue();
538 SmallVector<Value *, 4> Objs;
539 GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL);
541 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end();
543 if (!isIdentifiedObject(V))
546 Objects.push_back(*I);
552 // Replace Branch with the compact branch instruction.
553 Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch,
554 const DebugLoc &DL) {
555 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
556 const MipsInstrInfo *TII = STI.getInstrInfo();
558 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch);
559 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
561 std::next(Branch)->eraseFromParent();
565 // For given opcode returns opcode of corresponding instruction with short
567 // For the pseudo TAILCALL*_MM instructions return the short delay slot
568 // form. Unfortunately, TAILCALL<->b16 is denied as b16 has a limited range
569 // that is too short to make use of for tail calls.
570 static int getEquivalentCallShort(int Opcode) {
573 return Mips::BGEZALS_MM;
575 return Mips::BLTZALS_MM;
577 return Mips::JALS_MM;
579 return Mips::JALRS_MM;
580 case Mips::JALR16_MM:
581 return Mips::JALRS16_MM;
582 case Mips::TAILCALL_MM:
583 llvm_unreachable("Attempting to shorten the TAILCALL_MM pseudo!");
584 case Mips::TAILCALLREG:
585 return Mips::JR16_MM;
587 llvm_unreachable("Unexpected call instruction for microMIPS.");
591 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
592 /// We assume there is only one delay slot per delayed instruction.
593 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
594 bool Changed = false;
595 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
596 bool InMicroMipsMode = STI.inMicroMipsMode();
597 const MipsInstrInfo *TII = STI.getInstrInfo();
599 if (InMicroMipsMode && STI.hasMips32r6()) {
600 // This is microMIPS32r6 or microMIPS64r6 processor. Delay slot for
601 // branching instructions is not needed.
605 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
606 if (!hasUnoccupiedSlot(&*I))
612 // Delay slot filling is disabled at -O0.
613 if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None)) {
616 if (MipsCompactBranchPolicy.getValue() != CB_Always ||
617 !TII->getEquivalentCompactForm(I)) {
618 if (searchBackward(MBB, *I)) {
620 } else if (I->isTerminator()) {
621 if (searchSuccBBs(MBB, I)) {
624 } else if (searchForward(MBB, I)) {
630 // Get instruction with delay slot.
631 MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
633 if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
635 // If instruction in delay slot is 16b change opcode to
636 // corresponding instruction with short delay slot.
638 // TODO: Implement an instruction mapping table of 16bit opcodes to
639 // 32bit opcodes so that an instruction can be expanded. This would
640 // save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop.
641 // TODO: Permit b16 when branching backwards to the the same function
642 // if it is in range.
643 DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
649 // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
650 // instead of adding NOP replace this instruction with the corresponding
651 // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
652 // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
653 // be replaced with JRC16_MM.
655 // For MIPSR6 attempt to produce the corresponding compact (no delay slot)
656 // form of the CTI. For indirect jumps this will not require inserting a
657 // NOP and for branches will hopefully avoid requiring a NOP.
658 if ((InMicroMipsMode ||
659 (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) &&
660 TII->getEquivalentCompactForm(I)) {
661 I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
665 // Bundle the NOP to the instruction with the delay slot.
666 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
667 MIBundleBuilder(MBB, I, std::next(I, 2));
673 template<typename IterTy>
674 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
675 RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,
676 IterTy &Filler) const {
677 for (IterTy I = Begin; I != End;) {
682 if (CurrI->isDebugValue())
685 if (terminateSearch(*CurrI))
688 assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
689 "Cannot put calls, returns or branches in delay slot.");
691 if (CurrI->isKill()) {
692 CurrI->eraseFromParent();
696 if (delayHasHazard(*CurrI, RegDU, IM))
699 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
700 if (STI.isTargetNaCl()) {
701 // In NaCl, instructions that must be masked are forbidden in delay slots.
702 // We only check for loads, stores and SP changes. Calls, returns and
703 // branches are not checked because non-NaCl targets never put them in
706 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
707 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
708 CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
712 bool InMicroMipsMode = STI.inMicroMipsMode();
713 const MipsInstrInfo *TII = STI.getInstrInfo();
714 unsigned Opcode = (*Slot).getOpcode();
715 // This is complicated by the tail call optimization. For non-PIC code
716 // there is only a 32bit sized unconditional branch which can be assumed
717 // to be able to reach the target. b16 only has a range of +/- 1 KB.
718 // It's entirely possible that the target function is reachable with b16
719 // but we don't have enough information to make that decision.
720 if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
721 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
722 Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL))
732 bool Filler::searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const {
733 if (DisableBackwardSearch)
736 auto *Fn = MBB.getParent();
737 RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo());
738 MemDefsUses MemDU(Fn->getDataLayout(), &Fn->getFrameInfo());
743 MachineBasicBlock::iterator SlotI = Slot;
744 if (!searchRange(MBB, ++SlotI.getReverse(), MBB.rend(), RegDU, MemDU, Slot,
748 MBB.splice(std::next(SlotI), &MBB, Filler.getReverse());
749 MIBundleBuilder(MBB, SlotI, std::next(SlotI, 2));
754 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
755 // Can handle only calls.
756 if (DisableForwardSearch || !Slot->isCall())
759 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
763 RegDU.setCallerSaved(*Slot);
765 if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler))
768 MBB.splice(std::next(Slot), &MBB, Filler);
769 MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
774 bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
775 if (DisableSuccBBSearch)
778 MachineBasicBlock *SuccBB = selectSuccBB(MBB);
783 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
784 bool HasMultipleSuccs = false;
786 std::unique_ptr<InspectMemInstr> IM;
788 auto *Fn = MBB.getParent();
790 // Iterate over SuccBB's predecessor list.
791 for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
792 PE = SuccBB->pred_end(); PI != PE; ++PI)
793 if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
796 // Do not allow moving instructions which have unallocatable register operands
797 // across basic block boundaries.
798 RegDU.setUnallocatableRegs(*Fn);
800 // Only allow moving loads from stack or constants if any of the SuccBB's
801 // predecessors have multiple successors.
802 if (HasMultipleSuccs) {
803 IM.reset(new LoadFromStackOrConst());
805 const MachineFrameInfo &MFI = Fn->getFrameInfo();
806 IM.reset(new MemDefsUses(Fn->getDataLayout(), &MFI));
809 if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Slot,
813 insertDelayFiller(Filler, BrMap);
814 addLiveInRegs(Filler, *SuccBB);
815 Filler->eraseFromParent();
820 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
824 // Select the successor with the larget edge weight.
825 auto &Prob = getAnalysis<MachineBranchProbabilityInfo>();
826 MachineBasicBlock *S = *std::max_element(
827 B.succ_begin(), B.succ_end(),
828 [&](const MachineBasicBlock *Dst0, const MachineBasicBlock *Dst1) {
829 return Prob.getEdgeProbability(&B, Dst0) <
830 Prob.getEdgeProbability(&B, Dst1);
832 return S->isEHPad() ? nullptr : S;
835 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
836 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
837 const MipsInstrInfo *TII =
838 MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
839 MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr;
840 SmallVector<MachineInstr*, 2> BranchInstrs;
841 SmallVector<MachineOperand, 2> Cond;
843 MipsInstrInfo::BranchType R =
844 TII->analyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
846 if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
847 return std::make_pair(R, nullptr);
849 if (R != MipsInstrInfo::BT_CondUncond) {
850 if (!hasUnoccupiedSlot(BranchInstrs[0]))
851 return std::make_pair(MipsInstrInfo::BT_None, nullptr);
853 assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
855 return std::make_pair(R, BranchInstrs[0]);
858 assert((TrueBB == &Dst) || (FalseBB == &Dst));
860 // Examine the conditional branch. See if its slot is occupied.
861 if (hasUnoccupiedSlot(BranchInstrs[0]))
862 return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
864 // If that fails, try the unconditional branch.
865 if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
866 return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
868 return std::make_pair(MipsInstrInfo::BT_None, nullptr);
871 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
872 RegDefsUses &RegDU, bool &HasMultipleSuccs,
873 BB2BrMap &BrMap) const {
874 std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
875 getBranch(Pred, Succ);
877 // Return if either getBranch wasn't able to analyze the branches or there
878 // were no branches with unoccupied slots.
879 if (P.first == MipsInstrInfo::BT_None)
882 if ((P.first != MipsInstrInfo::BT_Uncond) &&
883 (P.first != MipsInstrInfo::BT_NoBranch)) {
884 HasMultipleSuccs = true;
885 RegDU.addLiveOut(Pred, Succ);
888 BrMap[&Pred] = P.second;
892 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
893 InspectMemInstr &IM) const {
894 assert(!Candidate.isKill() &&
895 "KILL instructions should have been eliminated at this point.");
897 bool HasHazard = Candidate.isImplicitDef();
899 HasHazard |= IM.hasHazard(Candidate);
900 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
905 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
906 return (Candidate.isTerminator() || Candidate.isCall() ||
907 Candidate.isPosition() || Candidate.isInlineAsm() ||
908 Candidate.hasUnmodeledSideEffects());
911 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
912 /// slots in Mips MachineFunctions
913 FunctionPass *llvm::createMipsDelaySlotFillerPass() { return new Filler(); }