1 //===-- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
15 //===----------------------------------------------------------------------===//
17 #include "MipsCCState.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsISelLowering.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "llvm/Analysis/TargetLibraryInfo.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/GetElementPtrTypeIterator.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Support/Debug.h"
36 #define DEBUG_TYPE "mips-fastisel"
42 class MipsFastISel final : public FastISel {
44 // All possible address modes.
47 typedef enum { RegBase, FrameIndexBase } BaseKind;
58 const GlobalValue *GV;
61 // Innocuous defaults for our address.
62 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
63 void setKind(BaseKind K) { Kind = K; }
64 BaseKind getKind() const { return Kind; }
65 bool isRegBase() const { return Kind == RegBase; }
66 bool isFIBase() const { return Kind == FrameIndexBase; }
67 void setReg(unsigned Reg) {
68 assert(isRegBase() && "Invalid base register access!");
71 unsigned getReg() const {
72 assert(isRegBase() && "Invalid base register access!");
75 void setFI(unsigned FI) {
76 assert(isFIBase() && "Invalid base frame index access!");
79 unsigned getFI() const {
80 assert(isFIBase() && "Invalid base frame index access!");
84 void setOffset(int64_t Offset_) { Offset = Offset_; }
85 int64_t getOffset() const { return Offset; }
86 void setGlobalValue(const GlobalValue *G) { GV = G; }
87 const GlobalValue *getGlobalValue() { return GV; }
90 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
91 /// make the right decision when generating code for different targets.
92 const TargetMachine &TM;
93 const MipsSubtarget *Subtarget;
94 const TargetInstrInfo &TII;
95 const TargetLowering &TLI;
96 MipsFunctionInfo *MFI;
98 // Convenience variables to avoid some queries.
101 bool fastLowerArguments() override;
102 bool fastLowerCall(CallLoweringInfo &CLI) override;
103 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
105 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
106 // floating point but not reject doing fast-isel in other
110 // Selection routines.
111 bool selectLogicalOp(const Instruction *I);
112 bool selectLoad(const Instruction *I);
113 bool selectStore(const Instruction *I);
114 bool selectBranch(const Instruction *I);
115 bool selectSelect(const Instruction *I);
116 bool selectCmp(const Instruction *I);
117 bool selectFPExt(const Instruction *I);
118 bool selectFPTrunc(const Instruction *I);
119 bool selectFPToInt(const Instruction *I, bool IsSigned);
120 bool selectRet(const Instruction *I);
121 bool selectTrunc(const Instruction *I);
122 bool selectIntExt(const Instruction *I);
123 bool selectShift(const Instruction *I);
124 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
126 // Utility helper routines.
127 bool isTypeLegal(Type *Ty, MVT &VT);
128 bool isTypeSupported(Type *Ty, MVT &VT);
129 bool isLoadTypeLegal(Type *Ty, MVT &VT);
130 bool computeAddress(const Value *Obj, Address &Addr);
131 bool computeCallAddress(const Value *V, Address &Addr);
132 void simplifyAddress(Address &Addr);
134 // Emit helper routines.
135 bool emitCmp(unsigned DestReg, const CmpInst *CI);
136 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
137 unsigned Alignment = 0);
138 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
139 MachineMemOperand *MMO = nullptr);
140 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
141 unsigned Alignment = 0);
142 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
143 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
146 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
148 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
149 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
151 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
154 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
156 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
159 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
160 unsigned materializeGV(const GlobalValue *GV, MVT VT);
161 unsigned materializeInt(const Constant *C, MVT VT);
162 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
163 unsigned materializeExternalCallSym(MCSymbol *Syn);
165 MachineInstrBuilder emitInst(unsigned Opc) {
166 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
168 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
169 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
172 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
173 unsigned MemReg, int64_t MemOffset) {
174 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
176 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
177 unsigned MemReg, int64_t MemOffset) {
178 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
181 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
182 const TargetRegisterClass *RC,
183 unsigned Op0, bool Op0IsKill,
184 unsigned Op1, bool Op1IsKill);
186 // for some reason, this default is not generated by tablegen
187 // so we explicitly generate it here.
189 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
190 unsigned Op0, bool Op0IsKill, uint64_t imm1,
191 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
195 // Call handling routines.
197 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
198 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
200 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
201 const MipsABIInfo &getABI() const {
202 return static_cast<const MipsTargetMachine &>(TM).getABI();
206 // Backend specific FastISel code.
207 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
208 const TargetLibraryInfo *libInfo)
209 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
210 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
211 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
212 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
213 Context = &funcInfo.Fn->getContext();
214 UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
217 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
218 unsigned fastMaterializeConstant(const Constant *C) override;
219 bool fastSelectInstruction(const Instruction *I) override;
221 #include "MipsGenFastISel.inc"
223 } // end anonymous namespace.
225 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
226 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
227 CCState &State) LLVM_ATTRIBUTE_UNUSED;
229 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
230 CCValAssign::LocInfo LocInfo,
231 ISD::ArgFlagsTy ArgFlags, CCState &State) {
232 llvm_unreachable("should not be called");
235 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
236 CCValAssign::LocInfo LocInfo,
237 ISD::ArgFlagsTy ArgFlags, CCState &State) {
238 llvm_unreachable("should not be called");
241 #include "MipsGenCallingConv.inc"
243 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
247 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
248 const Value *LHS, const Value *RHS) {
249 // Canonicalize immediates to the RHS first.
250 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
265 llvm_unreachable("unexpected opcode");
268 unsigned LHSReg = getRegForValue(LHS);
273 if (const auto *C = dyn_cast<ConstantInt>(RHS))
274 RHSReg = materializeInt(C, MVT::i32);
276 RHSReg = getRegForValue(RHS);
280 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
284 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
288 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
289 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
290 "Alloca should always return a pointer.");
292 DenseMap<const AllocaInst *, int>::iterator SI =
293 FuncInfo.StaticAllocaMap.find(AI);
295 if (SI != FuncInfo.StaticAllocaMap.end()) {
296 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
297 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
299 .addFrameIndex(SI->second)
307 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
308 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
310 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
311 const ConstantInt *CI = cast<ConstantInt>(C);
312 return materialize32BitInt(CI->getZExtValue(), RC);
315 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
316 const TargetRegisterClass *RC) {
317 unsigned ResultReg = createResultReg(RC);
319 if (isInt<16>(Imm)) {
320 unsigned Opc = Mips::ADDiu;
321 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
323 } else if (isUInt<16>(Imm)) {
324 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
327 unsigned Lo = Imm & 0xFFFF;
328 unsigned Hi = (Imm >> 16) & 0xFFFF;
330 // Both Lo and Hi have nonzero bits.
331 unsigned TmpReg = createResultReg(RC);
332 emitInst(Mips::LUi, TmpReg).addImm(Hi);
333 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
335 emitInst(Mips::LUi, ResultReg).addImm(Hi);
340 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
341 if (UnsupportedFPMode)
343 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
344 if (VT == MVT::f32) {
345 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
346 unsigned DestReg = createResultReg(RC);
347 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
348 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
350 } else if (VT == MVT::f64) {
351 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
352 unsigned DestReg = createResultReg(RC);
353 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
355 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
356 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
362 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
363 // For now 32-bit only.
366 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
367 unsigned DestReg = createResultReg(RC);
368 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
369 bool IsThreadLocal = GVar && GVar->isThreadLocal();
370 // TLS not supported at this time.
373 emitInst(Mips::LW, DestReg)
374 .addReg(MFI->getGlobalBaseReg())
375 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
376 if ((GV->hasInternalLinkage() ||
377 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
378 unsigned TempReg = createResultReg(RC);
379 emitInst(Mips::ADDiu, TempReg)
381 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
387 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
388 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
389 unsigned DestReg = createResultReg(RC);
390 emitInst(Mips::LW, DestReg)
391 .addReg(MFI->getGlobalBaseReg())
392 .addSym(Sym, MipsII::MO_GOT);
396 // Materialize a constant into a register, and return the register
397 // number (or zero if we failed to handle it).
398 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
399 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
401 // Only handle simple types.
402 if (!CEVT.isSimple())
404 MVT VT = CEVT.getSimpleVT();
406 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
407 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
408 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
409 return materializeGV(GV, VT);
410 else if (isa<ConstantInt>(C))
411 return materializeInt(C, VT);
416 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
418 const User *U = nullptr;
419 unsigned Opcode = Instruction::UserOp1;
420 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
421 // Don't walk into other basic blocks unless the object is an alloca from
422 // another block, otherwise it may not have a virtual register assigned.
423 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
424 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
425 Opcode = I->getOpcode();
428 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
429 Opcode = C->getOpcode();
435 case Instruction::BitCast: {
436 // Look through bitcasts.
437 return computeAddress(U->getOperand(0), Addr);
439 case Instruction::GetElementPtr: {
440 Address SavedAddr = Addr;
441 int64_t TmpOffset = Addr.getOffset();
442 // Iterate through the GEP folding the constants into offsets where
444 gep_type_iterator GTI = gep_type_begin(U);
445 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
447 const Value *Op = *i;
448 if (StructType *STy = GTI.getStructTypeOrNull()) {
449 const StructLayout *SL = DL.getStructLayout(STy);
450 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
451 TmpOffset += SL->getElementOffset(Idx);
453 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
455 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
456 // Constant-offset addressing.
457 TmpOffset += CI->getSExtValue() * S;
460 if (canFoldAddIntoGEP(U, Op)) {
461 // A compatible add with a constant operand. Fold the constant.
463 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
464 TmpOffset += CI->getSExtValue() * S;
465 // Iterate on the other operand.
466 Op = cast<AddOperator>(Op)->getOperand(0);
470 goto unsupported_gep;
474 // Try to grab the base operand now.
475 Addr.setOffset(TmpOffset);
476 if (computeAddress(U->getOperand(0), Addr))
478 // We failed, restore everything and try the other options.
483 case Instruction::Alloca: {
484 const AllocaInst *AI = cast<AllocaInst>(Obj);
485 DenseMap<const AllocaInst *, int>::iterator SI =
486 FuncInfo.StaticAllocaMap.find(AI);
487 if (SI != FuncInfo.StaticAllocaMap.end()) {
488 Addr.setKind(Address::FrameIndexBase);
489 Addr.setFI(SI->second);
495 Addr.setReg(getRegForValue(Obj));
496 return Addr.getReg() != 0;
499 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
500 const User *U = nullptr;
501 unsigned Opcode = Instruction::UserOp1;
503 if (const auto *I = dyn_cast<Instruction>(V)) {
504 // Check if the value is defined in the same basic block. This information
505 // is crucial to know whether or not folding an operand is valid.
506 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
507 Opcode = I->getOpcode();
510 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
511 Opcode = C->getOpcode();
518 case Instruction::BitCast:
519 // Look past bitcasts if its operand is in the same BB.
520 return computeCallAddress(U->getOperand(0), Addr);
522 case Instruction::IntToPtr:
523 // Look past no-op inttoptrs if its operand is in the same BB.
524 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
525 TLI.getPointerTy(DL))
526 return computeCallAddress(U->getOperand(0), Addr);
528 case Instruction::PtrToInt:
529 // Look past no-op ptrtoints if its operand is in the same BB.
530 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
531 return computeCallAddress(U->getOperand(0), Addr);
535 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
536 Addr.setGlobalValue(GV);
540 // If all else fails, try to materialize the value in a register.
541 if (!Addr.getGlobalValue()) {
542 Addr.setReg(getRegForValue(V));
543 return Addr.getReg() != 0;
549 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
550 EVT evt = TLI.getValueType(DL, Ty, true);
551 // Only handle simple types.
552 if (evt == MVT::Other || !evt.isSimple())
554 VT = evt.getSimpleVT();
556 // Handle all legal types, i.e. a register that will directly hold this
558 return TLI.isTypeLegal(VT);
561 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
562 if (Ty->isVectorTy())
565 if (isTypeLegal(Ty, VT))
568 // If this is a type than can be sign or zero-extended to a basic operation
569 // go ahead and accept it now.
570 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
576 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
577 if (isTypeLegal(Ty, VT))
579 // We will extend this in a later patch:
580 // If this is a type than can be sign or zero-extended to a basic operation
581 // go ahead and accept it now.
582 if (VT == MVT::i8 || VT == MVT::i16)
586 // Because of how EmitCmp is called with fast-isel, you can
587 // end up with redundant "andi" instructions after the sequences emitted below.
588 // We should try and solve this issue in the future.
590 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
591 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
592 bool IsUnsigned = CI->isUnsigned();
593 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
596 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
599 CmpInst::Predicate P = CI->getPredicate();
604 case CmpInst::ICMP_EQ: {
605 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
606 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
607 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
610 case CmpInst::ICMP_NE: {
611 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
612 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
613 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
616 case CmpInst::ICMP_UGT: {
617 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
620 case CmpInst::ICMP_ULT: {
621 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
624 case CmpInst::ICMP_UGE: {
625 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
626 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
627 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
630 case CmpInst::ICMP_ULE: {
631 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
632 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
633 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
636 case CmpInst::ICMP_SGT: {
637 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
640 case CmpInst::ICMP_SLT: {
641 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
644 case CmpInst::ICMP_SGE: {
645 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
646 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
647 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
650 case CmpInst::ICMP_SLE: {
651 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
652 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
653 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
656 case CmpInst::FCMP_OEQ:
657 case CmpInst::FCMP_UNE:
658 case CmpInst::FCMP_OLT:
659 case CmpInst::FCMP_OLE:
660 case CmpInst::FCMP_OGT:
661 case CmpInst::FCMP_OGE: {
662 if (UnsupportedFPMode)
664 bool IsFloat = Left->getType()->isFloatTy();
665 bool IsDouble = Left->getType()->isDoubleTy();
666 if (!IsFloat && !IsDouble)
668 unsigned Opc, CondMovOpc;
670 case CmpInst::FCMP_OEQ:
671 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
672 CondMovOpc = Mips::MOVT_I;
674 case CmpInst::FCMP_UNE:
675 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
676 CondMovOpc = Mips::MOVF_I;
678 case CmpInst::FCMP_OLT:
679 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
680 CondMovOpc = Mips::MOVT_I;
682 case CmpInst::FCMP_OLE:
683 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
684 CondMovOpc = Mips::MOVT_I;
686 case CmpInst::FCMP_OGT:
687 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
688 CondMovOpc = Mips::MOVF_I;
690 case CmpInst::FCMP_OGE:
691 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
692 CondMovOpc = Mips::MOVF_I;
695 llvm_unreachable("Only switching of a subset of CCs.");
697 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
698 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
699 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
700 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
701 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
702 Mips::FCC0, RegState::ImplicitDefine);
703 emitInst(CondMovOpc, ResultReg)
706 .addReg(RegWithZero);
712 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
713 unsigned Alignment) {
715 // more cases will be handled here in following patches.
718 switch (VT.SimpleTy) {
720 ResultReg = createResultReg(&Mips::GPR32RegClass);
725 ResultReg = createResultReg(&Mips::GPR32RegClass);
730 ResultReg = createResultReg(&Mips::GPR32RegClass);
735 if (UnsupportedFPMode)
737 ResultReg = createResultReg(&Mips::FGR32RegClass);
742 if (UnsupportedFPMode)
744 ResultReg = createResultReg(&Mips::AFGR64RegClass);
751 if (Addr.isRegBase()) {
752 simplifyAddress(Addr);
753 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
756 if (Addr.isFIBase()) {
757 unsigned FI = Addr.getFI();
759 int64_t Offset = Addr.getOffset();
760 MachineFrameInfo &MFI = MF->getFrameInfo();
761 MachineMemOperand *MMO = MF->getMachineMemOperand(
762 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
763 MFI.getObjectSize(FI), Align);
764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
773 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
774 unsigned Alignment) {
776 // more cases will be handled here in following patches.
779 switch (VT.SimpleTy) {
790 if (UnsupportedFPMode)
795 if (UnsupportedFPMode)
802 if (Addr.isRegBase()) {
803 simplifyAddress(Addr);
804 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
807 if (Addr.isFIBase()) {
808 unsigned FI = Addr.getFI();
810 int64_t Offset = Addr.getOffset();
811 MachineFrameInfo &MFI = MF->getFrameInfo();
812 MachineMemOperand *MMO = MF->getMachineMemOperand(
813 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
814 MFI.getObjectSize(FI), Align);
815 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
825 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
827 if (!isTypeSupported(I->getType(), VT))
831 switch (I->getOpcode()) {
833 llvm_unreachable("Unexpected instruction.");
834 case Instruction::And:
835 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
837 case Instruction::Or:
838 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
840 case Instruction::Xor:
841 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
848 updateValueMap(I, ResultReg);
852 bool MipsFastISel::selectLoad(const Instruction *I) {
853 // Atomic loads need special handling.
854 if (cast<LoadInst>(I)->isAtomic())
857 // Verify we have a legal type before going any further.
859 if (!isLoadTypeLegal(I->getType(), VT))
862 // See if we can handle this address.
864 if (!computeAddress(I->getOperand(0), Addr))
868 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
870 updateValueMap(I, ResultReg);
874 bool MipsFastISel::selectStore(const Instruction *I) {
875 Value *Op0 = I->getOperand(0);
878 // Atomic stores need special handling.
879 if (cast<StoreInst>(I)->isAtomic())
882 // Verify we have a legal type before going any further.
884 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
887 // Get the value to be stored into a register.
888 SrcReg = getRegForValue(Op0);
892 // See if we can handle this address.
894 if (!computeAddress(I->getOperand(1), Addr))
897 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
903 // This can cause a redundant sltiu to be generated.
904 // FIXME: try and eliminate this in a future patch.
906 bool MipsFastISel::selectBranch(const Instruction *I) {
907 const BranchInst *BI = cast<BranchInst>(I);
908 MachineBasicBlock *BrBB = FuncInfo.MBB;
910 // TBB is the basic block for the case where the comparison is true.
911 // FBB is the basic block for the case where the comparison is false.
912 // if (cond) goto TBB
916 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
917 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
919 // For now, just try the simplest case where it's fed by a compare.
920 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
921 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
922 if (!emitCmp(CondReg, CI))
924 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
927 finishCondBranch(BI->getParent(), TBB, FBB);
933 bool MipsFastISel::selectCmp(const Instruction *I) {
934 const CmpInst *CI = cast<CmpInst>(I);
935 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
936 if (!emitCmp(ResultReg, CI))
938 updateValueMap(I, ResultReg);
942 // Attempt to fast-select a floating-point extend instruction.
943 bool MipsFastISel::selectFPExt(const Instruction *I) {
944 if (UnsupportedFPMode)
946 Value *Src = I->getOperand(0);
947 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
948 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
950 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
954 getRegForValue(Src); // this must be a 32bit floating point register class
955 // maybe we should handle this differently
959 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
960 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
961 updateValueMap(I, DestReg);
965 bool MipsFastISel::selectSelect(const Instruction *I) {
966 assert(isa<SelectInst>(I) && "Expected a select instruction.");
968 DEBUG(dbgs() << "selectSelect\n");
971 if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
972 DEBUG(dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
977 const TargetRegisterClass *RC;
979 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
980 CondMovOpc = Mips::MOVN_I_I;
981 RC = &Mips::GPR32RegClass;
982 } else if (VT == MVT::f32) {
983 CondMovOpc = Mips::MOVN_I_S;
984 RC = &Mips::FGR32RegClass;
985 } else if (VT == MVT::f64) {
986 CondMovOpc = Mips::MOVN_I_D32;
987 RC = &Mips::AFGR64RegClass;
991 const SelectInst *SI = cast<SelectInst>(I);
992 const Value *Cond = SI->getCondition();
993 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
994 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
995 unsigned CondReg = getRegForValue(Cond);
997 if (!Src1Reg || !Src2Reg || !CondReg)
1000 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1004 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1007 unsigned ResultReg = createResultReg(RC);
1008 unsigned TempReg = createResultReg(RC);
1010 if (!ResultReg || !TempReg)
1013 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1014 emitInst(CondMovOpc, ResultReg)
1015 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1016 updateValueMap(I, ResultReg);
1020 // Attempt to fast-select a floating-point truncate instruction.
1021 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1022 if (UnsupportedFPMode)
1024 Value *Src = I->getOperand(0);
1025 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1026 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1028 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1031 unsigned SrcReg = getRegForValue(Src);
1035 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1039 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1040 updateValueMap(I, DestReg);
1044 // Attempt to fast-select a floating-point-to-integer conversion.
1045 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1046 if (UnsupportedFPMode)
1050 return false; // We don't handle this case yet. There is no native
1051 // instruction for this but it can be synthesized.
1052 Type *DstTy = I->getType();
1053 if (!isTypeLegal(DstTy, DstVT))
1056 if (DstVT != MVT::i32)
1059 Value *Src = I->getOperand(0);
1060 Type *SrcTy = Src->getType();
1061 if (!isTypeLegal(SrcTy, SrcVT))
1064 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1067 unsigned SrcReg = getRegForValue(Src);
1071 // Determine the opcode for the conversion, which takes place
1072 // entirely within FPRs.
1073 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1074 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1075 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1077 // Generate the convert.
1078 emitInst(Opc, TempReg).addReg(SrcReg);
1079 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1081 updateValueMap(I, DestReg);
1085 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1086 SmallVectorImpl<MVT> &OutVTs,
1087 unsigned &NumBytes) {
1088 CallingConv::ID CC = CLI.CallConv;
1089 SmallVector<CCValAssign, 16> ArgLocs;
1090 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1091 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1092 // Get a count of how many bytes are to be pushed on the stack.
1093 NumBytes = CCInfo.getNextStackOffset();
1094 // This is the minimum argument area used for A0-A3.
1098 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1099 // Process the args.
1101 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1102 CCValAssign &VA = ArgLocs[i];
1103 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1104 MVT ArgVT = OutVTs[VA.getValNo()];
1108 if (ArgVT == MVT::f32) {
1109 VA.convertToReg(Mips::F12);
1110 } else if (ArgVT == MVT::f64) {
1111 VA.convertToReg(Mips::D6);
1113 } else if (i == 1) {
1114 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1115 if (ArgVT == MVT::f32) {
1116 VA.convertToReg(Mips::F14);
1117 } else if (ArgVT == MVT::f64) {
1118 VA.convertToReg(Mips::D7);
1122 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1123 (ArgVT == MVT::i8)) &&
1125 switch (VA.getLocMemOffset()) {
1127 VA.convertToReg(Mips::A0);
1130 VA.convertToReg(Mips::A1);
1133 VA.convertToReg(Mips::A2);
1136 VA.convertToReg(Mips::A3);
1142 unsigned ArgReg = getRegForValue(ArgVal);
1146 // Handle arg promotion: SExt, ZExt, AExt.
1147 switch (VA.getLocInfo()) {
1148 case CCValAssign::Full:
1150 case CCValAssign::AExt:
1151 case CCValAssign::SExt: {
1152 MVT DestVT = VA.getLocVT();
1154 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1159 case CCValAssign::ZExt: {
1160 MVT DestVT = VA.getLocVT();
1162 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1168 llvm_unreachable("Unknown arg promotion!");
1171 // Now copy/store arg to correct locations.
1172 if (VA.isRegLoc() && !VA.needsCustom()) {
1173 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1174 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1175 CLI.OutRegs.push_back(VA.getLocReg());
1176 } else if (VA.needsCustom()) {
1177 llvm_unreachable("Mips does not use custom args.");
1181 // FIXME: This path will currently return false. It was copied
1182 // from the AArch64 port and should be essentially fine for Mips too.
1183 // The work to finish up this path will be done in a follow-on patch.
1185 assert(VA.isMemLoc() && "Assuming store on stack.");
1186 // Don't emit stores for undef values.
1187 if (isa<UndefValue>(ArgVal))
1190 // Need to store on the stack.
1191 // FIXME: This alignment is incorrect but this path is disabled
1192 // for now (will return false). We need to determine the right alignment
1193 // based on the normal alignment for the underlying machine type.
1195 unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1197 unsigned BEAlign = 0;
1198 if (ArgSize < 8 && !Subtarget->isLittle())
1199 BEAlign = 8 - ArgSize;
1202 Addr.setKind(Address::RegBase);
1203 Addr.setReg(Mips::SP);
1204 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1206 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1207 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1208 MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1209 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1211 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1212 return false; // can't store on the stack yet.
1219 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1220 unsigned NumBytes) {
1221 CallingConv::ID CC = CLI.CallConv;
1222 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1223 if (RetVT != MVT::isVoid) {
1224 SmallVector<CCValAssign, 16> RVLocs;
1225 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1226 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1228 // Only handle a single return value.
1229 if (RVLocs.size() != 1)
1231 // Copy all of the result registers out of their specified physreg.
1232 MVT CopyVT = RVLocs[0].getValVT();
1233 // Special handling for extended integers.
1234 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1237 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1240 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1241 TII.get(TargetOpcode::COPY),
1242 ResultReg).addReg(RVLocs[0].getLocReg());
1243 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1245 CLI.ResultReg = ResultReg;
1246 CLI.NumResultRegs = 1;
1251 bool MipsFastISel::fastLowerArguments() {
1252 DEBUG(dbgs() << "fastLowerArguments\n");
1254 if (!FuncInfo.CanLowerReturn) {
1255 DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1259 const Function *F = FuncInfo.Fn;
1260 if (F->isVarArg()) {
1261 DEBUG(dbgs() << ".. gave up (varargs)\n");
1265 CallingConv::ID CC = F->getCallingConv();
1266 if (CC != CallingConv::C) {
1267 DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1271 const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
1273 const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};
1274 const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};
1275 ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();
1276 ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();
1277 ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();
1279 struct AllocatedReg {
1280 const TargetRegisterClass *RC;
1282 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1283 : RC(RC), Reg(Reg) {}
1286 // Only handle simple cases. i.e. All arguments are directly mapped to
1287 // registers of the appropriate type.
1288 SmallVector<AllocatedReg, 4> Allocation;
1290 for (const auto &FormalArg : F->args()) {
1291 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
1292 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
1293 F->getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
1294 DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1298 Type *ArgTy = FormalArg.getType();
1299 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1300 DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1304 EVT ArgVT = TLI.getValueType(DL, ArgTy);
1305 DEBUG(dbgs() << ".. " << (Idx - 1) << ": " << ArgVT.getEVTString() << "\n");
1306 if (!ArgVT.isSimple()) {
1307 DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1311 switch (ArgVT.getSimpleVT().SimpleTy) {
1315 if (!F->getAttributes().hasAttribute(Idx, Attribute::SExt) &&
1316 !F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) {
1317 // It must be any extend, this shouldn't happen for clang-generated IR
1318 // so just fall back on SelectionDAG.
1319 DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1323 if (NextGPR32 == GPR32ArgRegs.end()) {
1324 DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1328 DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1329 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1331 // Allocating any GPR32 prohibits further use of floating point arguments.
1332 NextFGR32 = FGR32ArgRegs.end();
1333 NextAFGR64 = AFGR64ArgRegs.end();
1337 if (F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) {
1338 // The O32 ABI does not permit a zero-extended i32.
1339 DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1343 if (NextGPR32 == GPR32ArgRegs.end()) {
1344 DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1348 DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1349 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1351 // Allocating any GPR32 prohibits further use of floating point arguments.
1352 NextFGR32 = FGR32ArgRegs.end();
1353 NextAFGR64 = AFGR64ArgRegs.end();
1357 if (UnsupportedFPMode) {
1358 DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1361 if (NextFGR32 == FGR32ArgRegs.end()) {
1362 DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1365 DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1366 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1367 // Allocating an FGR32 also allocates the super-register AFGR64, and
1368 // ABI rules require us to skip the corresponding GPR32.
1369 if (NextGPR32 != GPR32ArgRegs.end())
1371 if (NextAFGR64 != AFGR64ArgRegs.end())
1376 if (UnsupportedFPMode) {
1377 DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1380 if (NextAFGR64 == AFGR64ArgRegs.end()) {
1381 DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1384 DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1385 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1386 // Allocating an FGR32 also allocates the super-register AFGR64, and
1387 // ABI rules require us to skip the corresponding GPR32 pair.
1388 if (NextGPR32 != GPR32ArgRegs.end())
1390 if (NextGPR32 != GPR32ArgRegs.end())
1392 if (NextFGR32 != FGR32ArgRegs.end())
1397 DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1405 for (const auto &FormalArg : F->args()) {
1406 unsigned SrcReg = Allocation[Idx].Reg;
1407 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[Idx].RC);
1408 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1409 // Without this, EmitLiveInCopies may eliminate the livein if its only
1410 // use is a bitcast (which isn't turned into an instruction).
1411 unsigned ResultReg = createResultReg(Allocation[Idx].RC);
1412 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1413 TII.get(TargetOpcode::COPY), ResultReg)
1414 .addReg(DstReg, getKillRegState(true));
1415 updateValueMap(&FormalArg, ResultReg);
1419 // Calculate the size of the incoming arguments area.
1420 // We currently reject all the cases where this would be non-zero.
1421 unsigned IncomingArgSizeInBytes = 0;
1423 // Account for the reserved argument area on ABI's that have one (O32).
1424 // It seems strange to do this on the caller side but it's necessary in
1425 // SelectionDAG's implementation.
1426 IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1427 IncomingArgSizeInBytes);
1429 MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1435 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1436 CallingConv::ID CC = CLI.CallConv;
1437 bool IsTailCall = CLI.IsTailCall;
1438 bool IsVarArg = CLI.IsVarArg;
1439 const Value *Callee = CLI.Callee;
1440 MCSymbol *Symbol = CLI.Symbol;
1442 // Do not handle FastCC.
1443 if (CC == CallingConv::Fast)
1446 // Allow SelectionDAG isel to handle tail calls.
1450 // Let SDISel handle vararg functions.
1454 // FIXME: Only handle *simple* calls for now.
1456 if (CLI.RetTy->isVoidTy())
1457 RetVT = MVT::isVoid;
1458 else if (!isTypeSupported(CLI.RetTy, RetVT))
1461 for (auto Flag : CLI.OutFlags)
1462 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1465 // Set up the argument vectors.
1466 SmallVector<MVT, 16> OutVTs;
1467 OutVTs.reserve(CLI.OutVals.size());
1469 for (auto *Val : CLI.OutVals) {
1471 if (!isTypeLegal(Val->getType(), VT) &&
1472 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1475 // We don't handle vector parameters yet.
1476 if (VT.isVector() || VT.getSizeInBits() > 64)
1479 OutVTs.push_back(VT);
1483 if (!computeCallAddress(Callee, Addr))
1486 // Handle the arguments now that we've gotten them.
1488 if (!processCallArgs(CLI, OutVTs, NumBytes))
1491 if (!Addr.getGlobalValue())
1495 unsigned DestAddress;
1497 DestAddress = materializeExternalCallSym(Symbol);
1499 DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1500 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1501 MachineInstrBuilder MIB =
1502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1503 Mips::RA).addReg(Mips::T9);
1505 // Add implicit physical register uses to the call.
1506 for (auto Reg : CLI.OutRegs)
1507 MIB.addReg(Reg, RegState::Implicit);
1509 // Add a register mask with the call-preserved registers.
1510 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1511 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1515 // Finish off the call including any return values.
1516 return finishCall(CLI, RetVT, NumBytes);
1519 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1520 switch (II->getIntrinsicID()) {
1523 case Intrinsic::bswap: {
1524 Type *RetTy = II->getCalledFunction()->getReturnType();
1527 if (!isTypeSupported(RetTy, VT))
1530 unsigned SrcReg = getRegForValue(II->getOperand(0));
1533 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1536 if (VT == MVT::i16) {
1537 if (Subtarget->hasMips32r2()) {
1538 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1539 updateValueMap(II, DestReg);
1542 unsigned TempReg[3];
1543 for (int i = 0; i < 3; i++) {
1544 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1545 if (TempReg[i] == 0)
1548 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1549 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1550 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1551 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1552 updateValueMap(II, DestReg);
1555 } else if (VT == MVT::i32) {
1556 if (Subtarget->hasMips32r2()) {
1557 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1558 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1559 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1560 updateValueMap(II, DestReg);
1563 unsigned TempReg[8];
1564 for (int i = 0; i < 8; i++) {
1565 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1566 if (TempReg[i] == 0)
1570 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1571 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1572 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1573 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1575 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1576 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1578 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1579 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1580 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1581 updateValueMap(II, DestReg);
1587 case Intrinsic::memcpy:
1588 case Intrinsic::memmove: {
1589 const auto *MTI = cast<MemTransferInst>(II);
1590 // Don't handle volatile.
1591 if (MTI->isVolatile())
1593 if (!MTI->getLength()->getType()->isIntegerTy(32))
1595 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1596 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1598 case Intrinsic::memset: {
1599 const MemSetInst *MSI = cast<MemSetInst>(II);
1600 // Don't handle volatile.
1601 if (MSI->isVolatile())
1603 if (!MSI->getLength()->getType()->isIntegerTy(32))
1605 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1611 bool MipsFastISel::selectRet(const Instruction *I) {
1612 const Function &F = *I->getParent()->getParent();
1613 const ReturnInst *Ret = cast<ReturnInst>(I);
1615 DEBUG(dbgs() << "selectRet\n");
1617 if (!FuncInfo.CanLowerReturn)
1620 // Build a list of return value registers.
1621 SmallVector<unsigned, 4> RetRegs;
1623 if (Ret->getNumOperands() > 0) {
1624 CallingConv::ID CC = F.getCallingConv();
1626 // Do not handle FastCC.
1627 if (CC == CallingConv::Fast)
1630 SmallVector<ISD::OutputArg, 4> Outs;
1631 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1633 // Analyze operands of the call, assigning locations to each operand.
1634 SmallVector<CCValAssign, 16> ValLocs;
1635 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1637 CCAssignFn *RetCC = RetCC_Mips;
1638 CCInfo.AnalyzeReturn(Outs, RetCC);
1640 // Only handle a single return value for now.
1641 if (ValLocs.size() != 1)
1644 CCValAssign &VA = ValLocs[0];
1645 const Value *RV = Ret->getOperand(0);
1647 // Don't bother handling odd stuff for now.
1648 if ((VA.getLocInfo() != CCValAssign::Full) &&
1649 (VA.getLocInfo() != CCValAssign::BCvt))
1652 // Only handle register returns for now.
1656 unsigned Reg = getRegForValue(RV);
1660 unsigned SrcReg = Reg + VA.getValNo();
1661 unsigned DestReg = VA.getLocReg();
1662 // Avoid a cross-class copy. This is very unlikely.
1663 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1666 EVT RVEVT = TLI.getValueType(DL, RV->getType());
1667 if (!RVEVT.isSimple())
1670 if (RVEVT.isVector())
1673 MVT RVVT = RVEVT.getSimpleVT();
1674 if (RVVT == MVT::f128)
1677 // Do not handle FGR64 returns for now.
1678 if (RVVT == MVT::f64 && UnsupportedFPMode) {
1679 DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1683 MVT DestVT = VA.getValVT();
1684 // Special handling for extended integers.
1685 if (RVVT != DestVT) {
1686 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1689 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1690 bool IsZExt = Outs[0].Flags.isZExt();
1691 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1698 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1699 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1701 // Add register to return instruction.
1702 RetRegs.push_back(VA.getLocReg());
1704 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1705 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1706 MIB.addReg(RetRegs[i], RegState::Implicit);
1710 bool MipsFastISel::selectTrunc(const Instruction *I) {
1711 // The high bits for a type smaller than the register size are assumed to be
1713 Value *Op = I->getOperand(0);
1716 SrcVT = TLI.getValueType(DL, Op->getType(), true);
1717 DestVT = TLI.getValueType(DL, I->getType(), true);
1719 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1721 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1724 unsigned SrcReg = getRegForValue(Op);
1728 // Because the high bits are undefined, a truncate doesn't generate
1730 updateValueMap(I, SrcReg);
1733 bool MipsFastISel::selectIntExt(const Instruction *I) {
1734 Type *DestTy = I->getType();
1735 Value *Src = I->getOperand(0);
1736 Type *SrcTy = Src->getType();
1738 bool isZExt = isa<ZExtInst>(I);
1739 unsigned SrcReg = getRegForValue(Src);
1743 EVT SrcEVT, DestEVT;
1744 SrcEVT = TLI.getValueType(DL, SrcTy, true);
1745 DestEVT = TLI.getValueType(DL, DestTy, true);
1746 if (!SrcEVT.isSimple())
1748 if (!DestEVT.isSimple())
1751 MVT SrcVT = SrcEVT.getSimpleVT();
1752 MVT DestVT = DestEVT.getSimpleVT();
1753 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1755 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1757 updateValueMap(I, ResultReg);
1760 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1763 switch (SrcVT.SimpleTy) {
1773 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1774 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1775 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1779 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1781 switch (SrcVT.SimpleTy) {
1785 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1788 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1794 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1796 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1798 if (Subtarget->hasMips32r2())
1799 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1800 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1803 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1807 switch (SrcVT.SimpleTy) {
1821 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1825 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1826 unsigned DestReg, bool IsZExt) {
1827 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1828 // DestVT are odd things, so test to make sure that they are both types we can
1829 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1830 // bail out to SelectionDAG.
1831 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1832 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1835 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1836 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1839 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1841 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1842 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1843 return Success ? DestReg : 0;
1846 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1847 EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1848 if (!DestEVT.isSimple())
1851 MVT DestVT = DestEVT.getSimpleVT();
1852 if (DestVT != MVT::i32)
1856 switch (ISDOpcode) {
1861 DivOpc = Mips::SDIV;
1865 DivOpc = Mips::UDIV;
1869 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1870 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1871 if (!Src0Reg || !Src1Reg)
1874 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1875 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1877 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1881 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1884 emitInst(MFOpc, ResultReg);
1886 updateValueMap(I, ResultReg);
1890 bool MipsFastISel::selectShift(const Instruction *I) {
1893 if (!isTypeSupported(I->getType(), RetVT))
1896 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1900 unsigned Opcode = I->getOpcode();
1901 const Value *Op0 = I->getOperand(0);
1902 unsigned Op0Reg = getRegForValue(Op0);
1906 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1907 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1908 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1912 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1913 bool IsZExt = Opcode == Instruction::LShr;
1914 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1920 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1921 uint64_t ShiftVal = C->getZExtValue();
1925 llvm_unreachable("Unexpected instruction.");
1926 case Instruction::Shl:
1929 case Instruction::AShr:
1932 case Instruction::LShr:
1937 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1938 updateValueMap(I, ResultReg);
1942 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1948 llvm_unreachable("Unexpected instruction.");
1949 case Instruction::Shl:
1950 Opcode = Mips::SLLV;
1952 case Instruction::AShr:
1953 Opcode = Mips::SRAV;
1955 case Instruction::LShr:
1956 Opcode = Mips::SRLV;
1960 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1961 updateValueMap(I, ResultReg);
1965 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1966 switch (I->getOpcode()) {
1969 case Instruction::Load:
1970 return selectLoad(I);
1971 case Instruction::Store:
1972 return selectStore(I);
1973 case Instruction::SDiv:
1974 if (!selectBinaryOp(I, ISD::SDIV))
1975 return selectDivRem(I, ISD::SDIV);
1977 case Instruction::UDiv:
1978 if (!selectBinaryOp(I, ISD::UDIV))
1979 return selectDivRem(I, ISD::UDIV);
1981 case Instruction::SRem:
1982 if (!selectBinaryOp(I, ISD::SREM))
1983 return selectDivRem(I, ISD::SREM);
1985 case Instruction::URem:
1986 if (!selectBinaryOp(I, ISD::UREM))
1987 return selectDivRem(I, ISD::UREM);
1989 case Instruction::Shl:
1990 case Instruction::LShr:
1991 case Instruction::AShr:
1992 return selectShift(I);
1993 case Instruction::And:
1994 case Instruction::Or:
1995 case Instruction::Xor:
1996 return selectLogicalOp(I);
1997 case Instruction::Br:
1998 return selectBranch(I);
1999 case Instruction::Ret:
2000 return selectRet(I);
2001 case Instruction::Trunc:
2002 return selectTrunc(I);
2003 case Instruction::ZExt:
2004 case Instruction::SExt:
2005 return selectIntExt(I);
2006 case Instruction::FPTrunc:
2007 return selectFPTrunc(I);
2008 case Instruction::FPExt:
2009 return selectFPExt(I);
2010 case Instruction::FPToSI:
2011 return selectFPToInt(I, /*isSigned*/ true);
2012 case Instruction::FPToUI:
2013 return selectFPToInt(I, /*isSigned*/ false);
2014 case Instruction::ICmp:
2015 case Instruction::FCmp:
2016 return selectCmp(I);
2017 case Instruction::Select:
2018 return selectSelect(I);
2023 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2025 unsigned VReg = getRegForValue(V);
2028 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2029 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2030 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2031 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2038 void MipsFastISel::simplifyAddress(Address &Addr) {
2039 if (!isInt<16>(Addr.getOffset())) {
2041 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2042 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2043 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2044 Addr.setReg(DestReg);
2049 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2050 const TargetRegisterClass *RC,
2051 unsigned Op0, bool Op0IsKill,
2052 unsigned Op1, bool Op1IsKill) {
2053 // We treat the MUL instruction in a special way because it clobbers
2054 // the HI0 & LO0 registers. The TableGen definition of this instruction can
2055 // mark these registers only as implicitly defined. As a result, the
2056 // register allocator runs out of registers when this instruction is
2057 // followed by another instruction that defines the same registers too.
2058 // We can fix this by explicitly marking those registers as dead.
2059 if (MachineInstOpcode == Mips::MUL) {
2060 unsigned ResultReg = createResultReg(RC);
2061 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2062 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2063 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2065 .addReg(Op0, getKillRegState(Op0IsKill))
2066 .addReg(Op1, getKillRegState(Op1IsKill))
2067 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2068 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2072 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2077 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2078 const TargetLibraryInfo *libInfo) {
2079 return new MipsFastISel(funcInfo, libInfo);