1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
15 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsCCState.h"
20 #include "MipsISelLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Analysis/TargetLibraryInfo.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/MachineValueType.h"
40 #include "llvm/CodeGen/TargetInstrInfo.h"
41 #include "llvm/CodeGen/TargetLowering.h"
42 #include "llvm/CodeGen/ValueTypes.h"
43 #include "llvm/IR/Attributes.h"
44 #include "llvm/IR/CallingConv.h"
45 #include "llvm/IR/Constant.h"
46 #include "llvm/IR/Constants.h"
47 #include "llvm/IR/DataLayout.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GetElementPtrTypeIterator.h"
50 #include "llvm/IR/GlobalValue.h"
51 #include "llvm/IR/GlobalVariable.h"
52 #include "llvm/IR/InstrTypes.h"
53 #include "llvm/IR/Instruction.h"
54 #include "llvm/IR/Instructions.h"
55 #include "llvm/IR/IntrinsicInst.h"
56 #include "llvm/IR/Operator.h"
57 #include "llvm/IR/Type.h"
58 #include "llvm/IR/User.h"
59 #include "llvm/IR/Value.h"
60 #include "llvm/MC/MCInstrDesc.h"
61 #include "llvm/MC/MCRegisterInfo.h"
62 #include "llvm/MC/MCSymbol.h"
63 #include "llvm/Support/Casting.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/Debug.h"
66 #include "llvm/Support/ErrorHandling.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Support/raw_ostream.h"
73 #define DEBUG_TYPE "mips-fastisel"
79 class MipsFastISel final : public FastISel {
81 // All possible address modes.
84 using BaseKind = enum { RegBase, FrameIndexBase };
87 BaseKind Kind = RegBase;
95 const GlobalValue *GV = nullptr;
98 // Innocuous defaults for our address.
99 Address() { Base.Reg = 0; }
101 void setKind(BaseKind K) { Kind = K; }
102 BaseKind getKind() const { return Kind; }
103 bool isRegBase() const { return Kind == RegBase; }
104 bool isFIBase() const { return Kind == FrameIndexBase; }
106 void setReg(unsigned Reg) {
107 assert(isRegBase() && "Invalid base register access!");
111 unsigned getReg() const {
112 assert(isRegBase() && "Invalid base register access!");
116 void setFI(unsigned FI) {
117 assert(isFIBase() && "Invalid base frame index access!");
121 unsigned getFI() const {
122 assert(isFIBase() && "Invalid base frame index access!");
126 void setOffset(int64_t Offset_) { Offset = Offset_; }
127 int64_t getOffset() const { return Offset; }
128 void setGlobalValue(const GlobalValue *G) { GV = G; }
129 const GlobalValue *getGlobalValue() { return GV; }
132 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
133 /// make the right decision when generating code for different targets.
134 const TargetMachine &TM;
135 const MipsSubtarget *Subtarget;
136 const TargetInstrInfo &TII;
137 const TargetLowering &TLI;
138 MipsFunctionInfo *MFI;
140 // Convenience variables to avoid some queries.
141 LLVMContext *Context;
143 bool fastLowerArguments() override;
144 bool fastLowerCall(CallLoweringInfo &CLI) override;
145 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
147 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
148 // floating point but not reject doing fast-isel in other
152 // Selection routines.
153 bool selectLogicalOp(const Instruction *I);
154 bool selectLoad(const Instruction *I);
155 bool selectStore(const Instruction *I);
156 bool selectBranch(const Instruction *I);
157 bool selectSelect(const Instruction *I);
158 bool selectCmp(const Instruction *I);
159 bool selectFPExt(const Instruction *I);
160 bool selectFPTrunc(const Instruction *I);
161 bool selectFPToInt(const Instruction *I, bool IsSigned);
162 bool selectRet(const Instruction *I);
163 bool selectTrunc(const Instruction *I);
164 bool selectIntExt(const Instruction *I);
165 bool selectShift(const Instruction *I);
166 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
168 // Utility helper routines.
169 bool isTypeLegal(Type *Ty, MVT &VT);
170 bool isTypeSupported(Type *Ty, MVT &VT);
171 bool isLoadTypeLegal(Type *Ty, MVT &VT);
172 bool computeAddress(const Value *Obj, Address &Addr);
173 bool computeCallAddress(const Value *V, Address &Addr);
174 void simplifyAddress(Address &Addr);
176 // Emit helper routines.
177 bool emitCmp(unsigned DestReg, const CmpInst *CI);
178 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
179 unsigned Alignment = 0);
180 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
181 MachineMemOperand *MMO = nullptr);
182 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
183 unsigned Alignment = 0);
184 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
185 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
188 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
191 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
193 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
198 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
201 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
202 unsigned materializeGV(const GlobalValue *GV, MVT VT);
203 unsigned materializeInt(const Constant *C, MVT VT);
204 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
205 unsigned materializeExternalCallSym(MCSymbol *Syn);
207 MachineInstrBuilder emitInst(unsigned Opc) {
208 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
211 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
212 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
216 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
217 unsigned MemReg, int64_t MemOffset) {
218 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
221 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
222 unsigned MemReg, int64_t MemOffset) {
223 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
226 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
227 const TargetRegisterClass *RC,
228 unsigned Op0, bool Op0IsKill,
229 unsigned Op1, bool Op1IsKill);
231 // for some reason, this default is not generated by tablegen
232 // so we explicitly generate it here.
233 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
234 unsigned Op0, bool Op0IsKill, uint64_t imm1,
235 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
239 // Call handling routines.
241 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
242 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
244 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
246 const MipsABIInfo &getABI() const {
247 return static_cast<const MipsTargetMachine &>(TM).getABI();
251 // Backend specific FastISel code.
252 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
253 const TargetLibraryInfo *libInfo)
254 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
255 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
256 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
257 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
258 Context = &funcInfo.Fn->getContext();
259 UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
262 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
263 unsigned fastMaterializeConstant(const Constant *C) override;
264 bool fastSelectInstruction(const Instruction *I) override;
266 #include "MipsGenFastISel.inc"
269 } // end anonymous namespace
271 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
272 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
273 CCState &State) LLVM_ATTRIBUTE_UNUSED;
275 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
276 CCValAssign::LocInfo LocInfo,
277 ISD::ArgFlagsTy ArgFlags, CCState &State) {
278 llvm_unreachable("should not be called");
281 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
282 CCValAssign::LocInfo LocInfo,
283 ISD::ArgFlagsTy ArgFlags, CCState &State) {
284 llvm_unreachable("should not be called");
287 #include "MipsGenCallingConv.inc"
289 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
293 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
294 const Value *LHS, const Value *RHS) {
295 // Canonicalize immediates to the RHS first.
296 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
311 llvm_unreachable("unexpected opcode");
314 unsigned LHSReg = getRegForValue(LHS);
319 if (const auto *C = dyn_cast<ConstantInt>(RHS))
320 RHSReg = materializeInt(C, MVT::i32);
322 RHSReg = getRegForValue(RHS);
326 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
330 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
334 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
335 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
336 "Alloca should always return a pointer.");
338 DenseMap<const AllocaInst *, int>::iterator SI =
339 FuncInfo.StaticAllocaMap.find(AI);
341 if (SI != FuncInfo.StaticAllocaMap.end()) {
342 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
343 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
345 .addFrameIndex(SI->second)
353 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
354 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
356 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
357 const ConstantInt *CI = cast<ConstantInt>(C);
358 return materialize32BitInt(CI->getZExtValue(), RC);
361 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
362 const TargetRegisterClass *RC) {
363 unsigned ResultReg = createResultReg(RC);
365 if (isInt<16>(Imm)) {
366 unsigned Opc = Mips::ADDiu;
367 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
369 } else if (isUInt<16>(Imm)) {
370 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
373 unsigned Lo = Imm & 0xFFFF;
374 unsigned Hi = (Imm >> 16) & 0xFFFF;
376 // Both Lo and Hi have nonzero bits.
377 unsigned TmpReg = createResultReg(RC);
378 emitInst(Mips::LUi, TmpReg).addImm(Hi);
379 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
381 emitInst(Mips::LUi, ResultReg).addImm(Hi);
386 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
387 if (UnsupportedFPMode)
389 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
390 if (VT == MVT::f32) {
391 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
392 unsigned DestReg = createResultReg(RC);
393 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
394 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
396 } else if (VT == MVT::f64) {
397 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
398 unsigned DestReg = createResultReg(RC);
399 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
401 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
402 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
408 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
409 // For now 32-bit only.
412 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
413 unsigned DestReg = createResultReg(RC);
414 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
415 bool IsThreadLocal = GVar && GVar->isThreadLocal();
416 // TLS not supported at this time.
419 emitInst(Mips::LW, DestReg)
420 .addReg(MFI->getGlobalBaseReg())
421 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
422 if ((GV->hasInternalLinkage() ||
423 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
424 unsigned TempReg = createResultReg(RC);
425 emitInst(Mips::ADDiu, TempReg)
427 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
433 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
434 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
435 unsigned DestReg = createResultReg(RC);
436 emitInst(Mips::LW, DestReg)
437 .addReg(MFI->getGlobalBaseReg())
438 .addSym(Sym, MipsII::MO_GOT);
442 // Materialize a constant into a register, and return the register
443 // number (or zero if we failed to handle it).
444 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
445 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
447 // Only handle simple types.
448 if (!CEVT.isSimple())
450 MVT VT = CEVT.getSimpleVT();
452 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
453 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
454 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
455 return materializeGV(GV, VT);
456 else if (isa<ConstantInt>(C))
457 return materializeInt(C, VT);
462 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
463 const User *U = nullptr;
464 unsigned Opcode = Instruction::UserOp1;
465 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
466 // Don't walk into other basic blocks unless the object is an alloca from
467 // another block, otherwise it may not have a virtual register assigned.
468 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
469 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
470 Opcode = I->getOpcode();
473 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
474 Opcode = C->getOpcode();
480 case Instruction::BitCast:
481 // Look through bitcasts.
482 return computeAddress(U->getOperand(0), Addr);
483 case Instruction::GetElementPtr: {
484 Address SavedAddr = Addr;
485 int64_t TmpOffset = Addr.getOffset();
486 // Iterate through the GEP folding the constants into offsets where
488 gep_type_iterator GTI = gep_type_begin(U);
489 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
491 const Value *Op = *i;
492 if (StructType *STy = GTI.getStructTypeOrNull()) {
493 const StructLayout *SL = DL.getStructLayout(STy);
494 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
495 TmpOffset += SL->getElementOffset(Idx);
497 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
499 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
500 // Constant-offset addressing.
501 TmpOffset += CI->getSExtValue() * S;
504 if (canFoldAddIntoGEP(U, Op)) {
505 // A compatible add with a constant operand. Fold the constant.
507 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
508 TmpOffset += CI->getSExtValue() * S;
509 // Iterate on the other operand.
510 Op = cast<AddOperator>(Op)->getOperand(0);
514 goto unsupported_gep;
518 // Try to grab the base operand now.
519 Addr.setOffset(TmpOffset);
520 if (computeAddress(U->getOperand(0), Addr))
522 // We failed, restore everything and try the other options.
527 case Instruction::Alloca: {
528 const AllocaInst *AI = cast<AllocaInst>(Obj);
529 DenseMap<const AllocaInst *, int>::iterator SI =
530 FuncInfo.StaticAllocaMap.find(AI);
531 if (SI != FuncInfo.StaticAllocaMap.end()) {
532 Addr.setKind(Address::FrameIndexBase);
533 Addr.setFI(SI->second);
539 Addr.setReg(getRegForValue(Obj));
540 return Addr.getReg() != 0;
543 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
544 const User *U = nullptr;
545 unsigned Opcode = Instruction::UserOp1;
547 if (const auto *I = dyn_cast<Instruction>(V)) {
548 // Check if the value is defined in the same basic block. This information
549 // is crucial to know whether or not folding an operand is valid.
550 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
551 Opcode = I->getOpcode();
554 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
555 Opcode = C->getOpcode();
562 case Instruction::BitCast:
563 // Look past bitcasts if its operand is in the same BB.
564 return computeCallAddress(U->getOperand(0), Addr);
566 case Instruction::IntToPtr:
567 // Look past no-op inttoptrs if its operand is in the same BB.
568 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
569 TLI.getPointerTy(DL))
570 return computeCallAddress(U->getOperand(0), Addr);
572 case Instruction::PtrToInt:
573 // Look past no-op ptrtoints if its operand is in the same BB.
574 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
575 return computeCallAddress(U->getOperand(0), Addr);
579 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
580 Addr.setGlobalValue(GV);
584 // If all else fails, try to materialize the value in a register.
585 if (!Addr.getGlobalValue()) {
586 Addr.setReg(getRegForValue(V));
587 return Addr.getReg() != 0;
593 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
594 EVT evt = TLI.getValueType(DL, Ty, true);
595 // Only handle simple types.
596 if (evt == MVT::Other || !evt.isSimple())
598 VT = evt.getSimpleVT();
600 // Handle all legal types, i.e. a register that will directly hold this
602 return TLI.isTypeLegal(VT);
605 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
606 if (Ty->isVectorTy())
609 if (isTypeLegal(Ty, VT))
612 // If this is a type than can be sign or zero-extended to a basic operation
613 // go ahead and accept it now.
614 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
620 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
621 if (isTypeLegal(Ty, VT))
623 // We will extend this in a later patch:
624 // If this is a type than can be sign or zero-extended to a basic operation
625 // go ahead and accept it now.
626 if (VT == MVT::i8 || VT == MVT::i16)
631 // Because of how EmitCmp is called with fast-isel, you can
632 // end up with redundant "andi" instructions after the sequences emitted below.
633 // We should try and solve this issue in the future.
635 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
636 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
637 bool IsUnsigned = CI->isUnsigned();
638 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
641 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
644 CmpInst::Predicate P = CI->getPredicate();
649 case CmpInst::ICMP_EQ: {
650 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
651 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
652 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
655 case CmpInst::ICMP_NE: {
656 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
657 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
658 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
661 case CmpInst::ICMP_UGT:
662 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
664 case CmpInst::ICMP_ULT:
665 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
667 case CmpInst::ICMP_UGE: {
668 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
669 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
670 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
673 case CmpInst::ICMP_ULE: {
674 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
675 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
676 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
679 case CmpInst::ICMP_SGT:
680 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
682 case CmpInst::ICMP_SLT:
683 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
685 case CmpInst::ICMP_SGE: {
686 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
687 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
688 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
691 case CmpInst::ICMP_SLE: {
692 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
693 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
694 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
697 case CmpInst::FCMP_OEQ:
698 case CmpInst::FCMP_UNE:
699 case CmpInst::FCMP_OLT:
700 case CmpInst::FCMP_OLE:
701 case CmpInst::FCMP_OGT:
702 case CmpInst::FCMP_OGE: {
703 if (UnsupportedFPMode)
705 bool IsFloat = Left->getType()->isFloatTy();
706 bool IsDouble = Left->getType()->isDoubleTy();
707 if (!IsFloat && !IsDouble)
709 unsigned Opc, CondMovOpc;
711 case CmpInst::FCMP_OEQ:
712 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
713 CondMovOpc = Mips::MOVT_I;
715 case CmpInst::FCMP_UNE:
716 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
717 CondMovOpc = Mips::MOVF_I;
719 case CmpInst::FCMP_OLT:
720 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
721 CondMovOpc = Mips::MOVT_I;
723 case CmpInst::FCMP_OLE:
724 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
725 CondMovOpc = Mips::MOVT_I;
727 case CmpInst::FCMP_OGT:
728 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
729 CondMovOpc = Mips::MOVF_I;
731 case CmpInst::FCMP_OGE:
732 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
733 CondMovOpc = Mips::MOVF_I;
736 llvm_unreachable("Only switching of a subset of CCs.");
738 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
739 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
740 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
741 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
742 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
744 emitInst(CondMovOpc, ResultReg)
747 .addReg(RegWithZero);
754 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
755 unsigned Alignment) {
757 // more cases will be handled here in following patches.
760 switch (VT.SimpleTy) {
762 ResultReg = createResultReg(&Mips::GPR32RegClass);
766 ResultReg = createResultReg(&Mips::GPR32RegClass);
770 ResultReg = createResultReg(&Mips::GPR32RegClass);
774 if (UnsupportedFPMode)
776 ResultReg = createResultReg(&Mips::FGR32RegClass);
780 if (UnsupportedFPMode)
782 ResultReg = createResultReg(&Mips::AFGR64RegClass);
788 if (Addr.isRegBase()) {
789 simplifyAddress(Addr);
790 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
793 if (Addr.isFIBase()) {
794 unsigned FI = Addr.getFI();
796 int64_t Offset = Addr.getOffset();
797 MachineFrameInfo &MFI = MF->getFrameInfo();
798 MachineMemOperand *MMO = MF->getMachineMemOperand(
799 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
800 MFI.getObjectSize(FI), Align);
801 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
810 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
811 unsigned Alignment) {
813 // more cases will be handled here in following patches.
816 switch (VT.SimpleTy) {
827 if (UnsupportedFPMode)
832 if (UnsupportedFPMode)
839 if (Addr.isRegBase()) {
840 simplifyAddress(Addr);
841 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
844 if (Addr.isFIBase()) {
845 unsigned FI = Addr.getFI();
847 int64_t Offset = Addr.getOffset();
848 MachineFrameInfo &MFI = MF->getFrameInfo();
849 MachineMemOperand *MMO = MF->getMachineMemOperand(
850 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
851 MFI.getObjectSize(FI), Align);
852 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
862 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
864 if (!isTypeSupported(I->getType(), VT))
868 switch (I->getOpcode()) {
870 llvm_unreachable("Unexpected instruction.");
871 case Instruction::And:
872 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
874 case Instruction::Or:
875 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
877 case Instruction::Xor:
878 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
885 updateValueMap(I, ResultReg);
889 bool MipsFastISel::selectLoad(const Instruction *I) {
890 // Atomic loads need special handling.
891 if (cast<LoadInst>(I)->isAtomic())
894 // Verify we have a legal type before going any further.
896 if (!isLoadTypeLegal(I->getType(), VT))
899 // See if we can handle this address.
901 if (!computeAddress(I->getOperand(0), Addr))
905 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
907 updateValueMap(I, ResultReg);
911 bool MipsFastISel::selectStore(const Instruction *I) {
912 Value *Op0 = I->getOperand(0);
915 // Atomic stores need special handling.
916 if (cast<StoreInst>(I)->isAtomic())
919 // Verify we have a legal type before going any further.
921 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
924 // Get the value to be stored into a register.
925 SrcReg = getRegForValue(Op0);
929 // See if we can handle this address.
931 if (!computeAddress(I->getOperand(1), Addr))
934 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
939 // This can cause a redundant sltiu to be generated.
940 // FIXME: try and eliminate this in a future patch.
941 bool MipsFastISel::selectBranch(const Instruction *I) {
942 const BranchInst *BI = cast<BranchInst>(I);
943 MachineBasicBlock *BrBB = FuncInfo.MBB;
945 // TBB is the basic block for the case where the comparison is true.
946 // FBB is the basic block for the case where the comparison is false.
947 // if (cond) goto TBB
951 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
952 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
954 // For now, just try the simplest case where it's fed by a compare.
955 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
956 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
957 if (!emitCmp(CondReg, CI))
959 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
962 finishCondBranch(BI->getParent(), TBB, FBB);
968 bool MipsFastISel::selectCmp(const Instruction *I) {
969 const CmpInst *CI = cast<CmpInst>(I);
970 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
971 if (!emitCmp(ResultReg, CI))
973 updateValueMap(I, ResultReg);
977 // Attempt to fast-select a floating-point extend instruction.
978 bool MipsFastISel::selectFPExt(const Instruction *I) {
979 if (UnsupportedFPMode)
981 Value *Src = I->getOperand(0);
982 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
983 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
985 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
989 getRegForValue(Src); // this must be a 32bit floating point register class
990 // maybe we should handle this differently
994 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
995 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
996 updateValueMap(I, DestReg);
1000 bool MipsFastISel::selectSelect(const Instruction *I) {
1001 assert(isa<SelectInst>(I) && "Expected a select instruction.");
1003 DEBUG(dbgs() << "selectSelect\n");
1006 if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1007 DEBUG(dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1011 unsigned CondMovOpc;
1012 const TargetRegisterClass *RC;
1014 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1015 CondMovOpc = Mips::MOVN_I_I;
1016 RC = &Mips::GPR32RegClass;
1017 } else if (VT == MVT::f32) {
1018 CondMovOpc = Mips::MOVN_I_S;
1019 RC = &Mips::FGR32RegClass;
1020 } else if (VT == MVT::f64) {
1021 CondMovOpc = Mips::MOVN_I_D32;
1022 RC = &Mips::AFGR64RegClass;
1026 const SelectInst *SI = cast<SelectInst>(I);
1027 const Value *Cond = SI->getCondition();
1028 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1029 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1030 unsigned CondReg = getRegForValue(Cond);
1032 if (!Src1Reg || !Src2Reg || !CondReg)
1035 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1039 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1042 unsigned ResultReg = createResultReg(RC);
1043 unsigned TempReg = createResultReg(RC);
1045 if (!ResultReg || !TempReg)
1048 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1049 emitInst(CondMovOpc, ResultReg)
1050 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1051 updateValueMap(I, ResultReg);
1055 // Attempt to fast-select a floating-point truncate instruction.
1056 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1057 if (UnsupportedFPMode)
1059 Value *Src = I->getOperand(0);
1060 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1061 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1063 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1066 unsigned SrcReg = getRegForValue(Src);
1070 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1074 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1075 updateValueMap(I, DestReg);
1079 // Attempt to fast-select a floating-point-to-integer conversion.
1080 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1081 if (UnsupportedFPMode)
1085 return false; // We don't handle this case yet. There is no native
1086 // instruction for this but it can be synthesized.
1087 Type *DstTy = I->getType();
1088 if (!isTypeLegal(DstTy, DstVT))
1091 if (DstVT != MVT::i32)
1094 Value *Src = I->getOperand(0);
1095 Type *SrcTy = Src->getType();
1096 if (!isTypeLegal(SrcTy, SrcVT))
1099 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1102 unsigned SrcReg = getRegForValue(Src);
1106 // Determine the opcode for the conversion, which takes place
1107 // entirely within FPRs.
1108 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1109 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1110 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1112 // Generate the convert.
1113 emitInst(Opc, TempReg).addReg(SrcReg);
1114 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1116 updateValueMap(I, DestReg);
1120 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1121 SmallVectorImpl<MVT> &OutVTs,
1122 unsigned &NumBytes) {
1123 CallingConv::ID CC = CLI.CallConv;
1124 SmallVector<CCValAssign, 16> ArgLocs;
1125 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1126 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1127 // Get a count of how many bytes are to be pushed on the stack.
1128 NumBytes = CCInfo.getNextStackOffset();
1129 // This is the minimum argument area used for A0-A3.
1133 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1134 // Process the args.
1136 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1137 CCValAssign &VA = ArgLocs[i];
1138 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1139 MVT ArgVT = OutVTs[VA.getValNo()];
1143 if (ArgVT == MVT::f32) {
1144 VA.convertToReg(Mips::F12);
1145 } else if (ArgVT == MVT::f64) {
1146 VA.convertToReg(Mips::D6);
1148 } else if (i == 1) {
1149 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1150 if (ArgVT == MVT::f32) {
1151 VA.convertToReg(Mips::F14);
1152 } else if (ArgVT == MVT::f64) {
1153 VA.convertToReg(Mips::D7);
1157 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1158 (ArgVT == MVT::i8)) &&
1160 switch (VA.getLocMemOffset()) {
1162 VA.convertToReg(Mips::A0);
1165 VA.convertToReg(Mips::A1);
1168 VA.convertToReg(Mips::A2);
1171 VA.convertToReg(Mips::A3);
1177 unsigned ArgReg = getRegForValue(ArgVal);
1181 // Handle arg promotion: SExt, ZExt, AExt.
1182 switch (VA.getLocInfo()) {
1183 case CCValAssign::Full:
1185 case CCValAssign::AExt:
1186 case CCValAssign::SExt: {
1187 MVT DestVT = VA.getLocVT();
1189 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1194 case CCValAssign::ZExt: {
1195 MVT DestVT = VA.getLocVT();
1197 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1203 llvm_unreachable("Unknown arg promotion!");
1206 // Now copy/store arg to correct locations.
1207 if (VA.isRegLoc() && !VA.needsCustom()) {
1208 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1209 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1210 CLI.OutRegs.push_back(VA.getLocReg());
1211 } else if (VA.needsCustom()) {
1212 llvm_unreachable("Mips does not use custom args.");
1216 // FIXME: This path will currently return false. It was copied
1217 // from the AArch64 port and should be essentially fine for Mips too.
1218 // The work to finish up this path will be done in a follow-on patch.
1220 assert(VA.isMemLoc() && "Assuming store on stack.");
1221 // Don't emit stores for undef values.
1222 if (isa<UndefValue>(ArgVal))
1225 // Need to store on the stack.
1226 // FIXME: This alignment is incorrect but this path is disabled
1227 // for now (will return false). We need to determine the right alignment
1228 // based on the normal alignment for the underlying machine type.
1230 unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1232 unsigned BEAlign = 0;
1233 if (ArgSize < 8 && !Subtarget->isLittle())
1234 BEAlign = 8 - ArgSize;
1237 Addr.setKind(Address::RegBase);
1238 Addr.setReg(Mips::SP);
1239 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1241 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1242 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1243 MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1244 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1246 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1247 return false; // can't store on the stack yet.
1254 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1255 unsigned NumBytes) {
1256 CallingConv::ID CC = CLI.CallConv;
1257 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1258 if (RetVT != MVT::isVoid) {
1259 SmallVector<CCValAssign, 16> RVLocs;
1260 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1262 CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1263 CLI.Symbol ? CLI.Symbol->getName().data()
1266 // Only handle a single return value.
1267 if (RVLocs.size() != 1)
1269 // Copy all of the result registers out of their specified physreg.
1270 MVT CopyVT = RVLocs[0].getValVT();
1271 // Special handling for extended integers.
1272 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1275 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1279 TII.get(TargetOpcode::COPY),
1280 ResultReg).addReg(RVLocs[0].getLocReg());
1281 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1283 CLI.ResultReg = ResultReg;
1284 CLI.NumResultRegs = 1;
1289 bool MipsFastISel::fastLowerArguments() {
1290 DEBUG(dbgs() << "fastLowerArguments\n");
1292 if (!FuncInfo.CanLowerReturn) {
1293 DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1297 const Function *F = FuncInfo.Fn;
1298 if (F->isVarArg()) {
1299 DEBUG(dbgs() << ".. gave up (varargs)\n");
1303 CallingConv::ID CC = F->getCallingConv();
1304 if (CC != CallingConv::C) {
1305 DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1309 const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
1311 const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};
1312 const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};
1313 ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();
1314 ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();
1315 ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();
1317 struct AllocatedReg {
1318 const TargetRegisterClass *RC;
1320 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1321 : RC(RC), Reg(Reg) {}
1324 // Only handle simple cases. i.e. All arguments are directly mapped to
1325 // registers of the appropriate type.
1326 SmallVector<AllocatedReg, 4> Allocation;
1327 for (const auto &FormalArg : F->args()) {
1328 if (FormalArg.hasAttribute(Attribute::InReg) ||
1329 FormalArg.hasAttribute(Attribute::StructRet) ||
1330 FormalArg.hasAttribute(Attribute::ByVal)) {
1331 DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1335 Type *ArgTy = FormalArg.getType();
1336 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1337 DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1341 EVT ArgVT = TLI.getValueType(DL, ArgTy);
1342 DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1343 << ArgVT.getEVTString() << "\n");
1344 if (!ArgVT.isSimple()) {
1345 DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1349 switch (ArgVT.getSimpleVT().SimpleTy) {
1353 if (!FormalArg.hasAttribute(Attribute::SExt) &&
1354 !FormalArg.hasAttribute(Attribute::ZExt)) {
1355 // It must be any extend, this shouldn't happen for clang-generated IR
1356 // so just fall back on SelectionDAG.
1357 DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1361 if (NextGPR32 == GPR32ArgRegs.end()) {
1362 DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1366 DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1367 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1369 // Allocating any GPR32 prohibits further use of floating point arguments.
1370 NextFGR32 = FGR32ArgRegs.end();
1371 NextAFGR64 = AFGR64ArgRegs.end();
1375 if (FormalArg.hasAttribute(Attribute::ZExt)) {
1376 // The O32 ABI does not permit a zero-extended i32.
1377 DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1381 if (NextGPR32 == GPR32ArgRegs.end()) {
1382 DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1386 DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1387 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1389 // Allocating any GPR32 prohibits further use of floating point arguments.
1390 NextFGR32 = FGR32ArgRegs.end();
1391 NextAFGR64 = AFGR64ArgRegs.end();
1395 if (UnsupportedFPMode) {
1396 DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1399 if (NextFGR32 == FGR32ArgRegs.end()) {
1400 DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1403 DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1404 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1405 // Allocating an FGR32 also allocates the super-register AFGR64, and
1406 // ABI rules require us to skip the corresponding GPR32.
1407 if (NextGPR32 != GPR32ArgRegs.end())
1409 if (NextAFGR64 != AFGR64ArgRegs.end())
1414 if (UnsupportedFPMode) {
1415 DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1418 if (NextAFGR64 == AFGR64ArgRegs.end()) {
1419 DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1422 DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1423 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1424 // Allocating an FGR32 also allocates the super-register AFGR64, and
1425 // ABI rules require us to skip the corresponding GPR32 pair.
1426 if (NextGPR32 != GPR32ArgRegs.end())
1428 if (NextGPR32 != GPR32ArgRegs.end())
1430 if (NextFGR32 != FGR32ArgRegs.end())
1435 DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1440 for (const auto &FormalArg : F->args()) {
1441 unsigned ArgNo = FormalArg.getArgNo();
1442 unsigned SrcReg = Allocation[ArgNo].Reg;
1443 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1444 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1445 // Without this, EmitLiveInCopies may eliminate the livein if its only
1446 // use is a bitcast (which isn't turned into an instruction).
1447 unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1448 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1449 TII.get(TargetOpcode::COPY), ResultReg)
1450 .addReg(DstReg, getKillRegState(true));
1451 updateValueMap(&FormalArg, ResultReg);
1454 // Calculate the size of the incoming arguments area.
1455 // We currently reject all the cases where this would be non-zero.
1456 unsigned IncomingArgSizeInBytes = 0;
1458 // Account for the reserved argument area on ABI's that have one (O32).
1459 // It seems strange to do this on the caller side but it's necessary in
1460 // SelectionDAG's implementation.
1461 IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1462 IncomingArgSizeInBytes);
1464 MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1470 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1471 CallingConv::ID CC = CLI.CallConv;
1472 bool IsTailCall = CLI.IsTailCall;
1473 bool IsVarArg = CLI.IsVarArg;
1474 const Value *Callee = CLI.Callee;
1475 MCSymbol *Symbol = CLI.Symbol;
1477 // Do not handle FastCC.
1478 if (CC == CallingConv::Fast)
1481 // Allow SelectionDAG isel to handle tail calls.
1485 // Let SDISel handle vararg functions.
1489 // FIXME: Only handle *simple* calls for now.
1491 if (CLI.RetTy->isVoidTy())
1492 RetVT = MVT::isVoid;
1493 else if (!isTypeSupported(CLI.RetTy, RetVT))
1496 for (auto Flag : CLI.OutFlags)
1497 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1500 // Set up the argument vectors.
1501 SmallVector<MVT, 16> OutVTs;
1502 OutVTs.reserve(CLI.OutVals.size());
1504 for (auto *Val : CLI.OutVals) {
1506 if (!isTypeLegal(Val->getType(), VT) &&
1507 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1510 // We don't handle vector parameters yet.
1511 if (VT.isVector() || VT.getSizeInBits() > 64)
1514 OutVTs.push_back(VT);
1518 if (!computeCallAddress(Callee, Addr))
1521 // Handle the arguments now that we've gotten them.
1523 if (!processCallArgs(CLI, OutVTs, NumBytes))
1526 if (!Addr.getGlobalValue())
1530 unsigned DestAddress;
1532 DestAddress = materializeExternalCallSym(Symbol);
1534 DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1535 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1536 MachineInstrBuilder MIB =
1537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1538 Mips::RA).addReg(Mips::T9);
1540 // Add implicit physical register uses to the call.
1541 for (auto Reg : CLI.OutRegs)
1542 MIB.addReg(Reg, RegState::Implicit);
1544 // Add a register mask with the call-preserved registers.
1545 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1546 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1550 // Finish off the call including any return values.
1551 return finishCall(CLI, RetVT, NumBytes);
1554 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1555 switch (II->getIntrinsicID()) {
1558 case Intrinsic::bswap: {
1559 Type *RetTy = II->getCalledFunction()->getReturnType();
1562 if (!isTypeSupported(RetTy, VT))
1565 unsigned SrcReg = getRegForValue(II->getOperand(0));
1568 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1571 if (VT == MVT::i16) {
1572 if (Subtarget->hasMips32r2()) {
1573 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1574 updateValueMap(II, DestReg);
1577 unsigned TempReg[3];
1578 for (int i = 0; i < 3; i++) {
1579 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1580 if (TempReg[i] == 0)
1583 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1584 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1585 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1586 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1587 updateValueMap(II, DestReg);
1590 } else if (VT == MVT::i32) {
1591 if (Subtarget->hasMips32r2()) {
1592 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1593 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1594 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1595 updateValueMap(II, DestReg);
1598 unsigned TempReg[8];
1599 for (int i = 0; i < 8; i++) {
1600 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1601 if (TempReg[i] == 0)
1605 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1606 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1607 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1608 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1610 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1611 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1613 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1614 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1615 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1616 updateValueMap(II, DestReg);
1622 case Intrinsic::memcpy:
1623 case Intrinsic::memmove: {
1624 const auto *MTI = cast<MemTransferInst>(II);
1625 // Don't handle volatile.
1626 if (MTI->isVolatile())
1628 if (!MTI->getLength()->getType()->isIntegerTy(32))
1630 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1631 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1633 case Intrinsic::memset: {
1634 const MemSetInst *MSI = cast<MemSetInst>(II);
1635 // Don't handle volatile.
1636 if (MSI->isVolatile())
1638 if (!MSI->getLength()->getType()->isIntegerTy(32))
1640 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1646 bool MipsFastISel::selectRet(const Instruction *I) {
1647 const Function &F = *I->getParent()->getParent();
1648 const ReturnInst *Ret = cast<ReturnInst>(I);
1650 DEBUG(dbgs() << "selectRet\n");
1652 if (!FuncInfo.CanLowerReturn)
1655 // Build a list of return value registers.
1656 SmallVector<unsigned, 4> RetRegs;
1658 if (Ret->getNumOperands() > 0) {
1659 CallingConv::ID CC = F.getCallingConv();
1661 // Do not handle FastCC.
1662 if (CC == CallingConv::Fast)
1665 SmallVector<ISD::OutputArg, 4> Outs;
1666 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1668 // Analyze operands of the call, assigning locations to each operand.
1669 SmallVector<CCValAssign, 16> ValLocs;
1670 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1672 CCAssignFn *RetCC = RetCC_Mips;
1673 CCInfo.AnalyzeReturn(Outs, RetCC);
1675 // Only handle a single return value for now.
1676 if (ValLocs.size() != 1)
1679 CCValAssign &VA = ValLocs[0];
1680 const Value *RV = Ret->getOperand(0);
1682 // Don't bother handling odd stuff for now.
1683 if ((VA.getLocInfo() != CCValAssign::Full) &&
1684 (VA.getLocInfo() != CCValAssign::BCvt))
1687 // Only handle register returns for now.
1691 unsigned Reg = getRegForValue(RV);
1695 unsigned SrcReg = Reg + VA.getValNo();
1696 unsigned DestReg = VA.getLocReg();
1697 // Avoid a cross-class copy. This is very unlikely.
1698 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1701 EVT RVEVT = TLI.getValueType(DL, RV->getType());
1702 if (!RVEVT.isSimple())
1705 if (RVEVT.isVector())
1708 MVT RVVT = RVEVT.getSimpleVT();
1709 if (RVVT == MVT::f128)
1712 // Do not handle FGR64 returns for now.
1713 if (RVVT == MVT::f64 && UnsupportedFPMode) {
1714 DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1718 MVT DestVT = VA.getValVT();
1719 // Special handling for extended integers.
1720 if (RVVT != DestVT) {
1721 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1724 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1725 bool IsZExt = Outs[0].Flags.isZExt();
1726 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1733 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1734 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1736 // Add register to return instruction.
1737 RetRegs.push_back(VA.getLocReg());
1739 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1740 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1741 MIB.addReg(RetRegs[i], RegState::Implicit);
1745 bool MipsFastISel::selectTrunc(const Instruction *I) {
1746 // The high bits for a type smaller than the register size are assumed to be
1748 Value *Op = I->getOperand(0);
1751 SrcVT = TLI.getValueType(DL, Op->getType(), true);
1752 DestVT = TLI.getValueType(DL, I->getType(), true);
1754 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1756 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1759 unsigned SrcReg = getRegForValue(Op);
1763 // Because the high bits are undefined, a truncate doesn't generate
1765 updateValueMap(I, SrcReg);
1769 bool MipsFastISel::selectIntExt(const Instruction *I) {
1770 Type *DestTy = I->getType();
1771 Value *Src = I->getOperand(0);
1772 Type *SrcTy = Src->getType();
1774 bool isZExt = isa<ZExtInst>(I);
1775 unsigned SrcReg = getRegForValue(Src);
1779 EVT SrcEVT, DestEVT;
1780 SrcEVT = TLI.getValueType(DL, SrcTy, true);
1781 DestEVT = TLI.getValueType(DL, DestTy, true);
1782 if (!SrcEVT.isSimple())
1784 if (!DestEVT.isSimple())
1787 MVT SrcVT = SrcEVT.getSimpleVT();
1788 MVT DestVT = DestEVT.getSimpleVT();
1789 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1791 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1793 updateValueMap(I, ResultReg);
1797 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1800 switch (SrcVT.SimpleTy) {
1810 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1811 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1812 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1816 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1818 switch (SrcVT.SimpleTy) {
1822 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1825 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1831 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1833 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1835 if (Subtarget->hasMips32r2())
1836 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1837 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1840 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1844 switch (SrcVT.SimpleTy) {
1858 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1862 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1863 unsigned DestReg, bool IsZExt) {
1864 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1865 // DestVT are odd things, so test to make sure that they are both types we can
1866 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1867 // bail out to SelectionDAG.
1868 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1869 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1872 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1873 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1876 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1878 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1879 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1880 return Success ? DestReg : 0;
1883 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1884 EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1885 if (!DestEVT.isSimple())
1888 MVT DestVT = DestEVT.getSimpleVT();
1889 if (DestVT != MVT::i32)
1893 switch (ISDOpcode) {
1898 DivOpc = Mips::SDIV;
1902 DivOpc = Mips::UDIV;
1906 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1907 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1908 if (!Src0Reg || !Src1Reg)
1911 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1912 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1914 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1918 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1921 emitInst(MFOpc, ResultReg);
1923 updateValueMap(I, ResultReg);
1927 bool MipsFastISel::selectShift(const Instruction *I) {
1930 if (!isTypeSupported(I->getType(), RetVT))
1933 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1937 unsigned Opcode = I->getOpcode();
1938 const Value *Op0 = I->getOperand(0);
1939 unsigned Op0Reg = getRegForValue(Op0);
1943 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1944 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1945 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1949 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1950 bool IsZExt = Opcode == Instruction::LShr;
1951 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1957 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1958 uint64_t ShiftVal = C->getZExtValue();
1962 llvm_unreachable("Unexpected instruction.");
1963 case Instruction::Shl:
1966 case Instruction::AShr:
1969 case Instruction::LShr:
1974 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1975 updateValueMap(I, ResultReg);
1979 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1985 llvm_unreachable("Unexpected instruction.");
1986 case Instruction::Shl:
1987 Opcode = Mips::SLLV;
1989 case Instruction::AShr:
1990 Opcode = Mips::SRAV;
1992 case Instruction::LShr:
1993 Opcode = Mips::SRLV;
1997 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1998 updateValueMap(I, ResultReg);
2002 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2003 switch (I->getOpcode()) {
2006 case Instruction::Load:
2007 return selectLoad(I);
2008 case Instruction::Store:
2009 return selectStore(I);
2010 case Instruction::SDiv:
2011 if (!selectBinaryOp(I, ISD::SDIV))
2012 return selectDivRem(I, ISD::SDIV);
2014 case Instruction::UDiv:
2015 if (!selectBinaryOp(I, ISD::UDIV))
2016 return selectDivRem(I, ISD::UDIV);
2018 case Instruction::SRem:
2019 if (!selectBinaryOp(I, ISD::SREM))
2020 return selectDivRem(I, ISD::SREM);
2022 case Instruction::URem:
2023 if (!selectBinaryOp(I, ISD::UREM))
2024 return selectDivRem(I, ISD::UREM);
2026 case Instruction::Shl:
2027 case Instruction::LShr:
2028 case Instruction::AShr:
2029 return selectShift(I);
2030 case Instruction::And:
2031 case Instruction::Or:
2032 case Instruction::Xor:
2033 return selectLogicalOp(I);
2034 case Instruction::Br:
2035 return selectBranch(I);
2036 case Instruction::Ret:
2037 return selectRet(I);
2038 case Instruction::Trunc:
2039 return selectTrunc(I);
2040 case Instruction::ZExt:
2041 case Instruction::SExt:
2042 return selectIntExt(I);
2043 case Instruction::FPTrunc:
2044 return selectFPTrunc(I);
2045 case Instruction::FPExt:
2046 return selectFPExt(I);
2047 case Instruction::FPToSI:
2048 return selectFPToInt(I, /*isSigned*/ true);
2049 case Instruction::FPToUI:
2050 return selectFPToInt(I, /*isSigned*/ false);
2051 case Instruction::ICmp:
2052 case Instruction::FCmp:
2053 return selectCmp(I);
2054 case Instruction::Select:
2055 return selectSelect(I);
2060 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2062 unsigned VReg = getRegForValue(V);
2065 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2066 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2067 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2068 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2075 void MipsFastISel::simplifyAddress(Address &Addr) {
2076 if (!isInt<16>(Addr.getOffset())) {
2078 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2079 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2080 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2081 Addr.setReg(DestReg);
2086 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2087 const TargetRegisterClass *RC,
2088 unsigned Op0, bool Op0IsKill,
2089 unsigned Op1, bool Op1IsKill) {
2090 // We treat the MUL instruction in a special way because it clobbers
2091 // the HI0 & LO0 registers. The TableGen definition of this instruction can
2092 // mark these registers only as implicitly defined. As a result, the
2093 // register allocator runs out of registers when this instruction is
2094 // followed by another instruction that defines the same registers too.
2095 // We can fix this by explicitly marking those registers as dead.
2096 if (MachineInstOpcode == Mips::MUL) {
2097 unsigned ResultReg = createResultReg(RC);
2098 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2099 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2100 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2102 .addReg(Op0, getKillRegState(Op0IsKill))
2103 .addReg(Op1, getKillRegState(Op1IsKill))
2104 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2105 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2109 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2115 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2116 const TargetLibraryInfo *libInfo) {
2117 return new MipsFastISel(funcInfo, libInfo);
2120 } // end namespace llvm