1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #include "MipsISelLowering.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsTargetObjectFile.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 #define DEBUG_TYPE "mips-lower"
43 STATISTIC(NumTailCalls, "Number of tail calls");
46 LargeGOT("mxgot", cl::Hidden,
47 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
50 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
51 cl::desc("MIPS: Don't trap on integer division by zero."),
55 EnableMipsFastISel("mips-fast-isel", cl::Hidden,
56 cl::desc("Allow mips-fast-isel to be used"),
59 static const MCPhysReg O32IntRegs[4] = {
60 Mips::A0, Mips::A1, Mips::A2, Mips::A3
63 static const MCPhysReg Mips64IntRegs[8] = {
64 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
65 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
68 static const MCPhysReg Mips64DPRegs[8] = {
69 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
70 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
73 // If I is a shifted mask, set the size (Size) and the first bit of the
74 // mask (Pos), and return true.
75 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
76 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
77 if (!isShiftedMask_64(I))
80 Size = CountPopulation_64(I);
81 Pos = countTrailingZeros(I);
85 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
86 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
87 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
90 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
92 unsigned Flag) const {
93 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
96 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
98 unsigned Flag) const {
99 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
102 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
104 unsigned Flag) const {
105 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
108 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
110 unsigned Flag) const {
111 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
114 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
116 unsigned Flag) const {
117 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
118 N->getOffset(), Flag);
121 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
123 case MipsISD::JmpLink: return "MipsISD::JmpLink";
124 case MipsISD::TailCall: return "MipsISD::TailCall";
125 case MipsISD::Hi: return "MipsISD::Hi";
126 case MipsISD::Lo: return "MipsISD::Lo";
127 case MipsISD::GPRel: return "MipsISD::GPRel";
128 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
129 case MipsISD::Ret: return "MipsISD::Ret";
130 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
131 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
132 case MipsISD::FPCmp: return "MipsISD::FPCmp";
133 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
134 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
135 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
136 case MipsISD::MFHI: return "MipsISD::MFHI";
137 case MipsISD::MFLO: return "MipsISD::MFLO";
138 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
139 case MipsISD::Mult: return "MipsISD::Mult";
140 case MipsISD::Multu: return "MipsISD::Multu";
141 case MipsISD::MAdd: return "MipsISD::MAdd";
142 case MipsISD::MAddu: return "MipsISD::MAddu";
143 case MipsISD::MSub: return "MipsISD::MSub";
144 case MipsISD::MSubu: return "MipsISD::MSubu";
145 case MipsISD::DivRem: return "MipsISD::DivRem";
146 case MipsISD::DivRemU: return "MipsISD::DivRemU";
147 case MipsISD::DivRem16: return "MipsISD::DivRem16";
148 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
149 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
150 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
151 case MipsISD::Wrapper: return "MipsISD::Wrapper";
152 case MipsISD::Sync: return "MipsISD::Sync";
153 case MipsISD::Ext: return "MipsISD::Ext";
154 case MipsISD::Ins: return "MipsISD::Ins";
155 case MipsISD::LWL: return "MipsISD::LWL";
156 case MipsISD::LWR: return "MipsISD::LWR";
157 case MipsISD::SWL: return "MipsISD::SWL";
158 case MipsISD::SWR: return "MipsISD::SWR";
159 case MipsISD::LDL: return "MipsISD::LDL";
160 case MipsISD::LDR: return "MipsISD::LDR";
161 case MipsISD::SDL: return "MipsISD::SDL";
162 case MipsISD::SDR: return "MipsISD::SDR";
163 case MipsISD::EXTP: return "MipsISD::EXTP";
164 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
165 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
166 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
167 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
168 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
169 case MipsISD::SHILO: return "MipsISD::SHILO";
170 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
171 case MipsISD::MULT: return "MipsISD::MULT";
172 case MipsISD::MULTU: return "MipsISD::MULTU";
173 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
174 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
175 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
176 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
177 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
178 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
179 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
180 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
181 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
182 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
183 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
184 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
185 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
186 case MipsISD::VCEQ: return "MipsISD::VCEQ";
187 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
188 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
189 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
190 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
191 case MipsISD::VSMAX: return "MipsISD::VSMAX";
192 case MipsISD::VSMIN: return "MipsISD::VSMIN";
193 case MipsISD::VUMAX: return "MipsISD::VUMAX";
194 case MipsISD::VUMIN: return "MipsISD::VUMIN";
195 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
196 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
197 case MipsISD::VNOR: return "MipsISD::VNOR";
198 case MipsISD::VSHF: return "MipsISD::VSHF";
199 case MipsISD::SHF: return "MipsISD::SHF";
200 case MipsISD::ILVEV: return "MipsISD::ILVEV";
201 case MipsISD::ILVOD: return "MipsISD::ILVOD";
202 case MipsISD::ILVL: return "MipsISD::ILVL";
203 case MipsISD::ILVR: return "MipsISD::ILVR";
204 case MipsISD::PCKEV: return "MipsISD::PCKEV";
205 case MipsISD::PCKOD: return "MipsISD::PCKOD";
206 case MipsISD::INSVE: return "MipsISD::INSVE";
207 default: return nullptr;
211 MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
212 const MipsSubtarget &STI)
213 : TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) {
214 // Mips does not have i1 type, so use i32 for
215 // setcc operations results (slt, sgt, ...).
216 setBooleanContents(ZeroOrOneBooleanContent);
217 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
218 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
219 // does. Integer booleans still use 0 and 1.
220 if (Subtarget.hasMips32r6())
221 setBooleanContents(ZeroOrOneBooleanContent,
222 ZeroOrNegativeOneBooleanContent);
224 // Load extented operations for i1 types must be promoted
225 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
226 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
227 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
229 // MIPS doesn't have extending float->double load/store
230 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
231 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
233 // Used by legalize types to correctly generate the setcc result.
234 // Without this, every float setcc comes with a AND/OR with the result,
235 // we don't want this, since the fpcmp result goes to a flag register,
236 // which is used implicitly by brcond and select operations.
237 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
239 // Mips Custom Operations
240 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
241 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
242 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
244 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
245 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
246 setOperationAction(ISD::SELECT, MVT::f32, Custom);
247 setOperationAction(ISD::SELECT, MVT::f64, Custom);
248 setOperationAction(ISD::SELECT, MVT::i32, Custom);
249 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
251 setOperationAction(ISD::SETCC, MVT::f32, Custom);
252 setOperationAction(ISD::SETCC, MVT::f64, Custom);
253 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
254 setOperationAction(ISD::VASTART, MVT::Other, Custom);
255 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
257 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
259 if (Subtarget.isGP64bit()) {
260 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
261 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
262 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
263 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
264 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
265 setOperationAction(ISD::SELECT, MVT::i64, Custom);
266 setOperationAction(ISD::LOAD, MVT::i64, Custom);
267 setOperationAction(ISD::STORE, MVT::i64, Custom);
268 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
271 if (!Subtarget.isGP64bit()) {
272 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
273 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
274 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
277 setOperationAction(ISD::ADD, MVT::i32, Custom);
278 if (Subtarget.isGP64bit())
279 setOperationAction(ISD::ADD, MVT::i64, Custom);
281 setOperationAction(ISD::SDIV, MVT::i32, Expand);
282 setOperationAction(ISD::SREM, MVT::i32, Expand);
283 setOperationAction(ISD::UDIV, MVT::i32, Expand);
284 setOperationAction(ISD::UREM, MVT::i32, Expand);
285 setOperationAction(ISD::SDIV, MVT::i64, Expand);
286 setOperationAction(ISD::SREM, MVT::i64, Expand);
287 setOperationAction(ISD::UDIV, MVT::i64, Expand);
288 setOperationAction(ISD::UREM, MVT::i64, Expand);
290 // Operations not directly supported by Mips.
291 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
294 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
295 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
296 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
297 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
298 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
299 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
300 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
301 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
302 if (Subtarget.hasCnMips()) {
303 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
304 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
306 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
307 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
309 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
310 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
311 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
312 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
313 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
314 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
315 setOperationAction(ISD::ROTL, MVT::i32, Expand);
316 setOperationAction(ISD::ROTL, MVT::i64, Expand);
317 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
318 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
320 if (!Subtarget.hasMips32r2())
321 setOperationAction(ISD::ROTR, MVT::i32, Expand);
323 if (!Subtarget.hasMips64r2())
324 setOperationAction(ISD::ROTR, MVT::i64, Expand);
326 setOperationAction(ISD::FSIN, MVT::f32, Expand);
327 setOperationAction(ISD::FSIN, MVT::f64, Expand);
328 setOperationAction(ISD::FCOS, MVT::f32, Expand);
329 setOperationAction(ISD::FCOS, MVT::f64, Expand);
330 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
331 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
332 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
333 setOperationAction(ISD::FPOW, MVT::f32, Expand);
334 setOperationAction(ISD::FPOW, MVT::f64, Expand);
335 setOperationAction(ISD::FLOG, MVT::f32, Expand);
336 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
337 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
338 setOperationAction(ISD::FEXP, MVT::f32, Expand);
339 setOperationAction(ISD::FMA, MVT::f32, Expand);
340 setOperationAction(ISD::FMA, MVT::f64, Expand);
341 setOperationAction(ISD::FREM, MVT::f32, Expand);
342 setOperationAction(ISD::FREM, MVT::f64, Expand);
344 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
346 setOperationAction(ISD::VAARG, MVT::Other, Expand);
347 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
348 setOperationAction(ISD::VAEND, MVT::Other, Expand);
350 // Use the default for now
351 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
352 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
354 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
355 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
356 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
357 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
359 setInsertFencesForAtomic(true);
361 if (!Subtarget.hasMips32r2()) {
362 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
363 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
366 // MIPS16 lacks MIPS32's clz and clo instructions.
367 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
368 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
369 if (!Subtarget.hasMips64())
370 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
372 if (!Subtarget.hasMips32r2())
373 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
374 if (!Subtarget.hasMips64r2())
375 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
377 if (Subtarget.isGP64bit()) {
378 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
379 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
380 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
381 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
384 setOperationAction(ISD::TRAP, MVT::Other, Legal);
386 setTargetDAGCombine(ISD::SDIVREM);
387 setTargetDAGCombine(ISD::UDIVREM);
388 setTargetDAGCombine(ISD::SELECT);
389 setTargetDAGCombine(ISD::AND);
390 setTargetDAGCombine(ISD::OR);
391 setTargetDAGCombine(ISD::ADD);
393 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
395 setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64
398 setExceptionPointerRegister(Subtarget.isABI_N64() ? Mips::A0_64 : Mips::A0);
399 setExceptionSelectorRegister(Subtarget.isABI_N64() ? Mips::A1_64 : Mips::A1);
401 MaxStoresPerMemcpy = 16;
403 isMicroMips = Subtarget.inMicroMipsMode();
406 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM,
407 const MipsSubtarget &STI) {
408 if (STI.inMips16Mode())
409 return llvm::createMips16TargetLowering(TM, STI);
411 return llvm::createMipsSETargetLowering(TM, STI);
414 // Create a fast isel object.
416 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
417 const TargetLibraryInfo *libInfo) const {
418 if (!EnableMipsFastISel)
419 return TargetLowering::createFastISel(funcInfo, libInfo);
420 return Mips::createFastISel(funcInfo, libInfo);
423 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
426 return VT.changeVectorElementTypeToInteger();
429 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
430 TargetLowering::DAGCombinerInfo &DCI,
431 const MipsSubtarget &Subtarget) {
432 if (DCI.isBeforeLegalizeOps())
435 EVT Ty = N->getValueType(0);
436 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
437 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
438 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
442 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
443 N->getOperand(0), N->getOperand(1));
444 SDValue InChain = DAG.getEntryNode();
445 SDValue InGlue = DivRem;
448 if (N->hasAnyUseOfValue(0)) {
449 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
451 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
452 InChain = CopyFromLo.getValue(1);
453 InGlue = CopyFromLo.getValue(2);
457 if (N->hasAnyUseOfValue(1)) {
458 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
460 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
466 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
468 default: llvm_unreachable("Unknown fp condition code!");
470 case ISD::SETOEQ: return Mips::FCOND_OEQ;
471 case ISD::SETUNE: return Mips::FCOND_UNE;
473 case ISD::SETOLT: return Mips::FCOND_OLT;
475 case ISD::SETOGT: return Mips::FCOND_OGT;
477 case ISD::SETOLE: return Mips::FCOND_OLE;
479 case ISD::SETOGE: return Mips::FCOND_OGE;
480 case ISD::SETULT: return Mips::FCOND_ULT;
481 case ISD::SETULE: return Mips::FCOND_ULE;
482 case ISD::SETUGT: return Mips::FCOND_UGT;
483 case ISD::SETUGE: return Mips::FCOND_UGE;
484 case ISD::SETUO: return Mips::FCOND_UN;
485 case ISD::SETO: return Mips::FCOND_OR;
487 case ISD::SETONE: return Mips::FCOND_ONE;
488 case ISD::SETUEQ: return Mips::FCOND_UEQ;
493 /// This function returns true if the floating point conditional branches and
494 /// conditional moves which use condition code CC should be inverted.
495 static bool invertFPCondCodeUser(Mips::CondCode CC) {
496 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
499 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
500 "Illegal Condition Code");
505 // Creates and returns an FPCmp node from a setcc node.
506 // Returns Op if setcc is not a floating point comparison.
507 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
508 // must be a SETCC node
509 if (Op.getOpcode() != ISD::SETCC)
512 SDValue LHS = Op.getOperand(0);
514 if (!LHS.getValueType().isFloatingPoint())
517 SDValue RHS = Op.getOperand(1);
520 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
521 // node if necessary.
522 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
524 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
525 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
528 // Creates and returns a CMovFPT/F node.
529 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
530 SDValue False, SDLoc DL) {
531 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
532 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
533 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
535 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
536 True.getValueType(), True, FCC0, False, Cond);
539 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
540 TargetLowering::DAGCombinerInfo &DCI,
541 const MipsSubtarget &Subtarget) {
542 if (DCI.isBeforeLegalizeOps())
545 SDValue SetCC = N->getOperand(0);
547 if ((SetCC.getOpcode() != ISD::SETCC) ||
548 !SetCC.getOperand(0).getValueType().isInteger())
551 SDValue False = N->getOperand(2);
552 EVT FalseTy = False.getValueType();
554 if (!FalseTy.isInteger())
557 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
559 // If the RHS (False) is 0, we swap the order of the operands
560 // of ISD::SELECT (obviously also inverting the condition) so that we can
561 // take advantage of conditional moves using the $0 register.
563 // return (a != 0) ? x : 0;
571 if (!FalseC->getZExtValue()) {
572 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
573 SDValue True = N->getOperand(1);
575 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
576 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
578 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
581 // If both operands are integer constants there's a possibility that we
582 // can do some interesting optimizations.
583 SDValue True = N->getOperand(1);
584 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
586 if (!TrueC || !True.getValueType().isInteger())
589 // We'll also ignore MVT::i64 operands as this optimizations proves
590 // to be ineffective because of the required sign extensions as the result
591 // of a SETCC operator is always MVT::i32 for non-vector types.
592 if (True.getValueType() == MVT::i64)
595 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
597 // 1) (a < x) ? y : y-1
599 // addiu $reg2, $reg1, y-1
601 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
603 // 2) (a < x) ? y-1 : y
605 // xor $reg1, $reg1, 1
606 // addiu $reg2, $reg1, y-1
608 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
609 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
610 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
611 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
614 // Couldn't optimize.
618 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
619 TargetLowering::DAGCombinerInfo &DCI,
620 const MipsSubtarget &Subtarget) {
621 // Pattern match EXT.
622 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
623 // => ext $dst, $src, size, pos
624 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
627 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
628 unsigned ShiftRightOpc = ShiftRight.getOpcode();
630 // Op's first operand must be a shift right.
631 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
634 // The second operand of the shift must be an immediate.
636 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
639 uint64_t Pos = CN->getZExtValue();
640 uint64_t SMPos, SMSize;
642 // Op's second operand must be a shifted mask.
643 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
644 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
647 // Return if the shifted mask does not start at bit 0 or the sum of its size
648 // and Pos exceeds the word's size.
649 EVT ValTy = N->getValueType(0);
650 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
653 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
654 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
655 DAG.getConstant(SMSize, MVT::i32));
658 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
659 TargetLowering::DAGCombinerInfo &DCI,
660 const MipsSubtarget &Subtarget) {
661 // Pattern match INS.
662 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
663 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
664 // => ins $dst, $src, size, pos, $src1
665 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
668 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
669 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
672 // See if Op's first operand matches (and $src1 , mask0).
673 if (And0.getOpcode() != ISD::AND)
676 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
677 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
680 // See if Op's second operand matches (and (shl $src, pos), mask1).
681 if (And1.getOpcode() != ISD::AND)
684 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
685 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
688 // The shift masks must have the same position and size.
689 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
692 SDValue Shl = And1.getOperand(0);
693 if (Shl.getOpcode() != ISD::SHL)
696 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
699 unsigned Shamt = CN->getZExtValue();
701 // Return if the shift amount and the first bit position of mask are not the
703 EVT ValTy = N->getValueType(0);
704 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
707 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
708 DAG.getConstant(SMPos0, MVT::i32),
709 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
712 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
713 TargetLowering::DAGCombinerInfo &DCI,
714 const MipsSubtarget &Subtarget) {
715 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
717 if (DCI.isBeforeLegalizeOps())
720 SDValue Add = N->getOperand(1);
722 if (Add.getOpcode() != ISD::ADD)
725 SDValue Lo = Add.getOperand(1);
727 if ((Lo.getOpcode() != MipsISD::Lo) ||
728 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
731 EVT ValTy = N->getValueType(0);
734 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
736 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
739 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
741 SelectionDAG &DAG = DCI.DAG;
742 unsigned Opc = N->getOpcode();
748 return performDivRemCombine(N, DAG, DCI, Subtarget);
750 return performSELECTCombine(N, DAG, DCI, Subtarget);
752 return performANDCombine(N, DAG, DCI, Subtarget);
754 return performORCombine(N, DAG, DCI, Subtarget);
756 return performADDCombine(N, DAG, DCI, Subtarget);
763 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
764 SmallVectorImpl<SDValue> &Results,
765 SelectionDAG &DAG) const {
766 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
768 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
769 Results.push_back(Res.getValue(I));
773 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
774 SmallVectorImpl<SDValue> &Results,
775 SelectionDAG &DAG) const {
776 return LowerOperationWrapper(N, Results, DAG);
779 SDValue MipsTargetLowering::
780 LowerOperation(SDValue Op, SelectionDAG &DAG) const
782 switch (Op.getOpcode())
784 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
785 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
786 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
787 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
788 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
789 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
790 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
791 case ISD::SELECT: return lowerSELECT(Op, DAG);
792 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
793 case ISD::SETCC: return lowerSETCC(Op, DAG);
794 case ISD::VASTART: return lowerVASTART(Op, DAG);
795 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
796 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
797 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
798 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
799 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
800 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
801 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
802 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
803 case ISD::LOAD: return lowerLOAD(Op, DAG);
804 case ISD::STORE: return lowerSTORE(Op, DAG);
805 case ISD::ADD: return lowerADD(Op, DAG);
806 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
811 //===----------------------------------------------------------------------===//
812 // Lower helper functions
813 //===----------------------------------------------------------------------===//
815 // addLiveIn - This helper function adds the specified physical register to the
816 // MachineFunction as a live in value. It also creates a corresponding
817 // virtual register for it.
819 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
821 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
822 MF.getRegInfo().addLiveIn(PReg, VReg);
826 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
827 MachineBasicBlock &MBB,
828 const TargetInstrInfo &TII,
833 // Insert instruction "teq $divisor_reg, $zero, 7".
834 MachineBasicBlock::iterator I(MI);
835 MachineInstrBuilder MIB;
836 MachineOperand &Divisor = MI->getOperand(2);
837 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
838 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
839 .addReg(Mips::ZERO).addImm(7);
841 // Use the 32-bit sub-register if this is a 64-bit division.
843 MIB->getOperand(0).setSubReg(Mips::sub_32);
845 // Clear Divisor's kill flag.
846 Divisor.setIsKill(false);
848 // We would normally delete the original instruction here but in this case
849 // we only needed to inject an additional instruction rather than replace it.
855 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
856 MachineBasicBlock *BB) const {
857 switch (MI->getOpcode()) {
859 llvm_unreachable("Unexpected instr type to insert");
860 case Mips::ATOMIC_LOAD_ADD_I8:
861 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
862 case Mips::ATOMIC_LOAD_ADD_I16:
863 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
864 case Mips::ATOMIC_LOAD_ADD_I32:
865 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
866 case Mips::ATOMIC_LOAD_ADD_I64:
867 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
869 case Mips::ATOMIC_LOAD_AND_I8:
870 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
871 case Mips::ATOMIC_LOAD_AND_I16:
872 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
873 case Mips::ATOMIC_LOAD_AND_I32:
874 return emitAtomicBinary(MI, BB, 4, Mips::AND);
875 case Mips::ATOMIC_LOAD_AND_I64:
876 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
878 case Mips::ATOMIC_LOAD_OR_I8:
879 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
880 case Mips::ATOMIC_LOAD_OR_I16:
881 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
882 case Mips::ATOMIC_LOAD_OR_I32:
883 return emitAtomicBinary(MI, BB, 4, Mips::OR);
884 case Mips::ATOMIC_LOAD_OR_I64:
885 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
887 case Mips::ATOMIC_LOAD_XOR_I8:
888 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
889 case Mips::ATOMIC_LOAD_XOR_I16:
890 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
891 case Mips::ATOMIC_LOAD_XOR_I32:
892 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
893 case Mips::ATOMIC_LOAD_XOR_I64:
894 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
896 case Mips::ATOMIC_LOAD_NAND_I8:
897 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
898 case Mips::ATOMIC_LOAD_NAND_I16:
899 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
900 case Mips::ATOMIC_LOAD_NAND_I32:
901 return emitAtomicBinary(MI, BB, 4, 0, true);
902 case Mips::ATOMIC_LOAD_NAND_I64:
903 return emitAtomicBinary(MI, BB, 8, 0, true);
905 case Mips::ATOMIC_LOAD_SUB_I8:
906 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
907 case Mips::ATOMIC_LOAD_SUB_I16:
908 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
909 case Mips::ATOMIC_LOAD_SUB_I32:
910 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
911 case Mips::ATOMIC_LOAD_SUB_I64:
912 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
914 case Mips::ATOMIC_SWAP_I8:
915 return emitAtomicBinaryPartword(MI, BB, 1, 0);
916 case Mips::ATOMIC_SWAP_I16:
917 return emitAtomicBinaryPartword(MI, BB, 2, 0);
918 case Mips::ATOMIC_SWAP_I32:
919 return emitAtomicBinary(MI, BB, 4, 0);
920 case Mips::ATOMIC_SWAP_I64:
921 return emitAtomicBinary(MI, BB, 8, 0);
923 case Mips::ATOMIC_CMP_SWAP_I8:
924 return emitAtomicCmpSwapPartword(MI, BB, 1);
925 case Mips::ATOMIC_CMP_SWAP_I16:
926 return emitAtomicCmpSwapPartword(MI, BB, 2);
927 case Mips::ATOMIC_CMP_SWAP_I32:
928 return emitAtomicCmpSwap(MI, BB, 4);
929 case Mips::ATOMIC_CMP_SWAP_I64:
930 return emitAtomicCmpSwap(MI, BB, 8);
931 case Mips::PseudoSDIV:
932 case Mips::PseudoUDIV:
937 return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(),
939 case Mips::PseudoDSDIV:
940 case Mips::PseudoDUDIV:
945 return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(),
948 return emitSEL_D(MI, BB);
952 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
953 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
955 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
956 unsigned Size, unsigned BinOpcode,
958 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
960 MachineFunction *MF = BB->getParent();
961 MachineRegisterInfo &RegInfo = MF->getRegInfo();
962 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
963 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
964 DebugLoc DL = MI->getDebugLoc();
965 unsigned LL, SC, AND, NOR, ZERO, BEQ;
972 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
973 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
980 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
981 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
984 ZERO = Mips::ZERO_64;
988 unsigned OldVal = MI->getOperand(0).getReg();
989 unsigned Ptr = MI->getOperand(1).getReg();
990 unsigned Incr = MI->getOperand(2).getReg();
992 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
993 unsigned AndRes = RegInfo.createVirtualRegister(RC);
994 unsigned Success = RegInfo.createVirtualRegister(RC);
996 // insert new blocks after the current block
997 const BasicBlock *LLVM_BB = BB->getBasicBlock();
998 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
999 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1000 MachineFunction::iterator It = BB;
1002 MF->insert(It, loopMBB);
1003 MF->insert(It, exitMBB);
1005 // Transfer the remainder of BB and its successor edges to exitMBB.
1006 exitMBB->splice(exitMBB->begin(), BB,
1007 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1008 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1012 // fallthrough --> loopMBB
1013 BB->addSuccessor(loopMBB);
1014 loopMBB->addSuccessor(loopMBB);
1015 loopMBB->addSuccessor(exitMBB);
1018 // ll oldval, 0(ptr)
1019 // <binop> storeval, oldval, incr
1020 // sc success, storeval, 0(ptr)
1021 // beq success, $0, loopMBB
1023 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1025 // and andres, oldval, incr
1026 // nor storeval, $0, andres
1027 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1028 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1029 } else if (BinOpcode) {
1030 // <binop> storeval, oldval, incr
1031 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1035 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1036 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1038 MI->eraseFromParent(); // The instruction is gone now.
1043 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1044 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1045 unsigned SrcReg) const {
1046 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1047 DebugLoc DL = MI->getDebugLoc();
1049 if (Subtarget.hasMips32r2() && Size == 1) {
1050 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1054 if (Subtarget.hasMips32r2() && Size == 2) {
1055 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1059 MachineFunction *MF = BB->getParent();
1060 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1061 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1062 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1065 int64_t ShiftImm = 32 - (Size * 8);
1067 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1068 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1073 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1074 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1076 assert((Size == 1 || Size == 2) &&
1077 "Unsupported size for EmitAtomicBinaryPartial.");
1079 MachineFunction *MF = BB->getParent();
1080 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1081 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1082 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1083 DebugLoc DL = MI->getDebugLoc();
1085 unsigned Dest = MI->getOperand(0).getReg();
1086 unsigned Ptr = MI->getOperand(1).getReg();
1087 unsigned Incr = MI->getOperand(2).getReg();
1089 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1090 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1091 unsigned Mask = RegInfo.createVirtualRegister(RC);
1092 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1093 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1094 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1095 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1096 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1097 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1098 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1099 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1100 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1101 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1102 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1103 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1104 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1105 unsigned Success = RegInfo.createVirtualRegister(RC);
1107 // insert new blocks after the current block
1108 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1109 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1110 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1111 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1112 MachineFunction::iterator It = BB;
1114 MF->insert(It, loopMBB);
1115 MF->insert(It, sinkMBB);
1116 MF->insert(It, exitMBB);
1118 // Transfer the remainder of BB and its successor edges to exitMBB.
1119 exitMBB->splice(exitMBB->begin(), BB,
1120 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1121 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1123 BB->addSuccessor(loopMBB);
1124 loopMBB->addSuccessor(loopMBB);
1125 loopMBB->addSuccessor(sinkMBB);
1126 sinkMBB->addSuccessor(exitMBB);
1129 // addiu masklsb2,$0,-4 # 0xfffffffc
1130 // and alignedaddr,ptr,masklsb2
1131 // andi ptrlsb2,ptr,3
1132 // sll shiftamt,ptrlsb2,3
1133 // ori maskupper,$0,255 # 0xff
1134 // sll mask,maskupper,shiftamt
1135 // nor mask2,$0,mask
1136 // sll incr2,incr,shiftamt
1138 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1139 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1140 .addReg(Mips::ZERO).addImm(-4);
1141 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1142 .addReg(Ptr).addReg(MaskLSB2);
1143 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1144 if (Subtarget.isLittle()) {
1145 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1147 unsigned Off = RegInfo.createVirtualRegister(RC);
1148 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1149 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1150 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1152 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1153 .addReg(Mips::ZERO).addImm(MaskImm);
1154 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1155 .addReg(MaskUpper).addReg(ShiftAmt);
1156 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1157 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1159 // atomic.load.binop
1161 // ll oldval,0(alignedaddr)
1162 // binop binopres,oldval,incr2
1163 // and newval,binopres,mask
1164 // and maskedoldval0,oldval,mask2
1165 // or storeval,maskedoldval0,newval
1166 // sc success,storeval,0(alignedaddr)
1167 // beq success,$0,loopMBB
1171 // ll oldval,0(alignedaddr)
1172 // and newval,incr2,mask
1173 // and maskedoldval0,oldval,mask2
1174 // or storeval,maskedoldval0,newval
1175 // sc success,storeval,0(alignedaddr)
1176 // beq success,$0,loopMBB
1179 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1181 // and andres, oldval, incr2
1182 // nor binopres, $0, andres
1183 // and newval, binopres, mask
1184 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1185 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1186 .addReg(Mips::ZERO).addReg(AndRes);
1187 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1188 } else if (BinOpcode) {
1189 // <binop> binopres, oldval, incr2
1190 // and newval, binopres, mask
1191 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1192 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1193 } else { // atomic.swap
1194 // and newval, incr2, mask
1195 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1198 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1199 .addReg(OldVal).addReg(Mask2);
1200 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1201 .addReg(MaskedOldVal0).addReg(NewVal);
1202 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1203 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1204 BuildMI(BB, DL, TII->get(Mips::BEQ))
1205 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1208 // and maskedoldval1,oldval,mask
1209 // srl srlres,maskedoldval1,shiftamt
1210 // sign_extend dest,srlres
1213 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1214 .addReg(OldVal).addReg(Mask);
1215 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1216 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1217 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1219 MI->eraseFromParent(); // The instruction is gone now.
1224 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1225 MachineBasicBlock *BB,
1226 unsigned Size) const {
1227 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1229 MachineFunction *MF = BB->getParent();
1230 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1231 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1232 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1233 DebugLoc DL = MI->getDebugLoc();
1234 unsigned LL, SC, ZERO, BNE, BEQ;
1237 LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1238 SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1245 ZERO = Mips::ZERO_64;
1250 unsigned Dest = MI->getOperand(0).getReg();
1251 unsigned Ptr = MI->getOperand(1).getReg();
1252 unsigned OldVal = MI->getOperand(2).getReg();
1253 unsigned NewVal = MI->getOperand(3).getReg();
1255 unsigned Success = RegInfo.createVirtualRegister(RC);
1257 // insert new blocks after the current block
1258 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1259 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1260 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1261 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1262 MachineFunction::iterator It = BB;
1264 MF->insert(It, loop1MBB);
1265 MF->insert(It, loop2MBB);
1266 MF->insert(It, exitMBB);
1268 // Transfer the remainder of BB and its successor edges to exitMBB.
1269 exitMBB->splice(exitMBB->begin(), BB,
1270 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1271 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1275 // fallthrough --> loop1MBB
1276 BB->addSuccessor(loop1MBB);
1277 loop1MBB->addSuccessor(exitMBB);
1278 loop1MBB->addSuccessor(loop2MBB);
1279 loop2MBB->addSuccessor(loop1MBB);
1280 loop2MBB->addSuccessor(exitMBB);
1284 // bne dest, oldval, exitMBB
1286 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1287 BuildMI(BB, DL, TII->get(BNE))
1288 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1291 // sc success, newval, 0(ptr)
1292 // beq success, $0, loop1MBB
1294 BuildMI(BB, DL, TII->get(SC), Success)
1295 .addReg(NewVal).addReg(Ptr).addImm(0);
1296 BuildMI(BB, DL, TII->get(BEQ))
1297 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1299 MI->eraseFromParent(); // The instruction is gone now.
1305 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1306 MachineBasicBlock *BB,
1307 unsigned Size) const {
1308 assert((Size == 1 || Size == 2) &&
1309 "Unsupported size for EmitAtomicCmpSwapPartial.");
1311 MachineFunction *MF = BB->getParent();
1312 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1313 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1314 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1315 DebugLoc DL = MI->getDebugLoc();
1317 unsigned Dest = MI->getOperand(0).getReg();
1318 unsigned Ptr = MI->getOperand(1).getReg();
1319 unsigned CmpVal = MI->getOperand(2).getReg();
1320 unsigned NewVal = MI->getOperand(3).getReg();
1322 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1323 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1324 unsigned Mask = RegInfo.createVirtualRegister(RC);
1325 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1326 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1327 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1328 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1329 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1330 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1331 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1332 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1333 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1334 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1335 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1336 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1337 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1338 unsigned Success = RegInfo.createVirtualRegister(RC);
1340 // insert new blocks after the current block
1341 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1342 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1343 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1344 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1345 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1346 MachineFunction::iterator It = BB;
1348 MF->insert(It, loop1MBB);
1349 MF->insert(It, loop2MBB);
1350 MF->insert(It, sinkMBB);
1351 MF->insert(It, exitMBB);
1353 // Transfer the remainder of BB and its successor edges to exitMBB.
1354 exitMBB->splice(exitMBB->begin(), BB,
1355 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1356 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1358 BB->addSuccessor(loop1MBB);
1359 loop1MBB->addSuccessor(sinkMBB);
1360 loop1MBB->addSuccessor(loop2MBB);
1361 loop2MBB->addSuccessor(loop1MBB);
1362 loop2MBB->addSuccessor(sinkMBB);
1363 sinkMBB->addSuccessor(exitMBB);
1365 // FIXME: computation of newval2 can be moved to loop2MBB.
1367 // addiu masklsb2,$0,-4 # 0xfffffffc
1368 // and alignedaddr,ptr,masklsb2
1369 // andi ptrlsb2,ptr,3
1370 // sll shiftamt,ptrlsb2,3
1371 // ori maskupper,$0,255 # 0xff
1372 // sll mask,maskupper,shiftamt
1373 // nor mask2,$0,mask
1374 // andi maskedcmpval,cmpval,255
1375 // sll shiftedcmpval,maskedcmpval,shiftamt
1376 // andi maskednewval,newval,255
1377 // sll shiftednewval,maskednewval,shiftamt
1378 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1379 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1380 .addReg(Mips::ZERO).addImm(-4);
1381 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1382 .addReg(Ptr).addReg(MaskLSB2);
1383 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1384 if (Subtarget.isLittle()) {
1385 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1387 unsigned Off = RegInfo.createVirtualRegister(RC);
1388 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1389 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1390 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1392 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1393 .addReg(Mips::ZERO).addImm(MaskImm);
1394 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1395 .addReg(MaskUpper).addReg(ShiftAmt);
1396 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1397 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1398 .addReg(CmpVal).addImm(MaskImm);
1399 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1400 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1401 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1402 .addReg(NewVal).addImm(MaskImm);
1403 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1404 .addReg(MaskedNewVal).addReg(ShiftAmt);
1407 // ll oldval,0(alginedaddr)
1408 // and maskedoldval0,oldval,mask
1409 // bne maskedoldval0,shiftedcmpval,sinkMBB
1411 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1412 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1413 .addReg(OldVal).addReg(Mask);
1414 BuildMI(BB, DL, TII->get(Mips::BNE))
1415 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1418 // and maskedoldval1,oldval,mask2
1419 // or storeval,maskedoldval1,shiftednewval
1420 // sc success,storeval,0(alignedaddr)
1421 // beq success,$0,loop1MBB
1423 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1424 .addReg(OldVal).addReg(Mask2);
1425 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1426 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1427 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1428 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1429 BuildMI(BB, DL, TII->get(Mips::BEQ))
1430 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1433 // srl srlres,maskedoldval0,shiftamt
1434 // sign_extend dest,srlres
1437 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1438 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1439 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1441 MI->eraseFromParent(); // The instruction is gone now.
1446 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
1447 MachineBasicBlock *BB) const {
1448 MachineFunction *MF = BB->getParent();
1449 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1450 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1451 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1452 DebugLoc DL = MI->getDebugLoc();
1453 MachineBasicBlock::iterator II(MI);
1455 unsigned Fc = MI->getOperand(1).getReg();
1456 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1458 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1460 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1463 .addImm(Mips::sub_lo);
1465 // We don't erase the original instruction, we just replace the condition
1466 // register with the 64-bit super-register.
1467 MI->getOperand(1).setReg(Fc2);
1472 //===----------------------------------------------------------------------===//
1473 // Misc Lower Operation implementation
1474 //===----------------------------------------------------------------------===//
1475 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1476 SDValue Chain = Op.getOperand(0);
1477 SDValue Table = Op.getOperand(1);
1478 SDValue Index = Op.getOperand(2);
1480 EVT PTy = getPointerTy();
1481 unsigned EntrySize =
1482 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1484 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1485 DAG.getConstant(EntrySize, PTy));
1486 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1488 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1489 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1490 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1492 Chain = Addr.getValue(1);
1494 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) ||
1495 Subtarget.isABI_N64()) {
1496 // For PIC, the sequence is:
1497 // BRIND(load(Jumptable + index) + RelocBase)
1498 // RelocBase can be JumpTable, GOT or some sort of global base.
1499 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1500 getPICJumpTableRelocBase(Table, DAG));
1503 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1506 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1507 // The first operand is the chain, the second is the condition, the third is
1508 // the block to branch to if the condition is true.
1509 SDValue Chain = Op.getOperand(0);
1510 SDValue Dest = Op.getOperand(2);
1513 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1514 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1516 // Return if flag is not set by a floating point comparison.
1517 if (CondRes.getOpcode() != MipsISD::FPCmp)
1520 SDValue CCNode = CondRes.getOperand(2);
1522 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1523 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1524 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1525 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1526 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1527 FCC0, Dest, CondRes);
1530 SDValue MipsTargetLowering::
1531 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1533 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1534 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1536 // Return if flag is not set by a floating point comparison.
1537 if (Cond.getOpcode() != MipsISD::FPCmp)
1540 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1544 SDValue MipsTargetLowering::
1545 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1548 EVT Ty = Op.getOperand(0).getValueType();
1549 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1550 getSetCCResultType(*DAG.getContext(), Ty),
1551 Op.getOperand(0), Op.getOperand(1),
1554 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1558 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1559 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1560 SDValue Cond = createFPCmp(DAG, Op);
1562 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1563 "Floating point operand expected.");
1565 SDValue True = DAG.getConstant(1, MVT::i32);
1566 SDValue False = DAG.getConstant(0, MVT::i32);
1568 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1571 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1572 SelectionDAG &DAG) const {
1573 // FIXME there isn't actually debug info here
1575 EVT Ty = Op.getValueType();
1576 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1577 const GlobalValue *GV = N->getGlobal();
1579 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1580 !Subtarget.isABI_N64()) {
1581 const MipsTargetObjectFile &TLOF =
1582 (const MipsTargetObjectFile&)getObjFileLowering();
1584 // %gp_rel relocation
1585 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1586 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
1588 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
1589 DAG.getVTList(MVT::i32), GA);
1590 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1591 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1594 // %hi/%lo relocation
1595 return getAddrNonPIC(N, Ty, DAG);
1598 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1599 return getAddrLocal(N, Ty, DAG,
1600 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1603 return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
1604 MipsII::MO_GOT_LO16, DAG.getEntryNode(),
1605 MachinePointerInfo::getGOT());
1607 return getAddrGlobal(N, Ty, DAG,
1608 (Subtarget.isABI_N32() || Subtarget.isABI_N64())
1609 ? MipsII::MO_GOT_DISP
1611 DAG.getEntryNode(), MachinePointerInfo::getGOT());
1614 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1615 SelectionDAG &DAG) const {
1616 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1617 EVT Ty = Op.getValueType();
1619 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1620 !Subtarget.isABI_N64())
1621 return getAddrNonPIC(N, Ty, DAG);
1623 return getAddrLocal(N, Ty, DAG,
1624 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1627 SDValue MipsTargetLowering::
1628 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1630 // If the relocation model is PIC, use the General Dynamic TLS Model or
1631 // Local Dynamic TLS model, otherwise use the Initial Exec or
1632 // Local Exec TLS Model.
1634 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1636 const GlobalValue *GV = GA->getGlobal();
1637 EVT PtrVT = getPointerTy();
1639 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1641 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1642 // General Dynamic and Local Dynamic TLS Model.
1643 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1646 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1647 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1648 getGlobalReg(DAG, PtrVT), TGA);
1649 unsigned PtrSize = PtrVT.getSizeInBits();
1650 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1652 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1656 Entry.Node = Argument;
1658 Args.push_back(Entry);
1660 TargetLowering::CallLoweringInfo CLI(DAG);
1661 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1662 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1663 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1665 SDValue Ret = CallResult.first;
1667 if (model != TLSModel::LocalDynamic)
1670 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1671 MipsII::MO_DTPREL_HI);
1672 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1673 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1674 MipsII::MO_DTPREL_LO);
1675 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1676 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1677 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1681 if (model == TLSModel::InitialExec) {
1682 // Initial Exec TLS Model
1683 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1684 MipsII::MO_GOTTPREL);
1685 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1687 Offset = DAG.getLoad(PtrVT, DL,
1688 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1689 false, false, false, 0);
1691 // Local Exec TLS Model
1692 assert(model == TLSModel::LocalExec);
1693 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1694 MipsII::MO_TPREL_HI);
1695 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1696 MipsII::MO_TPREL_LO);
1697 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1698 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1699 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1702 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1703 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1706 SDValue MipsTargetLowering::
1707 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1709 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1710 EVT Ty = Op.getValueType();
1712 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1713 !Subtarget.isABI_N64())
1714 return getAddrNonPIC(N, Ty, DAG);
1716 return getAddrLocal(N, Ty, DAG,
1717 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1720 SDValue MipsTargetLowering::
1721 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1723 // gp_rel relocation
1724 // FIXME: we should reference the constant pool using small data sections,
1725 // but the asm printer currently doesn't support this feature without
1726 // hacking it. This feature should come soon so we can uncomment the
1728 //if (IsInSmallSection(C->getType())) {
1729 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1730 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1731 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1732 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1733 EVT Ty = Op.getValueType();
1735 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1736 !Subtarget.isABI_N64())
1737 return getAddrNonPIC(N, Ty, DAG);
1739 return getAddrLocal(N, Ty, DAG,
1740 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1743 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1744 MachineFunction &MF = DAG.getMachineFunction();
1745 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1748 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1751 // vastart just stores the address of the VarArgsFrameIndex slot into the
1752 // memory location argument.
1753 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1754 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1755 MachinePointerInfo(SV), false, false, 0);
1758 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1759 bool HasExtractInsert) {
1760 EVT TyX = Op.getOperand(0).getValueType();
1761 EVT TyY = Op.getOperand(1).getValueType();
1762 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1763 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1767 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1769 SDValue X = (TyX == MVT::f32) ?
1770 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1771 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1773 SDValue Y = (TyY == MVT::f32) ?
1774 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1775 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1778 if (HasExtractInsert) {
1779 // ext E, Y, 31, 1 ; extract bit31 of Y
1780 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1781 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1782 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1785 // srl SrlX, SllX, 1
1787 // sll SllY, SrlX, 31
1788 // or Or, SrlX, SllY
1789 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1790 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1791 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1792 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1793 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1796 if (TyX == MVT::f32)
1797 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1799 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1800 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1801 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1804 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
1805 bool HasExtractInsert) {
1806 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1807 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1808 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1809 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1812 // Bitcast to integer nodes.
1813 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1814 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1816 if (HasExtractInsert) {
1817 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1818 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1819 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1820 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1822 if (WidthX > WidthY)
1823 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1824 else if (WidthY > WidthX)
1825 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1827 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1828 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1829 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1832 // (d)sll SllX, X, 1
1833 // (d)srl SrlX, SllX, 1
1834 // (d)srl SrlY, Y, width(Y)-1
1835 // (d)sll SllY, SrlX, width(Y)-1
1836 // or Or, SrlX, SllY
1837 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1838 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1839 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1840 DAG.getConstant(WidthY - 1, MVT::i32));
1842 if (WidthX > WidthY)
1843 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1844 else if (WidthY > WidthX)
1845 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1847 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1848 DAG.getConstant(WidthX - 1, MVT::i32));
1849 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1850 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1854 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1855 if (Subtarget.isGP64bit())
1856 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
1858 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
1861 SDValue MipsTargetLowering::
1862 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1864 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1865 "Frame address can only be determined for current frame.");
1867 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1868 MFI->setFrameAddressIsTaken(true);
1869 EVT VT = Op.getValueType();
1872 DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1873 Subtarget.isABI_N64() ? Mips::FP_64 : Mips::FP, VT);
1877 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1878 SelectionDAG &DAG) const {
1879 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1883 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1884 "Return address can be determined only for current frame.");
1886 MachineFunction &MF = DAG.getMachineFunction();
1887 MachineFrameInfo *MFI = MF.getFrameInfo();
1888 MVT VT = Op.getSimpleValueType();
1889 unsigned RA = Subtarget.isABI_N64() ? Mips::RA_64 : Mips::RA;
1890 MFI->setReturnAddressIsTaken(true);
1892 // Return RA, which contains the return address. Mark it an implicit live-in.
1893 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
1894 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
1897 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
1898 // generated from __builtin_eh_return (offset, handler)
1899 // The effect of this is to adjust the stack pointer by "offset"
1900 // and then branch to "handler".
1901 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
1903 MachineFunction &MF = DAG.getMachineFunction();
1904 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1906 MipsFI->setCallsEhReturn();
1907 SDValue Chain = Op.getOperand(0);
1908 SDValue Offset = Op.getOperand(1);
1909 SDValue Handler = Op.getOperand(2);
1911 EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
1913 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
1914 // EH_RETURN nodes, so that instructions are emitted back-to-back.
1915 unsigned OffsetReg = Subtarget.isABI_N64() ? Mips::V1_64 : Mips::V1;
1916 unsigned AddrReg = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
1917 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
1918 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
1919 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
1920 DAG.getRegister(OffsetReg, Ty),
1921 DAG.getRegister(AddrReg, getPointerTy()),
1925 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
1926 SelectionDAG &DAG) const {
1927 // FIXME: Need pseudo-fence for 'singlethread' fences
1928 // FIXME: Set SType for weaker fences where supported/appropriate.
1931 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
1932 DAG.getConstant(SType, MVT::i32));
1935 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
1936 SelectionDAG &DAG) const {
1938 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1939 SDValue Shamt = Op.getOperand(2);
1942 // lo = (shl lo, shamt)
1943 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
1946 // hi = (shl lo, shamt[4:0])
1947 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1948 DAG.getConstant(-1, MVT::i32));
1949 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1950 DAG.getConstant(1, MVT::i32));
1951 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1953 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1954 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1955 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1956 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1957 DAG.getConstant(0x20, MVT::i32));
1958 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1959 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
1960 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1962 SDValue Ops[2] = {Lo, Hi};
1963 return DAG.getMergeValues(Ops, DL);
1966 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
1969 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1970 SDValue Shamt = Op.getOperand(2);
1973 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
1975 // hi = (sra hi, shamt)
1977 // hi = (srl hi, shamt)
1980 // lo = (sra hi, shamt[4:0])
1981 // hi = (sra hi, 31)
1983 // lo = (srl hi, shamt[4:0])
1985 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1986 DAG.getConstant(-1, MVT::i32));
1987 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
1988 DAG.getConstant(1, MVT::i32));
1989 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
1990 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1991 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1992 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1994 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1995 DAG.getConstant(0x20, MVT::i32));
1996 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
1997 DAG.getConstant(31, MVT::i32));
1998 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
1999 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2000 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2003 SDValue Ops[2] = {Lo, Hi};
2004 return DAG.getMergeValues(Ops, DL);
2007 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2008 SDValue Chain, SDValue Src, unsigned Offset) {
2009 SDValue Ptr = LD->getBasePtr();
2010 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2011 EVT BasePtrVT = Ptr.getValueType();
2013 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2016 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2017 DAG.getConstant(Offset, BasePtrVT));
2019 SDValue Ops[] = { Chain, Ptr, Src };
2020 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2021 LD->getMemOperand());
2024 // Expand an unaligned 32 or 64-bit integer load node.
2025 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2026 LoadSDNode *LD = cast<LoadSDNode>(Op);
2027 EVT MemVT = LD->getMemoryVT();
2029 if (Subtarget.systemSupportsUnalignedAccess())
2032 // Return if load is aligned or if MemVT is neither i32 nor i64.
2033 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2034 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2037 bool IsLittle = Subtarget.isLittle();
2038 EVT VT = Op.getValueType();
2039 ISD::LoadExtType ExtType = LD->getExtensionType();
2040 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2042 assert((VT == MVT::i32) || (VT == MVT::i64));
2045 // (set dst, (i64 (load baseptr)))
2047 // (set tmp, (ldl (add baseptr, 7), undef))
2048 // (set dst, (ldr baseptr, tmp))
2049 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2050 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2052 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2056 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2058 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2062 // (set dst, (i32 (load baseptr))) or
2063 // (set dst, (i64 (sextload baseptr))) or
2064 // (set dst, (i64 (extload baseptr)))
2066 // (set tmp, (lwl (add baseptr, 3), undef))
2067 // (set dst, (lwr baseptr, tmp))
2068 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2069 (ExtType == ISD::EXTLOAD))
2072 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2075 // (set dst, (i64 (zextload baseptr)))
2077 // (set tmp0, (lwl (add baseptr, 3), undef))
2078 // (set tmp1, (lwr baseptr, tmp0))
2079 // (set tmp2, (shl tmp1, 32))
2080 // (set dst, (srl tmp2, 32))
2082 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2083 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2084 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2085 SDValue Ops[] = { SRL, LWR.getValue(1) };
2086 return DAG.getMergeValues(Ops, DL);
2089 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2090 SDValue Chain, unsigned Offset) {
2091 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2092 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2094 SDVTList VTList = DAG.getVTList(MVT::Other);
2097 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2098 DAG.getConstant(Offset, BasePtrVT));
2100 SDValue Ops[] = { Chain, Value, Ptr };
2101 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2102 SD->getMemOperand());
2105 // Expand an unaligned 32 or 64-bit integer store node.
2106 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2108 SDValue Value = SD->getValue(), Chain = SD->getChain();
2109 EVT VT = Value.getValueType();
2112 // (store val, baseptr) or
2113 // (truncstore val, baseptr)
2115 // (swl val, (add baseptr, 3))
2116 // (swr val, baseptr)
2117 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2118 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2120 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2123 assert(VT == MVT::i64);
2126 // (store val, baseptr)
2128 // (sdl val, (add baseptr, 7))
2129 // (sdr val, baseptr)
2130 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2131 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2134 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2135 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2136 SDValue Val = SD->getValue();
2138 if (Val.getOpcode() != ISD::FP_TO_SINT)
2141 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2142 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2145 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2146 SD->getPointerInfo(), SD->isVolatile(),
2147 SD->isNonTemporal(), SD->getAlignment());
2150 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2151 StoreSDNode *SD = cast<StoreSDNode>(Op);
2152 EVT MemVT = SD->getMemoryVT();
2154 // Lower unaligned integer stores.
2155 if (!Subtarget.systemSupportsUnalignedAccess() &&
2156 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2157 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2158 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2160 return lowerFP_TO_SINT_STORE(SD, DAG);
2163 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2164 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2165 || cast<ConstantSDNode>
2166 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2167 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2171 // (add (frameaddr 0), (frame_to_args_offset))
2172 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2173 // (add FrameObject, 0)
2174 // where FrameObject is a fixed StackObject with offset 0 which points to
2175 // the old stack pointer.
2176 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2177 EVT ValTy = Op->getValueType(0);
2178 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2179 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2180 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2181 DAG.getConstant(0, ValTy));
2184 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2185 SelectionDAG &DAG) const {
2186 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2187 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2189 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2192 //===----------------------------------------------------------------------===//
2193 // Calling Convention Implementation
2194 //===----------------------------------------------------------------------===//
2196 //===----------------------------------------------------------------------===//
2197 // TODO: Implement a generic logic using tblgen that can support this.
2198 // Mips O32 ABI rules:
2200 // i32 - Passed in A0, A1, A2, A3 and stack
2201 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2202 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2203 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2204 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2205 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2208 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2209 //===----------------------------------------------------------------------===//
2211 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2212 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2213 CCState &State, const MCPhysReg *F64Regs) {
2215 static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
2217 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2218 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2220 // Do not process byval args here.
2221 if (ArgFlags.isByVal())
2224 // Promote i8 and i16
2225 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2227 if (ArgFlags.isSExt())
2228 LocInfo = CCValAssign::SExt;
2229 else if (ArgFlags.isZExt())
2230 LocInfo = CCValAssign::ZExt;
2232 LocInfo = CCValAssign::AExt;
2237 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2238 // is true: function is vararg, argument is 3rd or higher, there is previous
2239 // argument which is not f32 or f64.
2240 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2241 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2242 unsigned OrigAlign = ArgFlags.getOrigAlign();
2243 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2245 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2246 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2247 // If this is the first part of an i64 arg,
2248 // the allocated register must be either A0 or A2.
2249 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2250 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2252 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2253 // Allocate int register and shadow next int register. If first
2254 // available register is Mips::A1 or Mips::A3, shadow it too.
2255 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2256 if (Reg == Mips::A1 || Reg == Mips::A3)
2257 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2258 State.AllocateReg(IntRegs, IntRegsSize);
2260 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2261 // we are guaranteed to find an available float register
2262 if (ValVT == MVT::f32) {
2263 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2264 // Shadow int register
2265 State.AllocateReg(IntRegs, IntRegsSize);
2267 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2268 // Shadow int registers
2269 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2270 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2271 State.AllocateReg(IntRegs, IntRegsSize);
2272 State.AllocateReg(IntRegs, IntRegsSize);
2275 llvm_unreachable("Cannot handle this ValVT.");
2278 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2280 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2282 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2287 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2288 MVT LocVT, CCValAssign::LocInfo LocInfo,
2289 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2290 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2292 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2295 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2296 MVT LocVT, CCValAssign::LocInfo LocInfo,
2297 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2298 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2300 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2303 #include "MipsGenCallingConv.inc"
2305 //===----------------------------------------------------------------------===//
2306 // Call Calling Convention Implementation
2307 //===----------------------------------------------------------------------===//
2309 // Return next O32 integer argument register.
2310 static unsigned getNextIntArgReg(unsigned Reg) {
2311 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2312 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2316 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2317 SDValue Chain, SDValue Arg, SDLoc DL,
2318 bool IsTailCall, SelectionDAG &DAG) const {
2320 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2321 DAG.getIntPtrConstant(Offset));
2322 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2326 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2327 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2328 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2329 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2330 /*isVolatile=*/ true, false, 0);
2333 void MipsTargetLowering::
2334 getOpndList(SmallVectorImpl<SDValue> &Ops,
2335 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2336 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2337 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
2338 // Insert node "GP copy globalreg" before call to function.
2340 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2341 // in PIC mode) allow symbols to be resolved via lazy binding.
2342 // The lazy binding stub requires GP to point to the GOT.
2343 if (IsPICCall && !InternalLinkage) {
2344 unsigned GPReg = Subtarget.isABI_N64() ? Mips::GP_64 : Mips::GP;
2345 EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
2346 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2349 // Build a sequence of copy-to-reg nodes chained together with token
2350 // chain and flag operands which copy the outgoing args into registers.
2351 // The InFlag in necessary since all emitted instructions must be
2355 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2356 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2357 RegsToPass[i].second, InFlag);
2358 InFlag = Chain.getValue(1);
2361 // Add argument registers to the end of the list so that they are
2362 // known live into the call.
2363 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2364 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2365 RegsToPass[i].second.getValueType()));
2367 // Add a register mask operand representing the call-preserved registers.
2368 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2369 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2370 assert(Mask && "Missing call preserved mask for calling convention");
2371 if (Subtarget.inMips16HardFloat()) {
2372 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2373 llvm::StringRef Sym = G->getGlobal()->getName();
2374 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2375 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2376 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2380 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2382 if (InFlag.getNode())
2383 Ops.push_back(InFlag);
2386 /// LowerCall - functions arguments are copied from virtual regs to
2387 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2389 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2390 SmallVectorImpl<SDValue> &InVals) const {
2391 SelectionDAG &DAG = CLI.DAG;
2393 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2394 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2395 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2396 SDValue Chain = CLI.Chain;
2397 SDValue Callee = CLI.Callee;
2398 bool &IsTailCall = CLI.IsTailCall;
2399 CallingConv::ID CallConv = CLI.CallConv;
2400 bool IsVarArg = CLI.IsVarArg;
2402 MachineFunction &MF = DAG.getMachineFunction();
2403 MachineFrameInfo *MFI = MF.getFrameInfo();
2404 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2405 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2406 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2408 // Analyze operands of the call, assigning locations to each operand.
2409 SmallVector<CCValAssign, 16> ArgLocs;
2410 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2411 getTargetMachine(), ArgLocs, *DAG.getContext());
2412 MipsCC::SpecialCallingConvType SpecialCallingConv =
2413 getSpecialCallingConv(Callee);
2414 MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
2415 CCInfo, SpecialCallingConv);
2417 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2418 Subtarget.abiUsesSoftFloat(),
2419 Callee.getNode(), CLI.getArgs());
2421 // Get a count of how many bytes are to be pushed on the stack.
2422 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2424 // Check if it's really possible to do a tail call.
2427 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2428 *MF.getInfo<MipsFunctionInfo>());
2430 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2431 report_fatal_error("failed to perform tail call elimination on a call "
2432 "site marked musttail");
2437 // Chain is the output chain of the last Load/Store or CopyToReg node.
2438 // ByValChain is the output chain of the last Memcpy node created for copying
2439 // byval arguments to the stack.
2440 unsigned StackAlignment = TFL->getStackAlignment();
2441 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2442 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2445 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2447 SDValue StackPtr = DAG.getCopyFromReg(
2448 Chain, DL, Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP,
2451 // With EABI is it possible to have 16 args on registers.
2452 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2453 SmallVector<SDValue, 8> MemOpChains;
2454 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2456 // Walk the register/memloc assignments, inserting copies/loads.
2457 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2458 SDValue Arg = OutVals[i];
2459 CCValAssign &VA = ArgLocs[i];
2460 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2461 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2464 if (Flags.isByVal()) {
2465 assert(Flags.getByValSize() &&
2466 "ByVal args of size 0 should have been ignored by front-end.");
2467 assert(ByValArg != MipsCCInfo.byval_end());
2468 assert(!IsTailCall &&
2469 "Do not tail-call optimize if there is a byval argument.");
2470 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2471 MipsCCInfo, *ByValArg, Flags, Subtarget.isLittle());
2476 // Promote the value if needed.
2477 switch (VA.getLocInfo()) {
2478 default: llvm_unreachable("Unknown loc info!");
2479 case CCValAssign::Full:
2480 if (VA.isRegLoc()) {
2481 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2482 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2483 (ValVT == MVT::i64 && LocVT == MVT::f64))
2484 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2485 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2486 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2487 Arg, DAG.getConstant(0, MVT::i32));
2488 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2489 Arg, DAG.getConstant(1, MVT::i32));
2490 if (!Subtarget.isLittle())
2492 unsigned LocRegLo = VA.getLocReg();
2493 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2494 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2495 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2500 case CCValAssign::SExt:
2501 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2503 case CCValAssign::ZExt:
2504 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2506 case CCValAssign::AExt:
2507 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2511 // Arguments that can be passed on register must be kept at
2512 // RegsToPass vector
2513 if (VA.isRegLoc()) {
2514 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2518 // Register can't get to this point...
2519 assert(VA.isMemLoc());
2521 // emit ISD::STORE whichs stores the
2522 // parameter value to a stack Location
2523 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2524 Chain, Arg, DL, IsTailCall, DAG));
2527 // Transform all store nodes into one single node because all store
2528 // nodes are independent of each other.
2529 if (!MemOpChains.empty())
2530 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2532 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2533 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2534 // node so that legalize doesn't hack it.
2536 (Subtarget.isABI_N64() || IsPIC); // true if calls are translated to
2538 bool GlobalOrExternal = false, InternalLinkage = false;
2540 EVT Ty = Callee.getValueType();
2542 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2544 const GlobalValue *Val = G->getGlobal();
2545 InternalLinkage = Val->hasInternalLinkage();
2547 if (InternalLinkage)
2548 Callee = getAddrLocal(G, Ty, DAG,
2549 Subtarget.isABI_N32() || Subtarget.isABI_N64());
2551 Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
2552 MipsII::MO_CALL_LO16, Chain,
2553 FuncInfo->callPtrInfo(Val));
2555 Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2556 FuncInfo->callPtrInfo(Val));
2558 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2559 MipsII::MO_NO_FLAG);
2560 GlobalOrExternal = true;
2562 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2563 const char *Sym = S->getSymbol();
2565 if (!Subtarget.isABI_N64() && !IsPIC) // !N64 && static
2566 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
2567 MipsII::MO_NO_FLAG);
2569 Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16,
2570 MipsII::MO_CALL_LO16, Chain,
2571 FuncInfo->callPtrInfo(Sym));
2573 Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2574 FuncInfo->callPtrInfo(Sym));
2576 GlobalOrExternal = true;
2579 SmallVector<SDValue, 8> Ops(1, Chain);
2580 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2582 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2583 CLI, Callee, Chain);
2586 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2588 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2589 SDValue InFlag = Chain.getValue(1);
2591 // Create the CALLSEQ_END node.
2592 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2593 DAG.getIntPtrConstant(0, true), InFlag, DL);
2594 InFlag = Chain.getValue(1);
2596 // Handle result values, copying them out of physregs into vregs that we
2598 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
2599 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
2602 /// LowerCallResult - Lower the result values of a call into the
2603 /// appropriate copies out of appropriate physical registers.
2605 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2606 CallingConv::ID CallConv, bool IsVarArg,
2607 const SmallVectorImpl<ISD::InputArg> &Ins,
2608 SDLoc DL, SelectionDAG &DAG,
2609 SmallVectorImpl<SDValue> &InVals,
2610 const SDNode *CallNode,
2611 const Type *RetTy) const {
2612 // Assign locations to each value returned by this call.
2613 SmallVector<CCValAssign, 16> RVLocs;
2614 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2615 getTargetMachine(), RVLocs, *DAG.getContext());
2616 MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
2619 MipsCCInfo.analyzeCallResult(Ins, Subtarget.abiUsesSoftFloat(),
2622 // Copy all of the result registers out of their specified physreg.
2623 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2624 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2625 RVLocs[i].getLocVT(), InFlag);
2626 Chain = Val.getValue(1);
2627 InFlag = Val.getValue(2);
2629 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2630 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2632 InVals.push_back(Val);
2638 //===----------------------------------------------------------------------===//
2639 // Formal Arguments Calling Convention Implementation
2640 //===----------------------------------------------------------------------===//
2641 /// LowerFormalArguments - transform physical registers into virtual registers
2642 /// and generate load operations for arguments places on the stack.
2644 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2645 CallingConv::ID CallConv,
2647 const SmallVectorImpl<ISD::InputArg> &Ins,
2648 SDLoc DL, SelectionDAG &DAG,
2649 SmallVectorImpl<SDValue> &InVals)
2651 MachineFunction &MF = DAG.getMachineFunction();
2652 MachineFrameInfo *MFI = MF.getFrameInfo();
2653 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2655 MipsFI->setVarArgsFrameIndex(0);
2657 // Used with vargs to acumulate store chains.
2658 std::vector<SDValue> OutChains;
2660 // Assign locations to all of the incoming arguments.
2661 SmallVector<CCValAssign, 16> ArgLocs;
2662 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2663 getTargetMachine(), ArgLocs, *DAG.getContext());
2664 MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
2666 Function::const_arg_iterator FuncArg =
2667 DAG.getMachineFunction().getFunction()->arg_begin();
2668 bool UseSoftFloat = Subtarget.abiUsesSoftFloat();
2670 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
2671 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2672 MipsCCInfo.hasByValArg());
2674 unsigned CurArgIdx = 0;
2675 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2677 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2678 CCValAssign &VA = ArgLocs[i];
2679 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2680 CurArgIdx = Ins[i].OrigArgIndex;
2681 EVT ValVT = VA.getValVT();
2682 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2683 bool IsRegLoc = VA.isRegLoc();
2685 if (Flags.isByVal()) {
2686 assert(Flags.getByValSize() &&
2687 "ByVal args of size 0 should have been ignored by front-end.");
2688 assert(ByValArg != MipsCCInfo.byval_end());
2689 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2690 MipsCCInfo, *ByValArg);
2695 // Arguments stored on registers
2697 MVT RegVT = VA.getLocVT();
2698 unsigned ArgReg = VA.getLocReg();
2699 const TargetRegisterClass *RC = getRegClassFor(RegVT);
2701 // Transform the arguments stored on
2702 // physical registers into virtual ones
2703 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2704 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2706 // If this is an 8 or 16-bit value, it has been passed promoted
2707 // to 32 bits. Insert an assert[sz]ext to capture this, then
2708 // truncate to the right size.
2709 if (VA.getLocInfo() != CCValAssign::Full) {
2710 unsigned Opcode = 0;
2711 if (VA.getLocInfo() == CCValAssign::SExt)
2712 Opcode = ISD::AssertSext;
2713 else if (VA.getLocInfo() == CCValAssign::ZExt)
2714 Opcode = ISD::AssertZext;
2716 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2717 DAG.getValueType(ValVT));
2718 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2721 // Handle floating point arguments passed in integer registers and
2722 // long double arguments passed in floating point registers.
2723 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2724 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2725 (RegVT == MVT::f64 && ValVT == MVT::i64))
2726 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2727 else if (Subtarget.isABI_O32() && RegVT == MVT::i32 &&
2728 ValVT == MVT::f64) {
2729 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2730 getNextIntArgReg(ArgReg), RC);
2731 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2732 if (!Subtarget.isLittle())
2733 std::swap(ArgValue, ArgValue2);
2734 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2735 ArgValue, ArgValue2);
2738 InVals.push_back(ArgValue);
2739 } else { // VA.isRegLoc()
2742 assert(VA.isMemLoc());
2744 // The stack pointer offset is relative to the caller stack frame.
2745 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2746 VA.getLocMemOffset(), true);
2748 // Create load nodes to retrieve arguments from the stack
2749 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2750 SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN,
2751 MachinePointerInfo::getFixedStack(FI),
2752 false, false, false, 0);
2753 InVals.push_back(Load);
2754 OutChains.push_back(Load.getValue(1));
2758 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2759 // The mips ABIs for returning structs by value requires that we copy
2760 // the sret argument into $v0 for the return. Save the argument into
2761 // a virtual register so that we can access it from the return points.
2762 if (Ins[i].Flags.isSRet()) {
2763 unsigned Reg = MipsFI->getSRetReturnReg();
2765 Reg = MF.getRegInfo().createVirtualRegister(
2766 getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32));
2767 MipsFI->setSRetReturnReg(Reg);
2769 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
2770 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2776 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
2778 // All stores are grouped in one node to allow the matching between
2779 // the size of Ins and InVals. This only happens when on varg functions
2780 if (!OutChains.empty()) {
2781 OutChains.push_back(Chain);
2782 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
2788 //===----------------------------------------------------------------------===//
2789 // Return Value Calling Convention Implementation
2790 //===----------------------------------------------------------------------===//
2793 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2794 MachineFunction &MF, bool IsVarArg,
2795 const SmallVectorImpl<ISD::OutputArg> &Outs,
2796 LLVMContext &Context) const {
2797 SmallVector<CCValAssign, 16> RVLocs;
2798 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
2800 return CCInfo.CheckReturn(Outs, RetCC_Mips);
2804 MipsTargetLowering::LowerReturn(SDValue Chain,
2805 CallingConv::ID CallConv, bool IsVarArg,
2806 const SmallVectorImpl<ISD::OutputArg> &Outs,
2807 const SmallVectorImpl<SDValue> &OutVals,
2808 SDLoc DL, SelectionDAG &DAG) const {
2809 // CCValAssign - represent the assignment of
2810 // the return value to a location
2811 SmallVector<CCValAssign, 16> RVLocs;
2812 MachineFunction &MF = DAG.getMachineFunction();
2814 // CCState - Info about the registers and stack slot.
2815 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
2817 MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
2820 // Analyze return values.
2821 MipsCCInfo.analyzeReturn(Outs, Subtarget.abiUsesSoftFloat(),
2822 MF.getFunction()->getReturnType());
2825 SmallVector<SDValue, 4> RetOps(1, Chain);
2827 // Copy the result values into the output registers.
2828 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2829 SDValue Val = OutVals[i];
2830 CCValAssign &VA = RVLocs[i];
2831 assert(VA.isRegLoc() && "Can only return in registers!");
2833 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2834 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
2836 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
2838 // Guarantee that all emitted copies are stuck together with flags.
2839 Flag = Chain.getValue(1);
2840 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2843 // The mips ABIs for returning structs by value requires that we copy
2844 // the sret argument into $v0 for the return. We saved the argument into
2845 // a virtual register in the entry block, so now we copy the value out
2847 if (MF.getFunction()->hasStructRetAttr()) {
2848 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2849 unsigned Reg = MipsFI->getSRetReturnReg();
2852 llvm_unreachable("sret virtual register not created in the entry block");
2853 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
2854 unsigned V0 = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
2856 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
2857 Flag = Chain.getValue(1);
2858 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
2861 RetOps[0] = Chain; // Update chain.
2863 // Add the flag if we have it.
2865 RetOps.push_back(Flag);
2867 // Return on Mips is always a "jr $ra"
2868 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
2871 //===----------------------------------------------------------------------===//
2872 // Mips Inline Assembly Support
2873 //===----------------------------------------------------------------------===//
2875 /// getConstraintType - Given a constraint letter, return the type of
2876 /// constraint it is for this target.
2877 MipsTargetLowering::ConstraintType MipsTargetLowering::
2878 getConstraintType(const std::string &Constraint) const
2880 // Mips specific constraints
2881 // GCC config/mips/constraints.md
2883 // 'd' : An address register. Equivalent to r
2884 // unless generating MIPS16 code.
2885 // 'y' : Equivalent to r; retained for
2886 // backwards compatibility.
2887 // 'c' : A register suitable for use in an indirect
2888 // jump. This will always be $25 for -mabicalls.
2889 // 'l' : The lo register. 1 word storage.
2890 // 'x' : The hilo register pair. Double word storage.
2891 if (Constraint.size() == 1) {
2892 switch (Constraint[0]) {
2900 return C_RegisterClass;
2905 return TargetLowering::getConstraintType(Constraint);
2908 /// Examine constraint type and operand type and determine a weight value.
2909 /// This object must already have been set up with the operand type
2910 /// and the current alternative constraint selected.
2911 TargetLowering::ConstraintWeight
2912 MipsTargetLowering::getSingleConstraintMatchWeight(
2913 AsmOperandInfo &info, const char *constraint) const {
2914 ConstraintWeight weight = CW_Invalid;
2915 Value *CallOperandVal = info.CallOperandVal;
2916 // If we don't have a value, we can't do a match,
2917 // but allow it at the lowest weight.
2918 if (!CallOperandVal)
2920 Type *type = CallOperandVal->getType();
2921 // Look at the constraint type.
2922 switch (*constraint) {
2924 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2928 if (type->isIntegerTy())
2929 weight = CW_Register;
2931 case 'f': // FPU or MSA register
2932 if (Subtarget.hasMSA() && type->isVectorTy() &&
2933 cast<VectorType>(type)->getBitWidth() == 128)
2934 weight = CW_Register;
2935 else if (type->isFloatTy())
2936 weight = CW_Register;
2938 case 'c': // $25 for indirect jumps
2939 case 'l': // lo register
2940 case 'x': // hilo register pair
2941 if (type->isIntegerTy())
2942 weight = CW_SpecificReg;
2944 case 'I': // signed 16 bit immediate
2945 case 'J': // integer zero
2946 case 'K': // unsigned 16 bit immediate
2947 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2948 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2949 case 'O': // signed 15 bit immediate (+- 16383)
2950 case 'P': // immediate in the range of 65535 to 1 (inclusive)
2951 if (isa<ConstantInt>(CallOperandVal))
2952 weight = CW_Constant;
2961 /// This is a helper function to parse a physical register string and split it
2962 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
2963 /// that is returned indicates whether parsing was successful. The second flag
2964 /// is true if the numeric part exists.
2965 static std::pair<bool, bool>
2966 parsePhysicalReg(const StringRef &C, std::string &Prefix,
2967 unsigned long long &Reg) {
2968 if (C.front() != '{' || C.back() != '}')
2969 return std::make_pair(false, false);
2971 // Search for the first numeric character.
2972 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
2973 I = std::find_if(B, E, std::ptr_fun(isdigit));
2975 Prefix.assign(B, I - B);
2977 // The second flag is set to false if no numeric characters were found.
2979 return std::make_pair(true, false);
2981 // Parse the numeric characters.
2982 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
2986 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
2987 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
2988 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2989 const TargetRegisterClass *RC;
2991 unsigned long long Reg;
2993 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
2996 return std::make_pair(0U, nullptr);
2998 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
2999 // No numeric characters follow "hi" or "lo".
3001 return std::make_pair(0U, nullptr);
3003 RC = TRI->getRegClass(Prefix == "hi" ?
3004 Mips::HI32RegClassID : Mips::LO32RegClassID);
3005 return std::make_pair(*(RC->begin()), RC);
3006 } else if (Prefix.compare(0, 4, "$msa") == 0) {
3007 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3009 // No numeric characters follow the name.
3011 return std::make_pair(0U, nullptr);
3013 Reg = StringSwitch<unsigned long long>(Prefix)
3014 .Case("$msair", Mips::MSAIR)
3015 .Case("$msacsr", Mips::MSACSR)
3016 .Case("$msaaccess", Mips::MSAAccess)
3017 .Case("$msasave", Mips::MSASave)
3018 .Case("$msamodify", Mips::MSAModify)
3019 .Case("$msarequest", Mips::MSARequest)
3020 .Case("$msamap", Mips::MSAMap)
3021 .Case("$msaunmap", Mips::MSAUnmap)
3025 return std::make_pair(0U, nullptr);
3027 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3028 return std::make_pair(Reg, RC);
3032 return std::make_pair(0U, nullptr);
3034 if (Prefix == "$f") { // Parse $f0-$f31.
3035 // If the size of FP registers is 64-bit or Reg is an even number, select
3036 // the 64-bit register class. Otherwise, select the 32-bit register class.
3037 if (VT == MVT::Other)
3038 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3040 RC = getRegClassFor(VT);
3042 if (RC == &Mips::AFGR64RegClass) {
3043 assert(Reg % 2 == 0);
3046 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3047 RC = TRI->getRegClass(Mips::FCCRegClassID);
3048 else if (Prefix == "$w") { // Parse $w0-$w31.
3049 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3050 } else { // Parse $0-$31.
3051 assert(Prefix == "$");
3052 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3055 assert(Reg < RC->getNumRegs());
3056 return std::make_pair(*(RC->begin() + Reg), RC);
3059 /// Given a register class constraint, like 'r', if this corresponds directly
3060 /// to an LLVM register class, return a register of 0 and the register class
3062 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3063 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
3065 if (Constraint.size() == 1) {
3066 switch (Constraint[0]) {
3067 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3068 case 'y': // Same as 'r'. Exists for compatibility.
3070 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3071 if (Subtarget.inMips16Mode())
3072 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3073 return std::make_pair(0U, &Mips::GPR32RegClass);
3075 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3076 return std::make_pair(0U, &Mips::GPR32RegClass);
3077 if (VT == MVT::i64 && Subtarget.isGP64bit())
3078 return std::make_pair(0U, &Mips::GPR64RegClass);
3079 // This will generate an error message
3080 return std::make_pair(0U, nullptr);
3081 case 'f': // FPU or MSA register
3082 if (VT == MVT::v16i8)
3083 return std::make_pair(0U, &Mips::MSA128BRegClass);
3084 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3085 return std::make_pair(0U, &Mips::MSA128HRegClass);
3086 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3087 return std::make_pair(0U, &Mips::MSA128WRegClass);
3088 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3089 return std::make_pair(0U, &Mips::MSA128DRegClass);
3090 else if (VT == MVT::f32)
3091 return std::make_pair(0U, &Mips::FGR32RegClass);
3092 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3093 if (Subtarget.isFP64bit())
3094 return std::make_pair(0U, &Mips::FGR64RegClass);
3095 return std::make_pair(0U, &Mips::AFGR64RegClass);
3098 case 'c': // register suitable for indirect jump
3100 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3101 assert(VT == MVT::i64 && "Unexpected type.");
3102 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3103 case 'l': // register suitable for indirect jump
3105 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3106 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3107 case 'x': // register suitable for indirect jump
3108 // Fixme: Not triggering the use of both hi and low
3109 // This will generate an error message
3110 return std::make_pair(0U, nullptr);
3114 std::pair<unsigned, const TargetRegisterClass *> R;
3115 R = parseRegForInlineAsmConstraint(Constraint, VT);
3120 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3123 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3124 /// vector. If it is invalid, don't add anything to Ops.
3125 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3126 std::string &Constraint,
3127 std::vector<SDValue>&Ops,
3128 SelectionDAG &DAG) const {
3131 // Only support length 1 constraints for now.
3132 if (Constraint.length() > 1) return;
3134 char ConstraintLetter = Constraint[0];
3135 switch (ConstraintLetter) {
3136 default: break; // This will fall through to the generic implementation
3137 case 'I': // Signed 16 bit constant
3138 // If this fails, the parent routine will give an error
3139 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3140 EVT Type = Op.getValueType();
3141 int64_t Val = C->getSExtValue();
3142 if (isInt<16>(Val)) {
3143 Result = DAG.getTargetConstant(Val, Type);
3148 case 'J': // integer zero
3149 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3150 EVT Type = Op.getValueType();
3151 int64_t Val = C->getZExtValue();
3153 Result = DAG.getTargetConstant(0, Type);
3158 case 'K': // unsigned 16 bit immediate
3159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3160 EVT Type = Op.getValueType();
3161 uint64_t Val = (uint64_t)C->getZExtValue();
3162 if (isUInt<16>(Val)) {
3163 Result = DAG.getTargetConstant(Val, Type);
3168 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3170 EVT Type = Op.getValueType();
3171 int64_t Val = C->getSExtValue();
3172 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3173 Result = DAG.getTargetConstant(Val, Type);
3178 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3180 EVT Type = Op.getValueType();
3181 int64_t Val = C->getSExtValue();
3182 if ((Val >= -65535) && (Val <= -1)) {
3183 Result = DAG.getTargetConstant(Val, Type);
3188 case 'O': // signed 15 bit immediate
3189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3190 EVT Type = Op.getValueType();
3191 int64_t Val = C->getSExtValue();
3192 if ((isInt<15>(Val))) {
3193 Result = DAG.getTargetConstant(Val, Type);
3198 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3199 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3200 EVT Type = Op.getValueType();
3201 int64_t Val = C->getSExtValue();
3202 if ((Val <= 65535) && (Val >= 1)) {
3203 Result = DAG.getTargetConstant(Val, Type);
3210 if (Result.getNode()) {
3211 Ops.push_back(Result);
3215 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3218 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3220 // No global is ever allowed as a base.
3225 case 0: // "r+i" or just "i", depending on HasBaseReg.
3228 if (!AM.HasBaseReg) // allow "r+i".
3230 return false; // disallow "r+r" or "r+r+i".
3239 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3240 // The Mips target isn't yet aware of offsets.
3244 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3246 bool IsMemset, bool ZeroMemset,
3248 MachineFunction &MF) const {
3249 if (Subtarget.hasMips64())
3255 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3256 if (VT != MVT::f32 && VT != MVT::f64)
3258 if (Imm.isNegZero())
3260 return Imm.isZero();
3263 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3264 if (Subtarget.isABI_N64())
3265 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3267 return TargetLowering::getJumpTableEncoding();
3270 /// This function returns true if CallSym is a long double emulation routine.
3271 static bool isF128SoftLibCall(const char *CallSym) {
3272 const char *const LibCalls[] =
3273 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
3274 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
3275 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
3276 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
3277 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
3278 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
3279 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
3280 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
3283 const char *const *End = LibCalls + array_lengthof(LibCalls);
3285 // Check that LibCalls is sorted alphabetically.
3286 MipsTargetLowering::LTStr Comp;
3289 for (const char *const *I = LibCalls; I < End - 1; ++I)
3290 assert(Comp(*I, *(I + 1)));
3293 return std::binary_search(LibCalls, End, CallSym, Comp);
3296 /// This function returns true if Ty is fp128 or i128 which was originally a
3298 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
3299 if (Ty->isFP128Ty())
3302 const ExternalSymbolSDNode *ES =
3303 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
3305 // If the Ty is i128 and the function being called is a long double emulation
3306 // routine, then the original type is f128.
3307 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
3310 MipsTargetLowering::MipsCC::SpecialCallingConvType
3311 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
3312 MipsCC::SpecialCallingConvType SpecialCallingConv =
3313 MipsCC::NoSpecialCallingConv;
3314 if (Subtarget.inMips16HardFloat()) {
3315 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3316 llvm::StringRef Sym = G->getGlobal()->getName();
3317 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3318 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
3319 SpecialCallingConv = MipsCC::Mips16RetHelperConv;
3323 return SpecialCallingConv;
3326 MipsTargetLowering::MipsCC::MipsCC(
3327 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
3328 MipsCC::SpecialCallingConvType SpecialCallingConv_)
3329 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
3330 SpecialCallingConv(SpecialCallingConv_){
3331 // Pre-allocate reserved argument area.
3332 CCInfo.AllocateStack(reservedArgArea(), 1);
3336 void MipsTargetLowering::MipsCC::
3337 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3338 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
3339 std::vector<ArgListEntry> &FuncArgs) {
3340 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
3341 "CallingConv::Fast shouldn't be used for vararg functions.");
3343 unsigned NumOpnds = Args.size();
3344 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
3346 for (unsigned I = 0; I != NumOpnds; ++I) {
3347 MVT ArgVT = Args[I].VT;
3348 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3351 if (ArgFlags.isByVal()) {
3352 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3356 if (IsVarArg && !Args[I].IsFixed)
3357 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3359 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
3361 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
3366 dbgs() << "Call operand #" << I << " has unhandled type "
3367 << EVT(ArgVT).getEVTString();
3369 llvm_unreachable(nullptr);
3374 void MipsTargetLowering::MipsCC::
3375 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3376 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
3377 unsigned NumArgs = Args.size();
3378 llvm::CCAssignFn *FixedFn = fixedArgFn();
3379 unsigned CurArgIdx = 0;
3381 for (unsigned I = 0; I != NumArgs; ++I) {
3382 MVT ArgVT = Args[I].VT;
3383 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3384 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
3385 CurArgIdx = Args[I].OrigArgIndex;
3387 if (ArgFlags.isByVal()) {
3388 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3392 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), nullptr, IsSoftFloat);
3394 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
3398 dbgs() << "Formal Arg #" << I << " has unhandled type "
3399 << EVT(ArgVT).getEVTString();
3401 llvm_unreachable(nullptr);
3405 template<typename Ty>
3406 void MipsTargetLowering::MipsCC::
3407 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
3408 const SDNode *CallNode, const Type *RetTy) const {
3411 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
3412 Fn = RetCC_F128Soft;
3416 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
3417 MVT VT = RetVals[I].VT;
3418 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3419 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
3421 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
3423 dbgs() << "Call result #" << I << " has unhandled type "
3424 << EVT(VT).getEVTString() << '\n';
3426 llvm_unreachable(nullptr);
3431 void MipsTargetLowering::MipsCC::
3432 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3433 const SDNode *CallNode, const Type *RetTy) const {
3434 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
3437 void MipsTargetLowering::MipsCC::
3438 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3439 const Type *RetTy) const {
3440 analyzeReturn(Outs, IsSoftFloat, nullptr, RetTy);
3443 void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3445 CCValAssign::LocInfo LocInfo,
3446 ISD::ArgFlagsTy ArgFlags) {
3447 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3449 struct ByValArgInfo ByVal;
3450 unsigned RegSize = regSize();
3451 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3452 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3455 if (useRegsForByval())
3456 allocateRegs(ByVal, ByValSize, Align);
3458 // Allocate space on caller's stack.
3459 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3461 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3463 ByValArgs.push_back(ByVal);
3466 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
3467 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
3470 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
3471 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
3474 const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const {
3475 return IsO32 ? O32IntRegs : Mips64IntRegs;
3478 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
3479 if (CallConv == CallingConv::Fast)
3480 return CC_Mips_FastCC;
3482 if (SpecialCallingConv == Mips16RetHelperConv)
3483 return CC_Mips16RetHelper;
3484 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN;
3487 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
3488 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
3491 const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const {
3492 return IsO32 ? O32IntRegs : Mips64DPRegs;
3495 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3498 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
3499 const MCPhysReg *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
3500 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3501 "Byval argument's size and alignment should be a multiple of"
3504 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3506 // If Align > RegSize, the first arg register must be even.
3507 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3508 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3512 // Mark the registers allocated.
3513 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3514 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3515 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3518 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
3519 const SDNode *CallNode,
3520 bool IsSoftFloat) const {
3521 if (IsSoftFloat || IsO32)
3524 // Check if the original type was fp128.
3525 if (originalTypeIsF128(OrigTy, CallNode)) {
3526 assert(VT == MVT::i64);
3533 void MipsTargetLowering::
3534 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
3535 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3536 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3537 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3538 MachineFunction &MF = DAG.getMachineFunction();
3539 MachineFrameInfo *MFI = MF.getFrameInfo();
3540 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3541 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3545 FrameObjOffset = (int)CC.reservedArgArea() -
3546 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3548 FrameObjOffset = ByVal.Address;
3550 // Create frame object.
3551 EVT PtrTy = getPointerTy();
3552 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3553 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3554 InVals.push_back(FIN);
3559 // Copy arg registers.
3560 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3561 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3563 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3564 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3565 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3566 unsigned Offset = I * CC.regSize();
3567 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3568 DAG.getConstant(Offset, PtrTy));
3569 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3570 StorePtr, MachinePointerInfo(FuncArg, Offset),
3572 OutChains.push_back(Store);
3576 // Copy byVal arg to registers and stack.
3577 void MipsTargetLowering::
3578 passByValArg(SDValue Chain, SDLoc DL,
3579 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
3580 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3581 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3582 const MipsCC &CC, const ByValArgInfo &ByVal,
3583 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3584 unsigned ByValSizeInBytes = Flags.getByValSize();
3585 unsigned OffsetInBytes = 0; // From beginning of struct
3586 unsigned RegSizeInBytes = CC.regSize();
3587 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3588 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3590 if (ByVal.NumRegs) {
3591 const MCPhysReg *ArgRegs = CC.intArgRegs();
3592 bool LeftoverBytes = (ByVal.NumRegs * RegSizeInBytes > ByValSizeInBytes);
3595 // Copy words to registers.
3596 for (; I < ByVal.NumRegs - LeftoverBytes;
3597 ++I, OffsetInBytes += RegSizeInBytes) {
3598 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3599 DAG.getConstant(OffsetInBytes, PtrTy));
3600 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3601 MachinePointerInfo(), false, false, false,
3603 MemOpChains.push_back(LoadVal.getValue(1));
3604 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3605 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3608 // Return if the struct has been fully copied.
3609 if (ByValSizeInBytes == OffsetInBytes)
3612 // Copy the remainder of the byval argument with sub-word loads and shifts.
3613 if (LeftoverBytes) {
3614 assert((ByValSizeInBytes > OffsetInBytes) &&
3615 (ByValSizeInBytes < OffsetInBytes + RegSizeInBytes) &&
3616 "Size of the remainder should be smaller than RegSizeInBytes.");
3619 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3620 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3621 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3623 if (RemainingSizeInBytes < LoadSizeInBytes)
3627 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3628 DAG.getConstant(OffsetInBytes, PtrTy));
3629 SDValue LoadVal = DAG.getExtLoad(
3630 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3631 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, Alignment);
3632 MemOpChains.push_back(LoadVal.getValue(1));
3634 // Shift the loaded value.
3638 Shamt = TotalBytesLoaded * 8;
3640 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3642 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3643 DAG.getConstant(Shamt, MVT::i32));
3646 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3650 OffsetInBytes += LoadSizeInBytes;
3651 TotalBytesLoaded += LoadSizeInBytes;
3652 Alignment = std::min(Alignment, LoadSizeInBytes);
3655 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3656 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3661 // Copy remainder of byval arg to it with memcpy.
3662 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3663 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3664 DAG.getConstant(OffsetInBytes, PtrTy));
3665 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3666 DAG.getIntPtrConstant(ByVal.Address));
3667 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
3668 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3669 MachinePointerInfo(), MachinePointerInfo());
3670 MemOpChains.push_back(Chain);
3673 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3674 const MipsCC &CC, SDValue Chain,
3675 SDLoc DL, SelectionDAG &DAG) const {
3676 unsigned NumRegs = CC.numIntArgRegs();
3677 const MCPhysReg *ArgRegs = CC.intArgRegs();
3678 const CCState &CCInfo = CC.getCCInfo();
3679 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3680 unsigned RegSize = CC.regSize();
3681 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
3682 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3683 MachineFunction &MF = DAG.getMachineFunction();
3684 MachineFrameInfo *MFI = MF.getFrameInfo();
3685 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3687 // Offset of the first variable argument from stack pointer.
3691 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3693 VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3695 // Record the frame index of the first variable argument
3696 // which is a value necessary to VASTART.
3697 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3698 MipsFI->setVarArgsFrameIndex(FI);
3700 // Copy the integer registers that have not been used for argument passing
3701 // to the argument register save area. For O32, the save area is allocated
3702 // in the caller's stack frame, while for N32/64, it is allocated in the
3703 // callee's stack frame.
3704 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3705 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3706 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3707 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3708 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3709 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3710 MachinePointerInfo(), false, false, 0);
3711 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3713 OutChains.push_back(Store);