1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #include "MipsISelLowering.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsCCState.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/CodeGen/ValueTypes.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "mips-lower"
45 STATISTIC(NumTailCalls, "Number of tail calls");
48 LargeGOT("mxgot", cl::Hidden,
49 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
52 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
53 cl::desc("MIPS: Don't trap on integer division by zero."),
57 EnableMipsFastISel("mips-fast-isel", cl::Hidden,
58 cl::desc("Allow mips-fast-isel to be used"),
61 static const MCPhysReg Mips64DPRegs[8] = {
62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
66 // If I is a shifted mask, set the size (Size) and the first bit of the
67 // mask (Pos), and return true.
68 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
69 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
70 if (!isShiftedMask_64(I))
73 Size = CountPopulation_64(I);
74 Pos = countTrailingZeros(I);
78 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
83 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
85 unsigned Flag) const {
86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
89 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
91 unsigned Flag) const {
92 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
95 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
97 unsigned Flag) const {
98 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
101 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
103 unsigned Flag) const {
104 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
107 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
109 unsigned Flag) const {
110 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
111 N->getOffset(), Flag);
114 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
116 case MipsISD::JmpLink: return "MipsISD::JmpLink";
117 case MipsISD::TailCall: return "MipsISD::TailCall";
118 case MipsISD::Hi: return "MipsISD::Hi";
119 case MipsISD::Lo: return "MipsISD::Lo";
120 case MipsISD::GPRel: return "MipsISD::GPRel";
121 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
122 case MipsISD::Ret: return "MipsISD::Ret";
123 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
124 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
125 case MipsISD::FPCmp: return "MipsISD::FPCmp";
126 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
127 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
128 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
129 case MipsISD::MFHI: return "MipsISD::MFHI";
130 case MipsISD::MFLO: return "MipsISD::MFLO";
131 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
132 case MipsISD::Mult: return "MipsISD::Mult";
133 case MipsISD::Multu: return "MipsISD::Multu";
134 case MipsISD::MAdd: return "MipsISD::MAdd";
135 case MipsISD::MAddu: return "MipsISD::MAddu";
136 case MipsISD::MSub: return "MipsISD::MSub";
137 case MipsISD::MSubu: return "MipsISD::MSubu";
138 case MipsISD::DivRem: return "MipsISD::DivRem";
139 case MipsISD::DivRemU: return "MipsISD::DivRemU";
140 case MipsISD::DivRem16: return "MipsISD::DivRem16";
141 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
142 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
143 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
144 case MipsISD::Wrapper: return "MipsISD::Wrapper";
145 case MipsISD::Sync: return "MipsISD::Sync";
146 case MipsISD::Ext: return "MipsISD::Ext";
147 case MipsISD::Ins: return "MipsISD::Ins";
148 case MipsISD::LWL: return "MipsISD::LWL";
149 case MipsISD::LWR: return "MipsISD::LWR";
150 case MipsISD::SWL: return "MipsISD::SWL";
151 case MipsISD::SWR: return "MipsISD::SWR";
152 case MipsISD::LDL: return "MipsISD::LDL";
153 case MipsISD::LDR: return "MipsISD::LDR";
154 case MipsISD::SDL: return "MipsISD::SDL";
155 case MipsISD::SDR: return "MipsISD::SDR";
156 case MipsISD::EXTP: return "MipsISD::EXTP";
157 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
158 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
159 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
160 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
161 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
162 case MipsISD::SHILO: return "MipsISD::SHILO";
163 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
164 case MipsISD::MULT: return "MipsISD::MULT";
165 case MipsISD::MULTU: return "MipsISD::MULTU";
166 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
167 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
168 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
169 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
170 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
171 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
172 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
173 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
174 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
175 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
176 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
177 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
178 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
179 case MipsISD::VCEQ: return "MipsISD::VCEQ";
180 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
181 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
182 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
183 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
184 case MipsISD::VSMAX: return "MipsISD::VSMAX";
185 case MipsISD::VSMIN: return "MipsISD::VSMIN";
186 case MipsISD::VUMAX: return "MipsISD::VUMAX";
187 case MipsISD::VUMIN: return "MipsISD::VUMIN";
188 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
189 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
190 case MipsISD::VNOR: return "MipsISD::VNOR";
191 case MipsISD::VSHF: return "MipsISD::VSHF";
192 case MipsISD::SHF: return "MipsISD::SHF";
193 case MipsISD::ILVEV: return "MipsISD::ILVEV";
194 case MipsISD::ILVOD: return "MipsISD::ILVOD";
195 case MipsISD::ILVL: return "MipsISD::ILVL";
196 case MipsISD::ILVR: return "MipsISD::ILVR";
197 case MipsISD::PCKEV: return "MipsISD::PCKEV";
198 case MipsISD::PCKOD: return "MipsISD::PCKOD";
199 case MipsISD::INSVE: return "MipsISD::INSVE";
200 default: return nullptr;
204 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
205 const MipsSubtarget &STI)
206 : TargetLowering(TM), Subtarget(STI) {
207 // Mips does not have i1 type, so use i32 for
208 // setcc operations results (slt, sgt, ...).
209 setBooleanContents(ZeroOrOneBooleanContent);
210 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
211 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
212 // does. Integer booleans still use 0 and 1.
213 if (Subtarget.hasMips32r6())
214 setBooleanContents(ZeroOrOneBooleanContent,
215 ZeroOrNegativeOneBooleanContent);
217 // Load extented operations for i1 types must be promoted
218 for (MVT VT : MVT::integer_valuetypes()) {
219 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
220 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
221 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
224 // MIPS doesn't have extending float->double load/store
225 for (MVT VT : MVT::fp_valuetypes())
226 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
227 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
229 // Used by legalize types to correctly generate the setcc result.
230 // Without this, every float setcc comes with a AND/OR with the result,
231 // we don't want this, since the fpcmp result goes to a flag register,
232 // which is used implicitly by brcond and select operations.
233 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
235 // Mips Custom Operations
236 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
237 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
238 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242 setOperationAction(ISD::SELECT, MVT::f32, Custom);
243 setOperationAction(ISD::SELECT, MVT::f64, Custom);
244 setOperationAction(ISD::SELECT, MVT::i32, Custom);
245 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
246 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
247 setOperationAction(ISD::SETCC, MVT::f32, Custom);
248 setOperationAction(ISD::SETCC, MVT::f64, Custom);
249 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
250 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
251 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
252 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
254 if (Subtarget.isGP64bit()) {
255 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
256 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
257 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
258 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
259 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
260 setOperationAction(ISD::SELECT, MVT::i64, Custom);
261 setOperationAction(ISD::LOAD, MVT::i64, Custom);
262 setOperationAction(ISD::STORE, MVT::i64, Custom);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
264 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
265 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
266 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
269 if (!Subtarget.isGP64bit()) {
270 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
271 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
272 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
275 setOperationAction(ISD::ADD, MVT::i32, Custom);
276 if (Subtarget.isGP64bit())
277 setOperationAction(ISD::ADD, MVT::i64, Custom);
279 setOperationAction(ISD::SDIV, MVT::i32, Expand);
280 setOperationAction(ISD::SREM, MVT::i32, Expand);
281 setOperationAction(ISD::UDIV, MVT::i32, Expand);
282 setOperationAction(ISD::UREM, MVT::i32, Expand);
283 setOperationAction(ISD::SDIV, MVT::i64, Expand);
284 setOperationAction(ISD::SREM, MVT::i64, Expand);
285 setOperationAction(ISD::UDIV, MVT::i64, Expand);
286 setOperationAction(ISD::UREM, MVT::i64, Expand);
288 // Operations not directly supported by Mips.
289 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
290 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
291 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
292 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
293 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
294 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
295 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
296 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
297 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
298 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
299 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
300 if (Subtarget.hasCnMips()) {
301 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
302 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
304 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
305 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
307 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
308 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
309 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
310 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
311 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
312 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
313 setOperationAction(ISD::ROTL, MVT::i32, Expand);
314 setOperationAction(ISD::ROTL, MVT::i64, Expand);
315 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
316 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
318 if (!Subtarget.hasMips32r2())
319 setOperationAction(ISD::ROTR, MVT::i32, Expand);
321 if (!Subtarget.hasMips64r2())
322 setOperationAction(ISD::ROTR, MVT::i64, Expand);
324 setOperationAction(ISD::FSIN, MVT::f32, Expand);
325 setOperationAction(ISD::FSIN, MVT::f64, Expand);
326 setOperationAction(ISD::FCOS, MVT::f32, Expand);
327 setOperationAction(ISD::FCOS, MVT::f64, Expand);
328 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
329 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
330 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
331 setOperationAction(ISD::FPOW, MVT::f32, Expand);
332 setOperationAction(ISD::FPOW, MVT::f64, Expand);
333 setOperationAction(ISD::FLOG, MVT::f32, Expand);
334 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
335 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
336 setOperationAction(ISD::FEXP, MVT::f32, Expand);
337 setOperationAction(ISD::FMA, MVT::f32, Expand);
338 setOperationAction(ISD::FMA, MVT::f64, Expand);
339 setOperationAction(ISD::FREM, MVT::f32, Expand);
340 setOperationAction(ISD::FREM, MVT::f64, Expand);
342 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
344 setOperationAction(ISD::VASTART, MVT::Other, Custom);
345 setOperationAction(ISD::VAARG, MVT::Other, Custom);
346 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
347 setOperationAction(ISD::VAEND, MVT::Other, Expand);
349 // Use the default for now
350 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
351 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
353 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
354 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
355 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
356 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
358 setInsertFencesForAtomic(true);
360 if (!Subtarget.hasMips32r2()) {
361 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
362 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
365 // MIPS16 lacks MIPS32's clz and clo instructions.
366 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
367 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
368 if (!Subtarget.hasMips64())
369 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
371 if (!Subtarget.hasMips32r2())
372 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
373 if (!Subtarget.hasMips64r2())
374 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
376 if (Subtarget.isGP64bit()) {
377 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
378 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
379 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
380 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
383 setOperationAction(ISD::TRAP, MVT::Other, Legal);
385 setTargetDAGCombine(ISD::SDIVREM);
386 setTargetDAGCombine(ISD::UDIVREM);
387 setTargetDAGCombine(ISD::SELECT);
388 setTargetDAGCombine(ISD::AND);
389 setTargetDAGCombine(ISD::OR);
390 setTargetDAGCombine(ISD::ADD);
392 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
394 // The arguments on the stack are defined in terms of 4-byte slots on O32
395 // and 8-byte slots on N32/N64.
396 setMinStackArgumentAlignment(
397 (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4);
399 setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64
402 setExceptionPointerRegister(Subtarget.isABI_N64() ? Mips::A0_64 : Mips::A0);
403 setExceptionSelectorRegister(Subtarget.isABI_N64() ? Mips::A1_64 : Mips::A1);
405 MaxStoresPerMemcpy = 16;
407 isMicroMips = Subtarget.inMicroMipsMode();
410 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
411 const MipsSubtarget &STI) {
412 if (STI.inMips16Mode())
413 return llvm::createMips16TargetLowering(TM, STI);
415 return llvm::createMipsSETargetLowering(TM, STI);
418 // Create a fast isel object.
420 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
421 const TargetLibraryInfo *libInfo) const {
422 if (!EnableMipsFastISel)
423 return TargetLowering::createFastISel(funcInfo, libInfo);
424 return Mips::createFastISel(funcInfo, libInfo);
427 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
430 return VT.changeVectorElementTypeToInteger();
433 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
434 TargetLowering::DAGCombinerInfo &DCI,
435 const MipsSubtarget &Subtarget) {
436 if (DCI.isBeforeLegalizeOps())
439 EVT Ty = N->getValueType(0);
440 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
441 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
442 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
446 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
447 N->getOperand(0), N->getOperand(1));
448 SDValue InChain = DAG.getEntryNode();
449 SDValue InGlue = DivRem;
452 if (N->hasAnyUseOfValue(0)) {
453 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
455 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
456 InChain = CopyFromLo.getValue(1);
457 InGlue = CopyFromLo.getValue(2);
461 if (N->hasAnyUseOfValue(1)) {
462 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
464 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
470 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
472 default: llvm_unreachable("Unknown fp condition code!");
474 case ISD::SETOEQ: return Mips::FCOND_OEQ;
475 case ISD::SETUNE: return Mips::FCOND_UNE;
477 case ISD::SETOLT: return Mips::FCOND_OLT;
479 case ISD::SETOGT: return Mips::FCOND_OGT;
481 case ISD::SETOLE: return Mips::FCOND_OLE;
483 case ISD::SETOGE: return Mips::FCOND_OGE;
484 case ISD::SETULT: return Mips::FCOND_ULT;
485 case ISD::SETULE: return Mips::FCOND_ULE;
486 case ISD::SETUGT: return Mips::FCOND_UGT;
487 case ISD::SETUGE: return Mips::FCOND_UGE;
488 case ISD::SETUO: return Mips::FCOND_UN;
489 case ISD::SETO: return Mips::FCOND_OR;
491 case ISD::SETONE: return Mips::FCOND_ONE;
492 case ISD::SETUEQ: return Mips::FCOND_UEQ;
497 /// This function returns true if the floating point conditional branches and
498 /// conditional moves which use condition code CC should be inverted.
499 static bool invertFPCondCodeUser(Mips::CondCode CC) {
500 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
503 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
504 "Illegal Condition Code");
509 // Creates and returns an FPCmp node from a setcc node.
510 // Returns Op if setcc is not a floating point comparison.
511 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
512 // must be a SETCC node
513 if (Op.getOpcode() != ISD::SETCC)
516 SDValue LHS = Op.getOperand(0);
518 if (!LHS.getValueType().isFloatingPoint())
521 SDValue RHS = Op.getOperand(1);
524 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
525 // node if necessary.
526 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
528 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
529 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
532 // Creates and returns a CMovFPT/F node.
533 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
534 SDValue False, SDLoc DL) {
535 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
536 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
537 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
539 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
540 True.getValueType(), True, FCC0, False, Cond);
543 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
544 TargetLowering::DAGCombinerInfo &DCI,
545 const MipsSubtarget &Subtarget) {
546 if (DCI.isBeforeLegalizeOps())
549 SDValue SetCC = N->getOperand(0);
551 if ((SetCC.getOpcode() != ISD::SETCC) ||
552 !SetCC.getOperand(0).getValueType().isInteger())
555 SDValue False = N->getOperand(2);
556 EVT FalseTy = False.getValueType();
558 if (!FalseTy.isInteger())
561 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
563 // If the RHS (False) is 0, we swap the order of the operands
564 // of ISD::SELECT (obviously also inverting the condition) so that we can
565 // take advantage of conditional moves using the $0 register.
567 // return (a != 0) ? x : 0;
575 if (!FalseC->getZExtValue()) {
576 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
577 SDValue True = N->getOperand(1);
579 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
580 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
582 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
585 // If both operands are integer constants there's a possibility that we
586 // can do some interesting optimizations.
587 SDValue True = N->getOperand(1);
588 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
590 if (!TrueC || !True.getValueType().isInteger())
593 // We'll also ignore MVT::i64 operands as this optimizations proves
594 // to be ineffective because of the required sign extensions as the result
595 // of a SETCC operator is always MVT::i32 for non-vector types.
596 if (True.getValueType() == MVT::i64)
599 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
601 // 1) (a < x) ? y : y-1
603 // addiu $reg2, $reg1, y-1
605 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
607 // 2) (a < x) ? y-1 : y
609 // xor $reg1, $reg1, 1
610 // addiu $reg2, $reg1, y-1
612 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
613 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
614 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
615 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
618 // Couldn't optimize.
622 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
623 TargetLowering::DAGCombinerInfo &DCI,
624 const MipsSubtarget &Subtarget) {
625 if (DCI.isBeforeLegalizeOps())
628 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
630 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
631 if (!FalseC || FalseC->getZExtValue())
634 // Since RHS (False) is 0, we swap the order of the True/False operands
635 // (obviously also inverting the condition) so that we can
636 // take advantage of conditional moves using the $0 register.
638 // return (a != 0) ? x : 0;
641 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
644 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
645 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
646 ValueIfFalse, FCC, ValueIfTrue, Glue);
649 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
650 TargetLowering::DAGCombinerInfo &DCI,
651 const MipsSubtarget &Subtarget) {
652 // Pattern match EXT.
653 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
654 // => ext $dst, $src, size, pos
655 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
658 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
659 unsigned ShiftRightOpc = ShiftRight.getOpcode();
661 // Op's first operand must be a shift right.
662 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
665 // The second operand of the shift must be an immediate.
667 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
670 uint64_t Pos = CN->getZExtValue();
671 uint64_t SMPos, SMSize;
673 // Op's second operand must be a shifted mask.
674 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
675 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
678 // Return if the shifted mask does not start at bit 0 or the sum of its size
679 // and Pos exceeds the word's size.
680 EVT ValTy = N->getValueType(0);
681 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
684 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
685 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
686 DAG.getConstant(SMSize, MVT::i32));
689 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
690 TargetLowering::DAGCombinerInfo &DCI,
691 const MipsSubtarget &Subtarget) {
692 // Pattern match INS.
693 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
694 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
695 // => ins $dst, $src, size, pos, $src1
696 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
699 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
700 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
703 // See if Op's first operand matches (and $src1 , mask0).
704 if (And0.getOpcode() != ISD::AND)
707 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
708 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
711 // See if Op's second operand matches (and (shl $src, pos), mask1).
712 if (And1.getOpcode() != ISD::AND)
715 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
716 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
719 // The shift masks must have the same position and size.
720 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
723 SDValue Shl = And1.getOperand(0);
724 if (Shl.getOpcode() != ISD::SHL)
727 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
730 unsigned Shamt = CN->getZExtValue();
732 // Return if the shift amount and the first bit position of mask are not the
734 EVT ValTy = N->getValueType(0);
735 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
738 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
739 DAG.getConstant(SMPos0, MVT::i32),
740 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
743 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
744 TargetLowering::DAGCombinerInfo &DCI,
745 const MipsSubtarget &Subtarget) {
746 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
748 if (DCI.isBeforeLegalizeOps())
751 SDValue Add = N->getOperand(1);
753 if (Add.getOpcode() != ISD::ADD)
756 SDValue Lo = Add.getOperand(1);
758 if ((Lo.getOpcode() != MipsISD::Lo) ||
759 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
762 EVT ValTy = N->getValueType(0);
765 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
767 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
770 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
772 SelectionDAG &DAG = DCI.DAG;
773 unsigned Opc = N->getOpcode();
779 return performDivRemCombine(N, DAG, DCI, Subtarget);
781 return performSELECTCombine(N, DAG, DCI, Subtarget);
782 case MipsISD::CMovFP_F:
783 case MipsISD::CMovFP_T:
784 return performCMovFPCombine(N, DAG, DCI, Subtarget);
786 return performANDCombine(N, DAG, DCI, Subtarget);
788 return performORCombine(N, DAG, DCI, Subtarget);
790 return performADDCombine(N, DAG, DCI, Subtarget);
797 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
798 SmallVectorImpl<SDValue> &Results,
799 SelectionDAG &DAG) const {
800 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
802 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
803 Results.push_back(Res.getValue(I));
807 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
808 SmallVectorImpl<SDValue> &Results,
809 SelectionDAG &DAG) const {
810 return LowerOperationWrapper(N, Results, DAG);
813 SDValue MipsTargetLowering::
814 LowerOperation(SDValue Op, SelectionDAG &DAG) const
816 switch (Op.getOpcode())
818 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
819 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
820 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
821 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
822 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
823 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
824 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
825 case ISD::SELECT: return lowerSELECT(Op, DAG);
826 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
827 case ISD::SETCC: return lowerSETCC(Op, DAG);
828 case ISD::VASTART: return lowerVASTART(Op, DAG);
829 case ISD::VAARG: return lowerVAARG(Op, DAG);
830 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
831 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
832 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
833 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
834 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
835 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
836 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
837 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
838 case ISD::LOAD: return lowerLOAD(Op, DAG);
839 case ISD::STORE: return lowerSTORE(Op, DAG);
840 case ISD::ADD: return lowerADD(Op, DAG);
841 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
846 //===----------------------------------------------------------------------===//
847 // Lower helper functions
848 //===----------------------------------------------------------------------===//
850 // addLiveIn - This helper function adds the specified physical register to the
851 // MachineFunction as a live in value. It also creates a corresponding
852 // virtual register for it.
854 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
856 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
857 MF.getRegInfo().addLiveIn(PReg, VReg);
861 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
862 MachineBasicBlock &MBB,
863 const TargetInstrInfo &TII,
868 // Insert instruction "teq $divisor_reg, $zero, 7".
869 MachineBasicBlock::iterator I(MI);
870 MachineInstrBuilder MIB;
871 MachineOperand &Divisor = MI->getOperand(2);
872 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
873 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
874 .addReg(Mips::ZERO).addImm(7);
876 // Use the 32-bit sub-register if this is a 64-bit division.
878 MIB->getOperand(0).setSubReg(Mips::sub_32);
880 // Clear Divisor's kill flag.
881 Divisor.setIsKill(false);
883 // We would normally delete the original instruction here but in this case
884 // we only needed to inject an additional instruction rather than replace it.
890 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
891 MachineBasicBlock *BB) const {
892 switch (MI->getOpcode()) {
894 llvm_unreachable("Unexpected instr type to insert");
895 case Mips::ATOMIC_LOAD_ADD_I8:
896 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
897 case Mips::ATOMIC_LOAD_ADD_I16:
898 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
899 case Mips::ATOMIC_LOAD_ADD_I32:
900 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
901 case Mips::ATOMIC_LOAD_ADD_I64:
902 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
904 case Mips::ATOMIC_LOAD_AND_I8:
905 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
906 case Mips::ATOMIC_LOAD_AND_I16:
907 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
908 case Mips::ATOMIC_LOAD_AND_I32:
909 return emitAtomicBinary(MI, BB, 4, Mips::AND);
910 case Mips::ATOMIC_LOAD_AND_I64:
911 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
913 case Mips::ATOMIC_LOAD_OR_I8:
914 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
915 case Mips::ATOMIC_LOAD_OR_I16:
916 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
917 case Mips::ATOMIC_LOAD_OR_I32:
918 return emitAtomicBinary(MI, BB, 4, Mips::OR);
919 case Mips::ATOMIC_LOAD_OR_I64:
920 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
922 case Mips::ATOMIC_LOAD_XOR_I8:
923 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
924 case Mips::ATOMIC_LOAD_XOR_I16:
925 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
926 case Mips::ATOMIC_LOAD_XOR_I32:
927 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
928 case Mips::ATOMIC_LOAD_XOR_I64:
929 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
931 case Mips::ATOMIC_LOAD_NAND_I8:
932 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
933 case Mips::ATOMIC_LOAD_NAND_I16:
934 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
935 case Mips::ATOMIC_LOAD_NAND_I32:
936 return emitAtomicBinary(MI, BB, 4, 0, true);
937 case Mips::ATOMIC_LOAD_NAND_I64:
938 return emitAtomicBinary(MI, BB, 8, 0, true);
940 case Mips::ATOMIC_LOAD_SUB_I8:
941 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
942 case Mips::ATOMIC_LOAD_SUB_I16:
943 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
944 case Mips::ATOMIC_LOAD_SUB_I32:
945 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
946 case Mips::ATOMIC_LOAD_SUB_I64:
947 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
949 case Mips::ATOMIC_SWAP_I8:
950 return emitAtomicBinaryPartword(MI, BB, 1, 0);
951 case Mips::ATOMIC_SWAP_I16:
952 return emitAtomicBinaryPartword(MI, BB, 2, 0);
953 case Mips::ATOMIC_SWAP_I32:
954 return emitAtomicBinary(MI, BB, 4, 0);
955 case Mips::ATOMIC_SWAP_I64:
956 return emitAtomicBinary(MI, BB, 8, 0);
958 case Mips::ATOMIC_CMP_SWAP_I8:
959 return emitAtomicCmpSwapPartword(MI, BB, 1);
960 case Mips::ATOMIC_CMP_SWAP_I16:
961 return emitAtomicCmpSwapPartword(MI, BB, 2);
962 case Mips::ATOMIC_CMP_SWAP_I32:
963 return emitAtomicCmpSwap(MI, BB, 4);
964 case Mips::ATOMIC_CMP_SWAP_I64:
965 return emitAtomicCmpSwap(MI, BB, 8);
966 case Mips::PseudoSDIV:
967 case Mips::PseudoUDIV:
972 return insertDivByZeroTrap(
973 MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), false);
974 case Mips::PseudoDSDIV:
975 case Mips::PseudoDUDIV:
980 return insertDivByZeroTrap(
981 MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), true);
983 return emitSEL_D(MI, BB);
985 case Mips::PseudoSELECT_I:
986 case Mips::PseudoSELECT_I64:
987 case Mips::PseudoSELECT_S:
988 case Mips::PseudoSELECT_D32:
989 case Mips::PseudoSELECT_D64:
990 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
991 case Mips::PseudoSELECTFP_F_I:
992 case Mips::PseudoSELECTFP_F_I64:
993 case Mips::PseudoSELECTFP_F_S:
994 case Mips::PseudoSELECTFP_F_D32:
995 case Mips::PseudoSELECTFP_F_D64:
996 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
997 case Mips::PseudoSELECTFP_T_I:
998 case Mips::PseudoSELECTFP_T_I64:
999 case Mips::PseudoSELECTFP_T_S:
1000 case Mips::PseudoSELECTFP_T_D32:
1001 case Mips::PseudoSELECTFP_T_D64:
1002 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1006 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1007 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1009 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1010 unsigned Size, unsigned BinOpcode,
1012 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1014 MachineFunction *MF = BB->getParent();
1015 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1016 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1017 const TargetInstrInfo *TII =
1018 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1019 DebugLoc DL = MI->getDebugLoc();
1020 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1027 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1028 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1035 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1036 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1039 ZERO = Mips::ZERO_64;
1043 unsigned OldVal = MI->getOperand(0).getReg();
1044 unsigned Ptr = MI->getOperand(1).getReg();
1045 unsigned Incr = MI->getOperand(2).getReg();
1047 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1048 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1049 unsigned Success = RegInfo.createVirtualRegister(RC);
1051 // insert new blocks after the current block
1052 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1053 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1054 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1055 MachineFunction::iterator It = BB;
1057 MF->insert(It, loopMBB);
1058 MF->insert(It, exitMBB);
1060 // Transfer the remainder of BB and its successor edges to exitMBB.
1061 exitMBB->splice(exitMBB->begin(), BB,
1062 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1063 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1067 // fallthrough --> loopMBB
1068 BB->addSuccessor(loopMBB);
1069 loopMBB->addSuccessor(loopMBB);
1070 loopMBB->addSuccessor(exitMBB);
1073 // ll oldval, 0(ptr)
1074 // <binop> storeval, oldval, incr
1075 // sc success, storeval, 0(ptr)
1076 // beq success, $0, loopMBB
1078 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1080 // and andres, oldval, incr
1081 // nor storeval, $0, andres
1082 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1083 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1084 } else if (BinOpcode) {
1085 // <binop> storeval, oldval, incr
1086 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1090 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1091 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1093 MI->eraseFromParent(); // The instruction is gone now.
1098 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1099 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1100 unsigned SrcReg) const {
1101 const TargetInstrInfo *TII =
1102 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1103 DebugLoc DL = MI->getDebugLoc();
1105 if (Subtarget.hasMips32r2() && Size == 1) {
1106 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1110 if (Subtarget.hasMips32r2() && Size == 2) {
1111 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1115 MachineFunction *MF = BB->getParent();
1116 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1117 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1118 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1121 int64_t ShiftImm = 32 - (Size * 8);
1123 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1124 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1129 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1130 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1132 assert((Size == 1 || Size == 2) &&
1133 "Unsupported size for EmitAtomicBinaryPartial.");
1135 MachineFunction *MF = BB->getParent();
1136 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1137 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1138 const TargetInstrInfo *TII =
1139 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1140 DebugLoc DL = MI->getDebugLoc();
1142 unsigned Dest = MI->getOperand(0).getReg();
1143 unsigned Ptr = MI->getOperand(1).getReg();
1144 unsigned Incr = MI->getOperand(2).getReg();
1146 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1147 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1148 unsigned Mask = RegInfo.createVirtualRegister(RC);
1149 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1150 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1151 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1152 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1153 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1154 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1155 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1156 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1157 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1158 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1159 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1160 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1161 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1162 unsigned Success = RegInfo.createVirtualRegister(RC);
1164 // insert new blocks after the current block
1165 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1166 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1167 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1168 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1169 MachineFunction::iterator It = BB;
1171 MF->insert(It, loopMBB);
1172 MF->insert(It, sinkMBB);
1173 MF->insert(It, exitMBB);
1175 // Transfer the remainder of BB and its successor edges to exitMBB.
1176 exitMBB->splice(exitMBB->begin(), BB,
1177 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1178 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1180 BB->addSuccessor(loopMBB);
1181 loopMBB->addSuccessor(loopMBB);
1182 loopMBB->addSuccessor(sinkMBB);
1183 sinkMBB->addSuccessor(exitMBB);
1186 // addiu masklsb2,$0,-4 # 0xfffffffc
1187 // and alignedaddr,ptr,masklsb2
1188 // andi ptrlsb2,ptr,3
1189 // sll shiftamt,ptrlsb2,3
1190 // ori maskupper,$0,255 # 0xff
1191 // sll mask,maskupper,shiftamt
1192 // nor mask2,$0,mask
1193 // sll incr2,incr,shiftamt
1195 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1196 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1197 .addReg(Mips::ZERO).addImm(-4);
1198 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1199 .addReg(Ptr).addReg(MaskLSB2);
1200 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1201 if (Subtarget.isLittle()) {
1202 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1204 unsigned Off = RegInfo.createVirtualRegister(RC);
1205 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1206 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1207 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1209 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1210 .addReg(Mips::ZERO).addImm(MaskImm);
1211 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1212 .addReg(MaskUpper).addReg(ShiftAmt);
1213 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1214 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1216 // atomic.load.binop
1218 // ll oldval,0(alignedaddr)
1219 // binop binopres,oldval,incr2
1220 // and newval,binopres,mask
1221 // and maskedoldval0,oldval,mask2
1222 // or storeval,maskedoldval0,newval
1223 // sc success,storeval,0(alignedaddr)
1224 // beq success,$0,loopMBB
1228 // ll oldval,0(alignedaddr)
1229 // and newval,incr2,mask
1230 // and maskedoldval0,oldval,mask2
1231 // or storeval,maskedoldval0,newval
1232 // sc success,storeval,0(alignedaddr)
1233 // beq success,$0,loopMBB
1236 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1237 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1239 // and andres, oldval, incr2
1240 // nor binopres, $0, andres
1241 // and newval, binopres, mask
1242 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1243 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1244 .addReg(Mips::ZERO).addReg(AndRes);
1245 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1246 } else if (BinOpcode) {
1247 // <binop> binopres, oldval, incr2
1248 // and newval, binopres, mask
1249 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1250 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1251 } else { // atomic.swap
1252 // and newval, incr2, mask
1253 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1256 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1257 .addReg(OldVal).addReg(Mask2);
1258 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1259 .addReg(MaskedOldVal0).addReg(NewVal);
1260 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1261 BuildMI(BB, DL, TII->get(SC), Success)
1262 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1263 BuildMI(BB, DL, TII->get(Mips::BEQ))
1264 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1267 // and maskedoldval1,oldval,mask
1268 // srl srlres,maskedoldval1,shiftamt
1269 // sign_extend dest,srlres
1272 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1273 .addReg(OldVal).addReg(Mask);
1274 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1275 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1276 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1278 MI->eraseFromParent(); // The instruction is gone now.
1283 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1284 MachineBasicBlock *BB,
1285 unsigned Size) const {
1286 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1288 MachineFunction *MF = BB->getParent();
1289 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1290 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1291 const TargetInstrInfo *TII =
1292 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1293 DebugLoc DL = MI->getDebugLoc();
1294 unsigned LL, SC, ZERO, BNE, BEQ;
1297 LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1298 SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1305 ZERO = Mips::ZERO_64;
1310 unsigned Dest = MI->getOperand(0).getReg();
1311 unsigned Ptr = MI->getOperand(1).getReg();
1312 unsigned OldVal = MI->getOperand(2).getReg();
1313 unsigned NewVal = MI->getOperand(3).getReg();
1315 unsigned Success = RegInfo.createVirtualRegister(RC);
1317 // insert new blocks after the current block
1318 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1319 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1320 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1321 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1322 MachineFunction::iterator It = BB;
1324 MF->insert(It, loop1MBB);
1325 MF->insert(It, loop2MBB);
1326 MF->insert(It, exitMBB);
1328 // Transfer the remainder of BB and its successor edges to exitMBB.
1329 exitMBB->splice(exitMBB->begin(), BB,
1330 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1331 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1335 // fallthrough --> loop1MBB
1336 BB->addSuccessor(loop1MBB);
1337 loop1MBB->addSuccessor(exitMBB);
1338 loop1MBB->addSuccessor(loop2MBB);
1339 loop2MBB->addSuccessor(loop1MBB);
1340 loop2MBB->addSuccessor(exitMBB);
1344 // bne dest, oldval, exitMBB
1346 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1347 BuildMI(BB, DL, TII->get(BNE))
1348 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1351 // sc success, newval, 0(ptr)
1352 // beq success, $0, loop1MBB
1354 BuildMI(BB, DL, TII->get(SC), Success)
1355 .addReg(NewVal).addReg(Ptr).addImm(0);
1356 BuildMI(BB, DL, TII->get(BEQ))
1357 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1359 MI->eraseFromParent(); // The instruction is gone now.
1365 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1366 MachineBasicBlock *BB,
1367 unsigned Size) const {
1368 assert((Size == 1 || Size == 2) &&
1369 "Unsupported size for EmitAtomicCmpSwapPartial.");
1371 MachineFunction *MF = BB->getParent();
1372 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1373 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1374 const TargetInstrInfo *TII =
1375 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1376 DebugLoc DL = MI->getDebugLoc();
1378 unsigned Dest = MI->getOperand(0).getReg();
1379 unsigned Ptr = MI->getOperand(1).getReg();
1380 unsigned CmpVal = MI->getOperand(2).getReg();
1381 unsigned NewVal = MI->getOperand(3).getReg();
1383 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1384 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1385 unsigned Mask = RegInfo.createVirtualRegister(RC);
1386 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1387 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1388 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1389 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1390 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1391 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1392 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1393 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1394 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1395 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1396 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1397 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1398 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1399 unsigned Success = RegInfo.createVirtualRegister(RC);
1401 // insert new blocks after the current block
1402 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1403 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1404 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1405 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1406 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1407 MachineFunction::iterator It = BB;
1409 MF->insert(It, loop1MBB);
1410 MF->insert(It, loop2MBB);
1411 MF->insert(It, sinkMBB);
1412 MF->insert(It, exitMBB);
1414 // Transfer the remainder of BB and its successor edges to exitMBB.
1415 exitMBB->splice(exitMBB->begin(), BB,
1416 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1417 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1419 BB->addSuccessor(loop1MBB);
1420 loop1MBB->addSuccessor(sinkMBB);
1421 loop1MBB->addSuccessor(loop2MBB);
1422 loop2MBB->addSuccessor(loop1MBB);
1423 loop2MBB->addSuccessor(sinkMBB);
1424 sinkMBB->addSuccessor(exitMBB);
1426 // FIXME: computation of newval2 can be moved to loop2MBB.
1428 // addiu masklsb2,$0,-4 # 0xfffffffc
1429 // and alignedaddr,ptr,masklsb2
1430 // andi ptrlsb2,ptr,3
1431 // sll shiftamt,ptrlsb2,3
1432 // ori maskupper,$0,255 # 0xff
1433 // sll mask,maskupper,shiftamt
1434 // nor mask2,$0,mask
1435 // andi maskedcmpval,cmpval,255
1436 // sll shiftedcmpval,maskedcmpval,shiftamt
1437 // andi maskednewval,newval,255
1438 // sll shiftednewval,maskednewval,shiftamt
1439 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1440 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1441 .addReg(Mips::ZERO).addImm(-4);
1442 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1443 .addReg(Ptr).addReg(MaskLSB2);
1444 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1445 if (Subtarget.isLittle()) {
1446 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1448 unsigned Off = RegInfo.createVirtualRegister(RC);
1449 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1450 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1451 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1453 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1454 .addReg(Mips::ZERO).addImm(MaskImm);
1455 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1456 .addReg(MaskUpper).addReg(ShiftAmt);
1457 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1458 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1459 .addReg(CmpVal).addImm(MaskImm);
1460 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1461 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1462 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1463 .addReg(NewVal).addImm(MaskImm);
1464 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1465 .addReg(MaskedNewVal).addReg(ShiftAmt);
1468 // ll oldval,0(alginedaddr)
1469 // and maskedoldval0,oldval,mask
1470 // bne maskedoldval0,shiftedcmpval,sinkMBB
1472 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1473 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1474 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1475 .addReg(OldVal).addReg(Mask);
1476 BuildMI(BB, DL, TII->get(Mips::BNE))
1477 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1480 // and maskedoldval1,oldval,mask2
1481 // or storeval,maskedoldval1,shiftednewval
1482 // sc success,storeval,0(alignedaddr)
1483 // beq success,$0,loop1MBB
1485 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1486 .addReg(OldVal).addReg(Mask2);
1487 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1488 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1489 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1490 BuildMI(BB, DL, TII->get(SC), Success)
1491 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1492 BuildMI(BB, DL, TII->get(Mips::BEQ))
1493 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1496 // srl srlres,maskedoldval0,shiftamt
1497 // sign_extend dest,srlres
1500 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1501 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1502 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1504 MI->eraseFromParent(); // The instruction is gone now.
1509 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
1510 MachineBasicBlock *BB) const {
1511 MachineFunction *MF = BB->getParent();
1512 const TargetRegisterInfo *TRI =
1513 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1514 const TargetInstrInfo *TII =
1515 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1516 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1517 DebugLoc DL = MI->getDebugLoc();
1518 MachineBasicBlock::iterator II(MI);
1520 unsigned Fc = MI->getOperand(1).getReg();
1521 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1523 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1525 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1528 .addImm(Mips::sub_lo);
1530 // We don't erase the original instruction, we just replace the condition
1531 // register with the 64-bit super-register.
1532 MI->getOperand(1).setReg(Fc2);
1537 //===----------------------------------------------------------------------===//
1538 // Misc Lower Operation implementation
1539 //===----------------------------------------------------------------------===//
1540 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1541 SDValue Chain = Op.getOperand(0);
1542 SDValue Table = Op.getOperand(1);
1543 SDValue Index = Op.getOperand(2);
1545 EVT PTy = getPointerTy();
1546 unsigned EntrySize =
1547 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1549 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1550 DAG.getConstant(EntrySize, PTy));
1551 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1553 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1554 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1555 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1557 Chain = Addr.getValue(1);
1559 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) ||
1560 Subtarget.isABI_N64()) {
1561 // For PIC, the sequence is:
1562 // BRIND(load(Jumptable + index) + RelocBase)
1563 // RelocBase can be JumpTable, GOT or some sort of global base.
1564 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1565 getPICJumpTableRelocBase(Table, DAG));
1568 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1571 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1572 // The first operand is the chain, the second is the condition, the third is
1573 // the block to branch to if the condition is true.
1574 SDValue Chain = Op.getOperand(0);
1575 SDValue Dest = Op.getOperand(2);
1578 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1579 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1581 // Return if flag is not set by a floating point comparison.
1582 if (CondRes.getOpcode() != MipsISD::FPCmp)
1585 SDValue CCNode = CondRes.getOperand(2);
1587 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1588 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1589 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1590 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1591 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1592 FCC0, Dest, CondRes);
1595 SDValue MipsTargetLowering::
1596 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1598 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1599 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1601 // Return if flag is not set by a floating point comparison.
1602 if (Cond.getOpcode() != MipsISD::FPCmp)
1605 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1609 SDValue MipsTargetLowering::
1610 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1613 EVT Ty = Op.getOperand(0).getValueType();
1614 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1615 getSetCCResultType(*DAG.getContext(), Ty),
1616 Op.getOperand(0), Op.getOperand(1),
1619 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1623 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1624 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1625 SDValue Cond = createFPCmp(DAG, Op);
1627 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1628 "Floating point operand expected.");
1630 SDValue True = DAG.getConstant(1, MVT::i32);
1631 SDValue False = DAG.getConstant(0, MVT::i32);
1633 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1636 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1637 SelectionDAG &DAG) const {
1638 EVT Ty = Op.getValueType();
1639 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1640 const GlobalValue *GV = N->getGlobal();
1642 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1643 !Subtarget.isABI_N64()) {
1644 const MipsTargetObjectFile &TLOF =
1645 (const MipsTargetObjectFile&)getObjFileLowering();
1647 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine()))
1648 // %gp_rel relocation
1649 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1651 // %hi/%lo relocation
1652 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1655 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1656 return getAddrLocal(N, SDLoc(N), Ty, DAG,
1657 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1660 return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16,
1661 MipsII::MO_GOT_LO16, DAG.getEntryNode(),
1662 MachinePointerInfo::getGOT());
1664 return getAddrGlobal(N, SDLoc(N), Ty, DAG,
1665 (Subtarget.isABI_N32() || Subtarget.isABI_N64())
1666 ? MipsII::MO_GOT_DISP
1668 DAG.getEntryNode(), MachinePointerInfo::getGOT());
1671 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1672 SelectionDAG &DAG) const {
1673 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1674 EVT Ty = Op.getValueType();
1676 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1677 !Subtarget.isABI_N64())
1678 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1680 return getAddrLocal(N, SDLoc(N), Ty, DAG,
1681 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1684 SDValue MipsTargetLowering::
1685 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1687 // If the relocation model is PIC, use the General Dynamic TLS Model or
1688 // Local Dynamic TLS model, otherwise use the Initial Exec or
1689 // Local Exec TLS Model.
1691 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1693 const GlobalValue *GV = GA->getGlobal();
1694 EVT PtrVT = getPointerTy();
1696 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1698 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1699 // General Dynamic and Local Dynamic TLS Model.
1700 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1703 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1704 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1705 getGlobalReg(DAG, PtrVT), TGA);
1706 unsigned PtrSize = PtrVT.getSizeInBits();
1707 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1709 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1713 Entry.Node = Argument;
1715 Args.push_back(Entry);
1717 TargetLowering::CallLoweringInfo CLI(DAG);
1718 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1719 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1720 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1722 SDValue Ret = CallResult.first;
1724 if (model != TLSModel::LocalDynamic)
1727 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1728 MipsII::MO_DTPREL_HI);
1729 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1730 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1731 MipsII::MO_DTPREL_LO);
1732 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1733 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1734 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1738 if (model == TLSModel::InitialExec) {
1739 // Initial Exec TLS Model
1740 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1741 MipsII::MO_GOTTPREL);
1742 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1744 Offset = DAG.getLoad(PtrVT, DL,
1745 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1746 false, false, false, 0);
1748 // Local Exec TLS Model
1749 assert(model == TLSModel::LocalExec);
1750 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1751 MipsII::MO_TPREL_HI);
1752 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1753 MipsII::MO_TPREL_LO);
1754 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1755 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1756 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1759 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1760 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1763 SDValue MipsTargetLowering::
1764 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1766 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1767 EVT Ty = Op.getValueType();
1769 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1770 !Subtarget.isABI_N64())
1771 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1773 return getAddrLocal(N, SDLoc(N), Ty, DAG,
1774 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1777 SDValue MipsTargetLowering::
1778 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1780 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1781 EVT Ty = Op.getValueType();
1783 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
1784 !Subtarget.isABI_N64()) {
1785 const MipsTargetObjectFile &TLOF =
1786 (const MipsTargetObjectFile&)getObjFileLowering();
1788 if (TLOF.IsConstantInSmallSection(N->getConstVal(), getTargetMachine()))
1789 // %gp_rel relocation
1790 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1792 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1795 return getAddrLocal(N, SDLoc(N), Ty, DAG,
1796 Subtarget.isABI_N32() || Subtarget.isABI_N64());
1799 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1800 MachineFunction &MF = DAG.getMachineFunction();
1801 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1804 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1807 // vastart just stores the address of the VarArgsFrameIndex slot into the
1808 // memory location argument.
1809 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1810 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1811 MachinePointerInfo(SV), false, false, 0);
1814 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1815 SDNode *Node = Op.getNode();
1816 EVT VT = Node->getValueType(0);
1817 SDValue Chain = Node->getOperand(0);
1818 SDValue VAListPtr = Node->getOperand(1);
1819 unsigned Align = Node->getConstantOperandVal(3);
1820 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1822 unsigned ArgSlotSizeInBytes =
1823 (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4;
1825 SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr,
1826 MachinePointerInfo(SV), false, false, false,
1828 SDValue VAList = VAListLoad;
1830 // Re-align the pointer if necessary.
1831 // It should only ever be necessary for 64-bit types on O32 since the minimum
1832 // argument alignment is the same as the maximum type alignment for N32/N64.
1834 // FIXME: We currently align too often. The code generator doesn't notice
1835 // when the pointer is still aligned from the last va_arg (or pair of
1836 // va_args for the i64 on O32 case).
1837 if (Align > getMinStackArgumentAlignment()) {
1838 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
1840 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1841 DAG.getConstant(Align - 1,
1842 VAList.getValueType()));
1844 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1845 DAG.getConstant(-(int64_t)Align,
1846 VAList.getValueType()));
1849 // Increment the pointer, VAList, to the next vaarg.
1850 unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1851 SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1852 DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
1853 VAList.getValueType()));
1854 // Store the incremented VAList to the legalized pointer
1855 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1856 MachinePointerInfo(SV), false, false, 0);
1858 // In big-endian mode we must adjust the pointer when the load size is smaller
1859 // than the argument slot size. We must also reduce the known alignment to
1860 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1861 // the correct half of the slot, and reduce the alignment from 8 (slot
1862 // alignment) down to 4 (type alignment).
1863 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1864 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1865 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1866 DAG.getIntPtrConstant(Adjustment));
1868 // Load the actual argument out of the pointer VAList
1869 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1873 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1874 bool HasExtractInsert) {
1875 EVT TyX = Op.getOperand(0).getValueType();
1876 EVT TyY = Op.getOperand(1).getValueType();
1877 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1878 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1882 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1884 SDValue X = (TyX == MVT::f32) ?
1885 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1886 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1888 SDValue Y = (TyY == MVT::f32) ?
1889 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1890 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1893 if (HasExtractInsert) {
1894 // ext E, Y, 31, 1 ; extract bit31 of Y
1895 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1896 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1897 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1900 // srl SrlX, SllX, 1
1902 // sll SllY, SrlX, 31
1903 // or Or, SrlX, SllY
1904 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1905 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1906 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1907 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1908 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1911 if (TyX == MVT::f32)
1912 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1914 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1915 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1916 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1919 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
1920 bool HasExtractInsert) {
1921 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1922 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1923 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1924 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1927 // Bitcast to integer nodes.
1928 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1929 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1931 if (HasExtractInsert) {
1932 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1933 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1934 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1935 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1937 if (WidthX > WidthY)
1938 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1939 else if (WidthY > WidthX)
1940 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1942 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1943 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1944 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1947 // (d)sll SllX, X, 1
1948 // (d)srl SrlX, SllX, 1
1949 // (d)srl SrlY, Y, width(Y)-1
1950 // (d)sll SllY, SrlX, width(Y)-1
1951 // or Or, SrlX, SllY
1952 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1953 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1954 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1955 DAG.getConstant(WidthY - 1, MVT::i32));
1957 if (WidthX > WidthY)
1958 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1959 else if (WidthY > WidthX)
1960 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1962 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1963 DAG.getConstant(WidthX - 1, MVT::i32));
1964 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1965 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1969 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1970 if (Subtarget.isGP64bit())
1971 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
1973 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
1976 SDValue MipsTargetLowering::
1977 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1979 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1980 "Frame address can only be determined for current frame.");
1982 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1983 MFI->setFrameAddressIsTaken(true);
1984 EVT VT = Op.getValueType();
1987 DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1988 Subtarget.isABI_N64() ? Mips::FP_64 : Mips::FP, VT);
1992 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1993 SelectionDAG &DAG) const {
1994 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1998 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1999 "Return address can be determined only for current frame.");
2001 MachineFunction &MF = DAG.getMachineFunction();
2002 MachineFrameInfo *MFI = MF.getFrameInfo();
2003 MVT VT = Op.getSimpleValueType();
2004 unsigned RA = Subtarget.isABI_N64() ? Mips::RA_64 : Mips::RA;
2005 MFI->setReturnAddressIsTaken(true);
2007 // Return RA, which contains the return address. Mark it an implicit live-in.
2008 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2009 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2012 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2013 // generated from __builtin_eh_return (offset, handler)
2014 // The effect of this is to adjust the stack pointer by "offset"
2015 // and then branch to "handler".
2016 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2018 MachineFunction &MF = DAG.getMachineFunction();
2019 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2021 MipsFI->setCallsEhReturn();
2022 SDValue Chain = Op.getOperand(0);
2023 SDValue Offset = Op.getOperand(1);
2024 SDValue Handler = Op.getOperand(2);
2026 EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
2028 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2029 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2030 unsigned OffsetReg = Subtarget.isABI_N64() ? Mips::V1_64 : Mips::V1;
2031 unsigned AddrReg = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
2032 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2033 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2034 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2035 DAG.getRegister(OffsetReg, Ty),
2036 DAG.getRegister(AddrReg, getPointerTy()),
2040 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2041 SelectionDAG &DAG) const {
2042 // FIXME: Need pseudo-fence for 'singlethread' fences
2043 // FIXME: Set SType for weaker fences where supported/appropriate.
2046 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2047 DAG.getConstant(SType, MVT::i32));
2050 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2051 SelectionDAG &DAG) const {
2053 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2055 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2056 SDValue Shamt = Op.getOperand(2);
2057 // if shamt < (VT.bits):
2058 // lo = (shl lo, shamt)
2059 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2062 // hi = (shl lo, shamt[4:0])
2063 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2064 DAG.getConstant(-1, MVT::i32));
2065 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2066 DAG.getConstant(1, VT));
2067 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2068 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2069 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2070 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2071 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2072 DAG.getConstant(VT.getSizeInBits(), MVT::i32));
2073 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2074 DAG.getConstant(0, VT), ShiftLeftLo);
2075 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2077 SDValue Ops[2] = {Lo, Hi};
2078 return DAG.getMergeValues(Ops, DL);
2081 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2084 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2085 SDValue Shamt = Op.getOperand(2);
2086 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2088 // if shamt < (VT.bits):
2089 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2091 // hi = (sra hi, shamt)
2093 // hi = (srl hi, shamt)
2096 // lo = (sra hi, shamt[4:0])
2097 // hi = (sra hi, 31)
2099 // lo = (srl hi, shamt[4:0])
2101 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2102 DAG.getConstant(-1, MVT::i32));
2103 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2104 DAG.getConstant(1, VT));
2105 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2106 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2107 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2108 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2110 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2111 DAG.getConstant(VT.getSizeInBits(), MVT::i32));
2112 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2113 DAG.getConstant(VT.getSizeInBits() - 1, VT));
2114 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2115 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2116 IsSRA ? Ext : DAG.getConstant(0, VT), ShiftRightHi);
2118 SDValue Ops[2] = {Lo, Hi};
2119 return DAG.getMergeValues(Ops, DL);
2122 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2123 SDValue Chain, SDValue Src, unsigned Offset) {
2124 SDValue Ptr = LD->getBasePtr();
2125 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2126 EVT BasePtrVT = Ptr.getValueType();
2128 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2131 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2132 DAG.getConstant(Offset, BasePtrVT));
2134 SDValue Ops[] = { Chain, Ptr, Src };
2135 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2136 LD->getMemOperand());
2139 // Expand an unaligned 32 or 64-bit integer load node.
2140 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2141 LoadSDNode *LD = cast<LoadSDNode>(Op);
2142 EVT MemVT = LD->getMemoryVT();
2144 if (Subtarget.systemSupportsUnalignedAccess())
2147 // Return if load is aligned or if MemVT is neither i32 nor i64.
2148 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2149 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2152 bool IsLittle = Subtarget.isLittle();
2153 EVT VT = Op.getValueType();
2154 ISD::LoadExtType ExtType = LD->getExtensionType();
2155 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2157 assert((VT == MVT::i32) || (VT == MVT::i64));
2160 // (set dst, (i64 (load baseptr)))
2162 // (set tmp, (ldl (add baseptr, 7), undef))
2163 // (set dst, (ldr baseptr, tmp))
2164 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2165 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2167 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2171 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2173 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2177 // (set dst, (i32 (load baseptr))) or
2178 // (set dst, (i64 (sextload baseptr))) or
2179 // (set dst, (i64 (extload baseptr)))
2181 // (set tmp, (lwl (add baseptr, 3), undef))
2182 // (set dst, (lwr baseptr, tmp))
2183 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2184 (ExtType == ISD::EXTLOAD))
2187 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2190 // (set dst, (i64 (zextload baseptr)))
2192 // (set tmp0, (lwl (add baseptr, 3), undef))
2193 // (set tmp1, (lwr baseptr, tmp0))
2194 // (set tmp2, (shl tmp1, 32))
2195 // (set dst, (srl tmp2, 32))
2197 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2198 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2199 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2200 SDValue Ops[] = { SRL, LWR.getValue(1) };
2201 return DAG.getMergeValues(Ops, DL);
2204 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2205 SDValue Chain, unsigned Offset) {
2206 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2207 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2209 SDVTList VTList = DAG.getVTList(MVT::Other);
2212 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2213 DAG.getConstant(Offset, BasePtrVT));
2215 SDValue Ops[] = { Chain, Value, Ptr };
2216 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2217 SD->getMemOperand());
2220 // Expand an unaligned 32 or 64-bit integer store node.
2221 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2223 SDValue Value = SD->getValue(), Chain = SD->getChain();
2224 EVT VT = Value.getValueType();
2227 // (store val, baseptr) or
2228 // (truncstore val, baseptr)
2230 // (swl val, (add baseptr, 3))
2231 // (swr val, baseptr)
2232 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2233 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2235 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2238 assert(VT == MVT::i64);
2241 // (store val, baseptr)
2243 // (sdl val, (add baseptr, 7))
2244 // (sdr val, baseptr)
2245 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2246 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2249 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2250 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2251 SDValue Val = SD->getValue();
2253 if (Val.getOpcode() != ISD::FP_TO_SINT)
2256 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2257 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2260 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2261 SD->getPointerInfo(), SD->isVolatile(),
2262 SD->isNonTemporal(), SD->getAlignment());
2265 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2266 StoreSDNode *SD = cast<StoreSDNode>(Op);
2267 EVT MemVT = SD->getMemoryVT();
2269 // Lower unaligned integer stores.
2270 if (!Subtarget.systemSupportsUnalignedAccess() &&
2271 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2272 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2273 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2275 return lowerFP_TO_SINT_STORE(SD, DAG);
2278 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2279 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2280 || cast<ConstantSDNode>
2281 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2282 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2286 // (add (frameaddr 0), (frame_to_args_offset))
2287 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2288 // (add FrameObject, 0)
2289 // where FrameObject is a fixed StackObject with offset 0 which points to
2290 // the old stack pointer.
2291 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2292 EVT ValTy = Op->getValueType(0);
2293 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2294 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2295 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2296 DAG.getConstant(0, ValTy));
2299 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2300 SelectionDAG &DAG) const {
2301 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2302 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2304 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2307 //===----------------------------------------------------------------------===//
2308 // Calling Convention Implementation
2309 //===----------------------------------------------------------------------===//
2311 //===----------------------------------------------------------------------===//
2312 // TODO: Implement a generic logic using tblgen that can support this.
2313 // Mips O32 ABI rules:
2315 // i32 - Passed in A0, A1, A2, A3 and stack
2316 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2317 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2318 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2319 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2320 // not used, it must be shadowed. If only A3 is available, shadow it and
2323 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2324 //===----------------------------------------------------------------------===//
2326 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2327 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2328 CCState &State, const MCPhysReg *F64Regs) {
2329 const MipsSubtarget &Subtarget =
2330 State.getMachineFunction().getTarget()
2331 .getSubtarget<const MipsSubtarget>();
2333 static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
2335 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2336 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2338 // Do not process byval args here.
2339 if (ArgFlags.isByVal())
2342 // Promote i8 and i16
2343 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2344 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2346 if (ArgFlags.isSExt())
2347 LocInfo = CCValAssign::SExtUpper;
2348 else if (ArgFlags.isZExt())
2349 LocInfo = CCValAssign::ZExtUpper;
2351 LocInfo = CCValAssign::AExtUpper;
2355 // Promote i8 and i16
2356 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2358 if (ArgFlags.isSExt())
2359 LocInfo = CCValAssign::SExt;
2360 else if (ArgFlags.isZExt())
2361 LocInfo = CCValAssign::ZExt;
2363 LocInfo = CCValAssign::AExt;
2368 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2369 // is true: function is vararg, argument is 3rd or higher, there is previous
2370 // argument which is not f32 or f64.
2371 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2372 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2373 unsigned OrigAlign = ArgFlags.getOrigAlign();
2374 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2376 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2377 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2378 // If this is the first part of an i64 arg,
2379 // the allocated register must be either A0 or A2.
2380 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2381 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2383 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2384 // Allocate int register and shadow next int register. If first
2385 // available register is Mips::A1 or Mips::A3, shadow it too.
2386 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2387 if (Reg == Mips::A1 || Reg == Mips::A3)
2388 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2389 State.AllocateReg(IntRegs, IntRegsSize);
2391 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2392 // we are guaranteed to find an available float register
2393 if (ValVT == MVT::f32) {
2394 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2395 // Shadow int register
2396 State.AllocateReg(IntRegs, IntRegsSize);
2398 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2399 // Shadow int registers
2400 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2401 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2402 State.AllocateReg(IntRegs, IntRegsSize);
2403 State.AllocateReg(IntRegs, IntRegsSize);
2406 llvm_unreachable("Cannot handle this ValVT.");
2409 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2411 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2413 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2418 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2419 MVT LocVT, CCValAssign::LocInfo LocInfo,
2420 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2421 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2423 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2426 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2427 MVT LocVT, CCValAssign::LocInfo LocInfo,
2428 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2429 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2431 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2434 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2435 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2436 CCState &State) LLVM_ATTRIBUTE_UNUSED;
2438 #include "MipsGenCallingConv.inc"
2440 //===----------------------------------------------------------------------===//
2441 // Call Calling Convention Implementation
2442 //===----------------------------------------------------------------------===//
2444 // Return next O32 integer argument register.
2445 static unsigned getNextIntArgReg(unsigned Reg) {
2446 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2447 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2451 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2452 SDValue Chain, SDValue Arg, SDLoc DL,
2453 bool IsTailCall, SelectionDAG &DAG) const {
2455 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2456 DAG.getIntPtrConstant(Offset));
2457 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2461 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2462 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2463 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2464 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2465 /*isVolatile=*/ true, false, 0);
2468 void MipsTargetLowering::
2469 getOpndList(SmallVectorImpl<SDValue> &Ops,
2470 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2471 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2472 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2473 SDValue Chain) const {
2474 // Insert node "GP copy globalreg" before call to function.
2476 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2477 // in PIC mode) allow symbols to be resolved via lazy binding.
2478 // The lazy binding stub requires GP to point to the GOT.
2479 // Note that we don't need GP to point to the GOT for indirect calls
2480 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2481 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2482 // used for the function (that is, Mips linker doesn't generate lazy binding
2483 // stub for a function whose address is taken in the program).
2484 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2485 unsigned GPReg = Subtarget.isABI_N64() ? Mips::GP_64 : Mips::GP;
2486 EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
2487 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2490 // Build a sequence of copy-to-reg nodes chained together with token
2491 // chain and flag operands which copy the outgoing args into registers.
2492 // The InFlag in necessary since all emitted instructions must be
2496 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2497 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2498 RegsToPass[i].second, InFlag);
2499 InFlag = Chain.getValue(1);
2502 // Add argument registers to the end of the list so that they are
2503 // known live into the call.
2504 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2505 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2506 RegsToPass[i].second.getValueType()));
2508 // Add a register mask operand representing the call-preserved registers.
2509 const TargetRegisterInfo *TRI =
2510 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2511 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2512 assert(Mask && "Missing call preserved mask for calling convention");
2513 if (Subtarget.inMips16HardFloat()) {
2514 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2515 llvm::StringRef Sym = G->getGlobal()->getName();
2516 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2517 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2518 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2522 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2524 if (InFlag.getNode())
2525 Ops.push_back(InFlag);
2528 /// LowerCall - functions arguments are copied from virtual regs to
2529 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2531 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2532 SmallVectorImpl<SDValue> &InVals) const {
2533 SelectionDAG &DAG = CLI.DAG;
2535 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2536 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2537 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2538 SDValue Chain = CLI.Chain;
2539 SDValue Callee = CLI.Callee;
2540 bool &IsTailCall = CLI.IsTailCall;
2541 CallingConv::ID CallConv = CLI.CallConv;
2542 bool IsVarArg = CLI.IsVarArg;
2544 MachineFunction &MF = DAG.getMachineFunction();
2545 MachineFrameInfo *MFI = MF.getFrameInfo();
2546 const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
2547 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2548 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2550 // Analyze operands of the call, assigning locations to each operand.
2551 SmallVector<CCValAssign, 16> ArgLocs;
2553 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2554 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2556 // Allocate the reserved argument area. It seems strange to do this from the
2557 // caller side but removing it breaks the frame size calculation.
2558 const MipsABIInfo &ABI = Subtarget.getABI();
2559 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2561 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2563 // Get a count of how many bytes are to be pushed on the stack.
2564 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2566 // Check if it's really possible to do a tail call.
2568 IsTailCall = isEligibleForTailCallOptimization(
2569 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2571 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2572 report_fatal_error("failed to perform tail call elimination on a call "
2573 "site marked musttail");
2578 // Chain is the output chain of the last Load/Store or CopyToReg node.
2579 // ByValChain is the output chain of the last Memcpy node created for copying
2580 // byval arguments to the stack.
2581 unsigned StackAlignment = TFL->getStackAlignment();
2582 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2583 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2586 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2588 SDValue StackPtr = DAG.getCopyFromReg(
2589 Chain, DL, Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP,
2592 // With EABI is it possible to have 16 args on registers.
2593 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2594 SmallVector<SDValue, 8> MemOpChains;
2596 CCInfo.rewindByValRegsInfo();
2598 // Walk the register/memloc assignments, inserting copies/loads.
2599 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2600 SDValue Arg = OutVals[i];
2601 CCValAssign &VA = ArgLocs[i];
2602 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2603 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2604 bool UseUpperBits = false;
2607 if (Flags.isByVal()) {
2608 unsigned FirstByValReg, LastByValReg;
2609 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2610 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2612 assert(Flags.getByValSize() &&
2613 "ByVal args of size 0 should have been ignored by front-end.");
2614 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2615 assert(!IsTailCall &&
2616 "Do not tail-call optimize if there is a byval argument.");
2617 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2618 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2620 CCInfo.nextInRegsParam();
2624 // Promote the value if needed.
2625 switch (VA.getLocInfo()) {
2627 llvm_unreachable("Unknown loc info!");
2628 case CCValAssign::Full:
2629 if (VA.isRegLoc()) {
2630 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2631 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2632 (ValVT == MVT::i64 && LocVT == MVT::f64))
2633 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2634 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2635 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2636 Arg, DAG.getConstant(0, MVT::i32));
2637 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2638 Arg, DAG.getConstant(1, MVT::i32));
2639 if (!Subtarget.isLittle())
2641 unsigned LocRegLo = VA.getLocReg();
2642 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2643 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2644 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2649 case CCValAssign::BCvt:
2650 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2652 case CCValAssign::SExtUpper:
2653 UseUpperBits = true;
2655 case CCValAssign::SExt:
2656 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2658 case CCValAssign::ZExtUpper:
2659 UseUpperBits = true;
2661 case CCValAssign::ZExt:
2662 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2664 case CCValAssign::AExtUpper:
2665 UseUpperBits = true;
2667 case CCValAssign::AExt:
2668 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2673 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2674 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2676 ISD::SHL, DL, VA.getLocVT(), Arg,
2677 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2680 // Arguments that can be passed on register must be kept at
2681 // RegsToPass vector
2682 if (VA.isRegLoc()) {
2683 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2687 // Register can't get to this point...
2688 assert(VA.isMemLoc());
2690 // emit ISD::STORE whichs stores the
2691 // parameter value to a stack Location
2692 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2693 Chain, Arg, DL, IsTailCall, DAG));
2696 // Transform all store nodes into one single node because all store
2697 // nodes are independent of each other.
2698 if (!MemOpChains.empty())
2699 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2701 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2702 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2703 // node so that legalize doesn't hack it.
2705 (Subtarget.isABI_N64() || IsPIC); // true if calls are translated to
2707 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2709 EVT Ty = Callee.getValueType();
2711 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2713 const GlobalValue *Val = G->getGlobal();
2714 InternalLinkage = Val->hasInternalLinkage();
2716 if (InternalLinkage)
2717 Callee = getAddrLocal(G, DL, Ty, DAG,
2718 Subtarget.isABI_N32() || Subtarget.isABI_N64());
2719 else if (LargeGOT) {
2720 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2721 MipsII::MO_CALL_LO16, Chain,
2722 FuncInfo->callPtrInfo(Val));
2725 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2726 FuncInfo->callPtrInfo(Val));
2730 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2731 MipsII::MO_NO_FLAG);
2732 GlobalOrExternal = true;
2734 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2735 const char *Sym = S->getSymbol();
2737 if (!Subtarget.isABI_N64() && !IsPIC) // !N64 && static
2739 DAG.getTargetExternalSymbol(Sym, getPointerTy(), MipsII::MO_NO_FLAG);
2740 else if (LargeGOT) {
2741 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2742 MipsII::MO_CALL_LO16, Chain,
2743 FuncInfo->callPtrInfo(Sym));
2745 } else { // N64 || PIC
2746 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2747 FuncInfo->callPtrInfo(Sym));
2751 GlobalOrExternal = true;
2754 SmallVector<SDValue, 8> Ops(1, Chain);
2755 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2757 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2758 IsCallReloc, CLI, Callee, Chain);
2761 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2763 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2764 SDValue InFlag = Chain.getValue(1);
2766 // Create the CALLSEQ_END node.
2767 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2768 DAG.getIntPtrConstant(0, true), InFlag, DL);
2769 InFlag = Chain.getValue(1);
2771 // Handle result values, copying them out of physregs into vregs that we
2773 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2777 /// LowerCallResult - Lower the result values of a call into the
2778 /// appropriate copies out of appropriate physical registers.
2779 SDValue MipsTargetLowering::LowerCallResult(
2780 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2781 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2782 SmallVectorImpl<SDValue> &InVals,
2783 TargetLowering::CallLoweringInfo &CLI) const {
2784 // Assign locations to each value returned by this call.
2785 SmallVector<CCValAssign, 16> RVLocs;
2786 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2788 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2790 // Copy all of the result registers out of their specified physreg.
2791 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2792 CCValAssign &VA = RVLocs[i];
2793 assert(VA.isRegLoc() && "Can only return in registers!");
2795 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2796 RVLocs[i].getLocVT(), InFlag);
2797 Chain = Val.getValue(1);
2798 InFlag = Val.getValue(2);
2800 if (VA.isUpperBitsInLoc()) {
2801 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2802 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2804 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2806 Shift, DL, VA.getLocVT(), Val,
2807 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2810 switch (VA.getLocInfo()) {
2812 llvm_unreachable("Unknown loc info!");
2813 case CCValAssign::Full:
2815 case CCValAssign::BCvt:
2816 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2818 case CCValAssign::AExt:
2819 case CCValAssign::AExtUpper:
2820 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2822 case CCValAssign::ZExt:
2823 case CCValAssign::ZExtUpper:
2824 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2825 DAG.getValueType(VA.getValVT()));
2826 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2828 case CCValAssign::SExt:
2829 case CCValAssign::SExtUpper:
2830 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2831 DAG.getValueType(VA.getValVT()));
2832 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2836 InVals.push_back(Val);
2842 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
2843 EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
2844 MVT LocVT = VA.getLocVT();
2845 EVT ValVT = VA.getValVT();
2847 // Shift into the upper bits if necessary.
2848 switch (VA.getLocInfo()) {
2851 case CCValAssign::AExtUpper:
2852 case CCValAssign::SExtUpper:
2853 case CCValAssign::ZExtUpper: {
2854 unsigned ValSizeInBits = ArgVT.getSizeInBits();
2855 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2857 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2859 Opcode, DL, VA.getLocVT(), Val,
2860 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2865 // If this is an value smaller than the argument slot size (32-bit for O32,
2866 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
2867 // size. Extract the value and insert any appropriate assertions regarding
2868 // sign/zero extension.
2869 switch (VA.getLocInfo()) {
2871 llvm_unreachable("Unknown loc info!");
2872 case CCValAssign::Full:
2874 case CCValAssign::AExtUpper:
2875 case CCValAssign::AExt:
2876 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2878 case CCValAssign::SExtUpper:
2879 case CCValAssign::SExt:
2880 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
2881 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2883 case CCValAssign::ZExtUpper:
2884 case CCValAssign::ZExt:
2885 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
2886 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2888 case CCValAssign::BCvt:
2889 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2896 //===----------------------------------------------------------------------===//
2897 // Formal Arguments Calling Convention Implementation
2898 //===----------------------------------------------------------------------===//
2899 /// LowerFormalArguments - transform physical registers into virtual registers
2900 /// and generate load operations for arguments places on the stack.
2902 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2903 CallingConv::ID CallConv,
2905 const SmallVectorImpl<ISD::InputArg> &Ins,
2906 SDLoc DL, SelectionDAG &DAG,
2907 SmallVectorImpl<SDValue> &InVals)
2909 MachineFunction &MF = DAG.getMachineFunction();
2910 MachineFrameInfo *MFI = MF.getFrameInfo();
2911 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2913 MipsFI->setVarArgsFrameIndex(0);
2915 // Used with vargs to acumulate store chains.
2916 std::vector<SDValue> OutChains;
2918 // Assign locations to all of the incoming arguments.
2919 SmallVector<CCValAssign, 16> ArgLocs;
2920 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2922 const MipsABIInfo &ABI = Subtarget.getABI();
2923 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2924 Function::const_arg_iterator FuncArg =
2925 DAG.getMachineFunction().getFunction()->arg_begin();
2927 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
2928 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2929 CCInfo.getInRegsParamsCount() > 0);
2931 unsigned CurArgIdx = 0;
2932 CCInfo.rewindByValRegsInfo();
2934 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2935 CCValAssign &VA = ArgLocs[i];
2936 if (Ins[i].isOrigArg()) {
2937 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2938 CurArgIdx = Ins[i].getOrigArgIndex();
2940 EVT ValVT = VA.getValVT();
2941 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2942 bool IsRegLoc = VA.isRegLoc();
2944 if (Flags.isByVal()) {
2945 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
2946 unsigned FirstByValReg, LastByValReg;
2947 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2948 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2950 assert(Flags.getByValSize() &&
2951 "ByVal args of size 0 should have been ignored by front-end.");
2952 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2953 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2954 FirstByValReg, LastByValReg, VA, CCInfo);
2955 CCInfo.nextInRegsParam();
2959 // Arguments stored on registers
2961 MVT RegVT = VA.getLocVT();
2962 unsigned ArgReg = VA.getLocReg();
2963 const TargetRegisterClass *RC = getRegClassFor(RegVT);
2965 // Transform the arguments stored on
2966 // physical registers into virtual ones
2967 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2968 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2970 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
2972 // Handle floating point arguments passed in integer registers and
2973 // long double arguments passed in floating point registers.
2974 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2975 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2976 (RegVT == MVT::f64 && ValVT == MVT::i64))
2977 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2978 else if (Subtarget.isABI_O32() && RegVT == MVT::i32 &&
2979 ValVT == MVT::f64) {
2980 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2981 getNextIntArgReg(ArgReg), RC);
2982 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2983 if (!Subtarget.isLittle())
2984 std::swap(ArgValue, ArgValue2);
2985 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2986 ArgValue, ArgValue2);
2989 InVals.push_back(ArgValue);
2990 } else { // VA.isRegLoc()
2991 MVT LocVT = VA.getLocVT();
2993 if (Subtarget.isABI_O32()) {
2994 // We ought to be able to use LocVT directly but O32 sets it to i32
2995 // when allocating floating point values to integer registers.
2996 // This shouldn't influence how we load the value into registers unless
2997 // we are targetting softfloat.
2998 if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat())
2999 LocVT = VA.getValVT();
3003 assert(VA.isMemLoc());
3005 // The stack pointer offset is relative to the caller stack frame.
3006 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
3007 VA.getLocMemOffset(), true);
3009 // Create load nodes to retrieve arguments from the stack
3010 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3011 SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
3012 MachinePointerInfo::getFixedStack(FI),
3013 false, false, false, 0);
3014 OutChains.push_back(ArgValue.getValue(1));
3016 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3018 InVals.push_back(ArgValue);
3022 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3023 // The mips ABIs for returning structs by value requires that we copy
3024 // the sret argument into $v0 for the return. Save the argument into
3025 // a virtual register so that we can access it from the return points.
3026 if (Ins[i].Flags.isSRet()) {
3027 unsigned Reg = MipsFI->getSRetReturnReg();
3029 Reg = MF.getRegInfo().createVirtualRegister(
3030 getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32));
3031 MipsFI->setSRetReturnReg(Reg);
3033 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3034 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3040 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3042 // All stores are grouped in one node to allow the matching between
3043 // the size of Ins and InVals. This only happens when on varg functions
3044 if (!OutChains.empty()) {
3045 OutChains.push_back(Chain);
3046 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3052 //===----------------------------------------------------------------------===//
3053 // Return Value Calling Convention Implementation
3054 //===----------------------------------------------------------------------===//
3057 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3058 MachineFunction &MF, bool IsVarArg,
3059 const SmallVectorImpl<ISD::OutputArg> &Outs,
3060 LLVMContext &Context) const {
3061 SmallVector<CCValAssign, 16> RVLocs;
3062 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3063 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3067 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3068 if (Subtarget.hasMips3() && Subtarget.abiUsesSoftFloat()) {
3069 if (Type == MVT::i32)
3076 MipsTargetLowering::LowerReturn(SDValue Chain,
3077 CallingConv::ID CallConv, bool IsVarArg,
3078 const SmallVectorImpl<ISD::OutputArg> &Outs,
3079 const SmallVectorImpl<SDValue> &OutVals,
3080 SDLoc DL, SelectionDAG &DAG) const {
3081 // CCValAssign - represent the assignment of
3082 // the return value to a location
3083 SmallVector<CCValAssign, 16> RVLocs;
3084 MachineFunction &MF = DAG.getMachineFunction();
3086 // CCState - Info about the registers and stack slot.
3087 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3089 // Analyze return values.
3090 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3093 SmallVector<SDValue, 4> RetOps(1, Chain);
3095 // Copy the result values into the output registers.
3096 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3097 SDValue Val = OutVals[i];
3098 CCValAssign &VA = RVLocs[i];
3099 assert(VA.isRegLoc() && "Can only return in registers!");
3100 bool UseUpperBits = false;
3102 switch (VA.getLocInfo()) {
3104 llvm_unreachable("Unknown loc info!");
3105 case CCValAssign::Full:
3107 case CCValAssign::BCvt:
3108 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3110 case CCValAssign::AExtUpper:
3111 UseUpperBits = true;
3113 case CCValAssign::AExt:
3114 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3116 case CCValAssign::ZExtUpper:
3117 UseUpperBits = true;
3119 case CCValAssign::ZExt:
3120 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3122 case CCValAssign::SExtUpper:
3123 UseUpperBits = true;
3125 case CCValAssign::SExt:
3126 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3131 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3132 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3134 ISD::SHL, DL, VA.getLocVT(), Val,
3135 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
3138 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3140 // Guarantee that all emitted copies are stuck together with flags.
3141 Flag = Chain.getValue(1);
3142 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3145 // The mips ABIs for returning structs by value requires that we copy
3146 // the sret argument into $v0 for the return. We saved the argument into
3147 // a virtual register in the entry block, so now we copy the value out
3149 if (MF.getFunction()->hasStructRetAttr()) {
3150 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3151 unsigned Reg = MipsFI->getSRetReturnReg();
3154 llvm_unreachable("sret virtual register not created in the entry block");
3155 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
3156 unsigned V0 = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
3158 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3159 Flag = Chain.getValue(1);
3160 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
3163 RetOps[0] = Chain; // Update chain.
3165 // Add the flag if we have it.
3167 RetOps.push_back(Flag);
3169 // Return on Mips is always a "jr $ra"
3170 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3173 //===----------------------------------------------------------------------===//
3174 // Mips Inline Assembly Support
3175 //===----------------------------------------------------------------------===//
3177 /// getConstraintType - Given a constraint letter, return the type of
3178 /// constraint it is for this target.
3179 MipsTargetLowering::ConstraintType MipsTargetLowering::
3180 getConstraintType(const std::string &Constraint) const
3182 // Mips specific constraints
3183 // GCC config/mips/constraints.md
3185 // 'd' : An address register. Equivalent to r
3186 // unless generating MIPS16 code.
3187 // 'y' : Equivalent to r; retained for
3188 // backwards compatibility.
3189 // 'c' : A register suitable for use in an indirect
3190 // jump. This will always be $25 for -mabicalls.
3191 // 'l' : The lo register. 1 word storage.
3192 // 'x' : The hilo register pair. Double word storage.
3193 if (Constraint.size() == 1) {
3194 switch (Constraint[0]) {
3202 return C_RegisterClass;
3207 return TargetLowering::getConstraintType(Constraint);
3210 /// Examine constraint type and operand type and determine a weight value.
3211 /// This object must already have been set up with the operand type
3212 /// and the current alternative constraint selected.
3213 TargetLowering::ConstraintWeight
3214 MipsTargetLowering::getSingleConstraintMatchWeight(
3215 AsmOperandInfo &info, const char *constraint) const {
3216 ConstraintWeight weight = CW_Invalid;
3217 Value *CallOperandVal = info.CallOperandVal;
3218 // If we don't have a value, we can't do a match,
3219 // but allow it at the lowest weight.
3220 if (!CallOperandVal)
3222 Type *type = CallOperandVal->getType();
3223 // Look at the constraint type.
3224 switch (*constraint) {
3226 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3230 if (type->isIntegerTy())
3231 weight = CW_Register;
3233 case 'f': // FPU or MSA register
3234 if (Subtarget.hasMSA() && type->isVectorTy() &&
3235 cast<VectorType>(type)->getBitWidth() == 128)
3236 weight = CW_Register;
3237 else if (type->isFloatTy())
3238 weight = CW_Register;
3240 case 'c': // $25 for indirect jumps
3241 case 'l': // lo register
3242 case 'x': // hilo register pair
3243 if (type->isIntegerTy())
3244 weight = CW_SpecificReg;
3246 case 'I': // signed 16 bit immediate
3247 case 'J': // integer zero
3248 case 'K': // unsigned 16 bit immediate
3249 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3250 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3251 case 'O': // signed 15 bit immediate (+- 16383)
3252 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3253 if (isa<ConstantInt>(CallOperandVal))
3254 weight = CW_Constant;
3263 /// This is a helper function to parse a physical register string and split it
3264 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3265 /// that is returned indicates whether parsing was successful. The second flag
3266 /// is true if the numeric part exists.
3267 static std::pair<bool, bool>
3268 parsePhysicalReg(StringRef C, std::string &Prefix,
3269 unsigned long long &Reg) {
3270 if (C.front() != '{' || C.back() != '}')
3271 return std::make_pair(false, false);
3273 // Search for the first numeric character.
3274 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3275 I = std::find_if(B, E, std::ptr_fun(isdigit));
3277 Prefix.assign(B, I - B);
3279 // The second flag is set to false if no numeric characters were found.
3281 return std::make_pair(true, false);
3283 // Parse the numeric characters.
3284 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3288 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3289 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3290 const TargetRegisterInfo *TRI =
3291 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3292 const TargetRegisterClass *RC;
3294 unsigned long long Reg;
3296 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3299 return std::make_pair(0U, nullptr);
3301 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3302 // No numeric characters follow "hi" or "lo".
3304 return std::make_pair(0U, nullptr);
3306 RC = TRI->getRegClass(Prefix == "hi" ?
3307 Mips::HI32RegClassID : Mips::LO32RegClassID);
3308 return std::make_pair(*(RC->begin()), RC);
3309 } else if (Prefix.compare(0, 4, "$msa") == 0) {
3310 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3312 // No numeric characters follow the name.
3314 return std::make_pair(0U, nullptr);
3316 Reg = StringSwitch<unsigned long long>(Prefix)
3317 .Case("$msair", Mips::MSAIR)
3318 .Case("$msacsr", Mips::MSACSR)
3319 .Case("$msaaccess", Mips::MSAAccess)
3320 .Case("$msasave", Mips::MSASave)
3321 .Case("$msamodify", Mips::MSAModify)
3322 .Case("$msarequest", Mips::MSARequest)
3323 .Case("$msamap", Mips::MSAMap)
3324 .Case("$msaunmap", Mips::MSAUnmap)
3328 return std::make_pair(0U, nullptr);
3330 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3331 return std::make_pair(Reg, RC);
3335 return std::make_pair(0U, nullptr);
3337 if (Prefix == "$f") { // Parse $f0-$f31.
3338 // If the size of FP registers is 64-bit or Reg is an even number, select
3339 // the 64-bit register class. Otherwise, select the 32-bit register class.
3340 if (VT == MVT::Other)
3341 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3343 RC = getRegClassFor(VT);
3345 if (RC == &Mips::AFGR64RegClass) {
3346 assert(Reg % 2 == 0);
3349 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3350 RC = TRI->getRegClass(Mips::FCCRegClassID);
3351 else if (Prefix == "$w") { // Parse $w0-$w31.
3352 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3353 } else { // Parse $0-$31.
3354 assert(Prefix == "$");
3355 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3358 assert(Reg < RC->getNumRegs());
3359 return std::make_pair(*(RC->begin() + Reg), RC);
3362 /// Given a register class constraint, like 'r', if this corresponds directly
3363 /// to an LLVM register class, return a register of 0 and the register class
3365 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3366 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
3368 if (Constraint.size() == 1) {
3369 switch (Constraint[0]) {
3370 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3371 case 'y': // Same as 'r'. Exists for compatibility.
3373 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3374 if (Subtarget.inMips16Mode())
3375 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3376 return std::make_pair(0U, &Mips::GPR32RegClass);
3378 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3379 return std::make_pair(0U, &Mips::GPR32RegClass);
3380 if (VT == MVT::i64 && Subtarget.isGP64bit())
3381 return std::make_pair(0U, &Mips::GPR64RegClass);
3382 // This will generate an error message
3383 return std::make_pair(0U, nullptr);
3384 case 'f': // FPU or MSA register
3385 if (VT == MVT::v16i8)
3386 return std::make_pair(0U, &Mips::MSA128BRegClass);
3387 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3388 return std::make_pair(0U, &Mips::MSA128HRegClass);
3389 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3390 return std::make_pair(0U, &Mips::MSA128WRegClass);
3391 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3392 return std::make_pair(0U, &Mips::MSA128DRegClass);
3393 else if (VT == MVT::f32)
3394 return std::make_pair(0U, &Mips::FGR32RegClass);
3395 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3396 if (Subtarget.isFP64bit())
3397 return std::make_pair(0U, &Mips::FGR64RegClass);
3398 return std::make_pair(0U, &Mips::AFGR64RegClass);
3401 case 'c': // register suitable for indirect jump
3403 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3404 assert(VT == MVT::i64 && "Unexpected type.");
3405 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3406 case 'l': // register suitable for indirect jump
3408 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3409 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3410 case 'x': // register suitable for indirect jump
3411 // Fixme: Not triggering the use of both hi and low
3412 // This will generate an error message
3413 return std::make_pair(0U, nullptr);
3417 std::pair<unsigned, const TargetRegisterClass *> R;
3418 R = parseRegForInlineAsmConstraint(Constraint, VT);
3423 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3426 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3427 /// vector. If it is invalid, don't add anything to Ops.
3428 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3429 std::string &Constraint,
3430 std::vector<SDValue>&Ops,
3431 SelectionDAG &DAG) const {
3434 // Only support length 1 constraints for now.
3435 if (Constraint.length() > 1) return;
3437 char ConstraintLetter = Constraint[0];
3438 switch (ConstraintLetter) {
3439 default: break; // This will fall through to the generic implementation
3440 case 'I': // Signed 16 bit constant
3441 // If this fails, the parent routine will give an error
3442 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3443 EVT Type = Op.getValueType();
3444 int64_t Val = C->getSExtValue();
3445 if (isInt<16>(Val)) {
3446 Result = DAG.getTargetConstant(Val, Type);
3451 case 'J': // integer zero
3452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3453 EVT Type = Op.getValueType();
3454 int64_t Val = C->getZExtValue();
3456 Result = DAG.getTargetConstant(0, Type);
3461 case 'K': // unsigned 16 bit immediate
3462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3463 EVT Type = Op.getValueType();
3464 uint64_t Val = (uint64_t)C->getZExtValue();
3465 if (isUInt<16>(Val)) {
3466 Result = DAG.getTargetConstant(Val, Type);
3471 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3473 EVT Type = Op.getValueType();
3474 int64_t Val = C->getSExtValue();
3475 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3476 Result = DAG.getTargetConstant(Val, Type);
3481 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3483 EVT Type = Op.getValueType();
3484 int64_t Val = C->getSExtValue();
3485 if ((Val >= -65535) && (Val <= -1)) {
3486 Result = DAG.getTargetConstant(Val, Type);
3491 case 'O': // signed 15 bit immediate
3492 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3493 EVT Type = Op.getValueType();
3494 int64_t Val = C->getSExtValue();
3495 if ((isInt<15>(Val))) {
3496 Result = DAG.getTargetConstant(Val, Type);
3501 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3502 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3503 EVT Type = Op.getValueType();
3504 int64_t Val = C->getSExtValue();
3505 if ((Val <= 65535) && (Val >= 1)) {
3506 Result = DAG.getTargetConstant(Val, Type);
3513 if (Result.getNode()) {
3514 Ops.push_back(Result);
3518 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3521 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3523 // No global is ever allowed as a base.
3528 case 0: // "r+i" or just "i", depending on HasBaseReg.
3531 if (!AM.HasBaseReg) // allow "r+i".
3533 return false; // disallow "r+r" or "r+r+i".
3542 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3543 // The Mips target isn't yet aware of offsets.
3547 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3549 bool IsMemset, bool ZeroMemset,
3551 MachineFunction &MF) const {
3552 if (Subtarget.hasMips64())
3558 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3559 if (VT != MVT::f32 && VT != MVT::f64)
3561 if (Imm.isNegZero())
3563 return Imm.isZero();
3566 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3567 if (Subtarget.isABI_N64())
3568 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3570 return TargetLowering::getJumpTableEncoding();
3573 void MipsTargetLowering::copyByValRegs(
3574 SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3575 const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
3576 const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
3577 const CCValAssign &VA, MipsCCState &State) const {
3578 MachineFunction &MF = DAG.getMachineFunction();
3579 MachineFrameInfo *MFI = MF.getFrameInfo();
3580 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3581 unsigned NumRegs = LastReg - FirstReg;
3582 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3583 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3585 const MipsABIInfo &ABI = Subtarget.getABI();
3586 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3590 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3591 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3593 FrameObjOffset = VA.getLocMemOffset();
3595 // Create frame object.
3596 EVT PtrTy = getPointerTy();
3597 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3598 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3599 InVals.push_back(FIN);
3604 // Copy arg registers.
3605 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3606 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3608 for (unsigned I = 0; I < NumRegs; ++I) {
3609 unsigned ArgReg = ByValArgRegs[FirstReg + I];
3610 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3611 unsigned Offset = I * GPRSizeInBytes;
3612 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3613 DAG.getConstant(Offset, PtrTy));
3614 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3615 StorePtr, MachinePointerInfo(FuncArg, Offset),
3617 OutChains.push_back(Store);
3621 // Copy byVal arg to registers and stack.
3622 void MipsTargetLowering::passByValArg(
3623 SDValue Chain, SDLoc DL,
3624 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3625 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3626 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3627 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3628 const CCValAssign &VA) const {
3629 unsigned ByValSizeInBytes = Flags.getByValSize();
3630 unsigned OffsetInBytes = 0; // From beginning of struct
3631 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3632 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3633 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3634 unsigned NumRegs = LastReg - FirstReg;
3637 const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetByValArgRegs();
3638 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3641 // Copy words to registers.
3642 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3643 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3644 DAG.getConstant(OffsetInBytes, PtrTy));
3645 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3646 MachinePointerInfo(), false, false, false,
3648 MemOpChains.push_back(LoadVal.getValue(1));
3649 unsigned ArgReg = ArgRegs[FirstReg + I];
3650 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3653 // Return if the struct has been fully copied.
3654 if (ByValSizeInBytes == OffsetInBytes)
3657 // Copy the remainder of the byval argument with sub-word loads and shifts.
3658 if (LeftoverBytes) {
3661 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3662 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3663 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3665 if (RemainingSizeInBytes < LoadSizeInBytes)
3669 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3670 DAG.getConstant(OffsetInBytes, PtrTy));
3671 SDValue LoadVal = DAG.getExtLoad(
3672 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3673 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3675 MemOpChains.push_back(LoadVal.getValue(1));
3677 // Shift the loaded value.
3681 Shamt = TotalBytesLoaded * 8;
3683 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3685 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3686 DAG.getConstant(Shamt, MVT::i32));
3689 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3693 OffsetInBytes += LoadSizeInBytes;
3694 TotalBytesLoaded += LoadSizeInBytes;
3695 Alignment = std::min(Alignment, LoadSizeInBytes);
3698 unsigned ArgReg = ArgRegs[FirstReg + I];
3699 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3704 // Copy remainder of byval arg to it with memcpy.
3705 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3706 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3707 DAG.getConstant(OffsetInBytes, PtrTy));
3708 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3709 DAG.getIntPtrConstant(VA.getLocMemOffset()));
3710 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
3711 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3712 MachinePointerInfo(), MachinePointerInfo());
3713 MemOpChains.push_back(Chain);
3716 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3717 SDValue Chain, SDLoc DL,
3719 CCState &State) const {
3720 const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetVarArgRegs();
3721 unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
3722 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3723 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3724 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3725 MachineFunction &MF = DAG.getMachineFunction();
3726 MachineFrameInfo *MFI = MF.getFrameInfo();
3727 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3729 // Offset of the first variable argument from stack pointer.
3732 if (ArgRegs.size() == Idx)
3734 RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
3736 const MipsABIInfo &ABI = Subtarget.getABI();
3738 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3739 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3742 // Record the frame index of the first variable argument
3743 // which is a value necessary to VASTART.
3744 int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3745 MipsFI->setVarArgsFrameIndex(FI);
3747 // Copy the integer registers that have not been used for argument passing
3748 // to the argument register save area. For O32, the save area is allocated
3749 // in the caller's stack frame, while for N32/64, it is allocated in the
3750 // callee's stack frame.
3751 for (unsigned I = Idx; I < ArgRegs.size();
3752 ++I, VaArgOffset += RegSizeInBytes) {
3753 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3754 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3755 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3756 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3757 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3758 MachinePointerInfo(), false, false, 0);
3759 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3761 OutChains.push_back(Store);
3765 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3766 unsigned Align) const {
3767 MachineFunction &MF = State->getMachineFunction();
3768 const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
3770 assert(Size && "Byval argument's size shouldn't be 0.");
3772 Align = std::min(Align, TFL->getStackAlignment());
3774 unsigned FirstReg = 0;
3775 unsigned NumRegs = 0;
3777 if (State->getCallingConv() != CallingConv::Fast) {
3778 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3779 const ArrayRef<MCPhysReg> IntArgRegs = Subtarget.getABI().GetByValArgRegs();
3780 // FIXME: The O32 case actually describes no shadow registers.
3781 const MCPhysReg *ShadowRegs =
3782 Subtarget.isABI_O32() ? IntArgRegs.data() : Mips64DPRegs;
3784 // We used to check the size as well but we can't do that anymore since
3785 // CCState::HandleByVal() rounds up the size after calling this function.
3786 assert(!(Align % RegSizeInBytes) &&
3787 "Byval argument's alignment should be a multiple of"
3790 FirstReg = State->getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
3792 // If Align > RegSizeInBytes, the first arg register must be even.
3793 // FIXME: This condition happens to do the right thing but it's not the
3794 // right way to test it. We want to check that the stack frame offset
3795 // of the register is aligned.
3796 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3797 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3801 // Mark the registers allocated.
3802 Size = RoundUpToAlignment(Size, RegSizeInBytes);
3803 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3804 Size -= RegSizeInBytes, ++I, ++NumRegs)
3805 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3808 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3812 MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB,
3813 bool isFPCmp, unsigned Opc) const {
3814 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
3815 "Subtarget already supports SELECT nodes with the use of"
3816 "conditional-move instructions.");
3818 const TargetInstrInfo *TII =
3819 getTargetMachine().getSubtargetImpl()->getInstrInfo();
3820 DebugLoc DL = MI->getDebugLoc();
3822 // To "insert" a SELECT instruction, we actually have to insert the
3823 // diamond control-flow pattern. The incoming instruction knows the
3824 // destination vreg to set, the condition code register to branch on, the
3825 // true/false values to select between, and a branch opcode to use.
3826 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3827 MachineFunction::iterator It = BB;
3834 // bNE r1, r0, copy1MBB
3835 // fallthrough --> copy0MBB
3836 MachineBasicBlock *thisMBB = BB;
3837 MachineFunction *F = BB->getParent();
3838 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3839 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3840 F->insert(It, copy0MBB);
3841 F->insert(It, sinkMBB);
3843 // Transfer the remainder of BB and its successor edges to sinkMBB.
3844 sinkMBB->splice(sinkMBB->begin(), BB,
3845 std::next(MachineBasicBlock::iterator(MI)), BB->end());
3846 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3848 // Next, add the true and fallthrough blocks as its successors.
3849 BB->addSuccessor(copy0MBB);
3850 BB->addSuccessor(sinkMBB);
3853 // bc1[tf] cc, sinkMBB
3854 BuildMI(BB, DL, TII->get(Opc))
3855 .addReg(MI->getOperand(1).getReg())
3858 // bne rs, $0, sinkMBB
3859 BuildMI(BB, DL, TII->get(Opc))
3860 .addReg(MI->getOperand(1).getReg())
3866 // %FalseValue = ...
3867 // # fallthrough to sinkMBB
3870 // Update machine-CFG edges
3871 BB->addSuccessor(sinkMBB);
3874 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
3878 BuildMI(*BB, BB->begin(), DL,
3879 TII->get(Mips::PHI), MI->getOperand(0).getReg())
3880 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
3881 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
3883 MI->eraseFromParent(); // The pseudo instruction is gone now.
3888 // FIXME? Maybe this could be a TableGen attribute on some registers and
3889 // this table could be generated automatically from RegInfo.
3890 unsigned MipsTargetLowering::getRegisterByName(const char* RegName,
3892 // Named registers is expected to be fairly rare. For now, just support $28
3893 // since the linux kernel uses it.
3894 if (Subtarget.isGP64bit()) {
3895 unsigned Reg = StringSwitch<unsigned>(RegName)
3896 .Case("$28", Mips::GP_64)
3901 unsigned Reg = StringSwitch<unsigned>(RegName)
3902 .Case("$28", Mips::GP)
3907 report_fatal_error("Invalid register name global variable");