1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
30 enum NodeType : unsigned {
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Highest (63-48) 16 bits from a 64-bit immediate
43 // Get the Higher (47-32) 16 bits from a 64-bit immediate
46 // Get the High 16 bits from a 32/64-bit immediate
47 // No relation with Mips Hi register
50 // Get the Lower 16 bits from a 32/64-bit immediate
51 // No relation with Mips Lo register
54 // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
57 // Handle gp_rel (small data/bss sections) relocation.
63 // Floating Point Branch Conditional
66 // Floating Point Compare
69 // Floating Point Conditional Moves
73 // FP-to-int truncation node.
79 // Interrupt, exception, error trap Return
82 // Software Exception Return.
85 // Node used to extract integer from accumulator.
89 // Node used to insert integers to accumulator.
121 // EXTR.W instrinsic nodes.
131 // DPA.W intrinsic nodes.
167 // DSP setcc and select_cc nodes.
171 // Vector comparisons.
172 // These take a vector and return a boolean.
178 // These take a vector and return a vector bitmask.
185 // Element-wise vector max/min.
191 // Vector Shuffle with mask as an operand
192 VSHF, // Generic shuffle
193 SHF, // 4-element set shuffle.
194 ILVEV, // Interleave even elements
195 ILVOD, // Interleave odd elements
196 ILVL, // Interleave left elements
197 ILVR, // Interleave right elements
198 PCKEV, // Pack even elements
199 PCKOD, // Pack odd elements
202 INSVE, // Copy element from one vector to another
204 // Combined (XOR (OR $a, $b), -1)
207 // Extended vector element extraction
211 // Load/Store Left/Right nodes.
212 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
223 //===--------------------------------------------------------------------===//
224 // TargetLowering Implementation
225 //===--------------------------------------------------------------------===//
226 class MipsFunctionInfo;
230 class MipsTargetLowering : public TargetLowering {
233 explicit MipsTargetLowering(const MipsTargetMachine &TM,
234 const MipsSubtarget &STI);
236 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
237 const MipsSubtarget &STI);
239 /// createFastISel - This method returns a target specific FastISel object,
240 /// or null if the target does not support "fast" ISel.
241 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
242 const TargetLibraryInfo *libInfo) const override;
244 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
248 bool isCheapToSpeculateCttz() const override;
249 bool isCheapToSpeculateCtlz() const override;
251 /// Return the register type for a given MVT, ensuring vectors are treated
252 /// as a series of gpr sized integers.
253 virtual MVT getRegisterTypeForCallingConv(MVT VT) const override;
255 /// Return the register type for a given MVT, ensuring vectors are treated
256 /// as a series of gpr sized integers.
257 virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
258 EVT VT) const override;
260 /// Return the number of registers for a given MVT, ensuring vectors are
261 /// treated as a series of gpr sized integers.
262 virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
263 EVT VT) const override;
265 /// Break down vectors to the correct number of gpr sized integers.
266 virtual unsigned getVectorTypeBreakdownForCallingConv(
267 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
268 unsigned &NumIntermediates, MVT &RegisterVT) const override;
270 /// Return the correct alignment for the current calling convention.
272 getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override {
273 if (ArgTy->isVectorTy())
274 return std::min(DL.getABITypeAlignment(ArgTy), 8U);
275 return DL.getABITypeAlignment(ArgTy);
278 ISD::NodeType getExtendForAtomicOps() const override {
279 return ISD::SIGN_EXTEND;
282 void LowerOperationWrapper(SDNode *N,
283 SmallVectorImpl<SDValue> &Results,
284 SelectionDAG &DAG) const override;
286 /// LowerOperation - Provide custom lowering hooks for some operations.
287 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
289 /// ReplaceNodeResults - Replace the results of node with an illegal result
290 /// type with new values built out of custom code.
292 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
293 SelectionDAG &DAG) const override;
295 /// getTargetNodeName - This method returns the name of a target specific
297 const char *getTargetNodeName(unsigned Opcode) const override;
299 /// getSetCCResultType - get the ISD::SETCC result ValueType
300 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
301 EVT VT) const override;
303 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
306 EmitInstrWithCustomInserter(MachineInstr &MI,
307 MachineBasicBlock *MBB) const override;
309 void HandleByVal(CCState *, unsigned &, unsigned) const override;
311 unsigned getRegisterByName(const char* RegName, EVT VT,
312 SelectionDAG &DAG) const override;
314 /// If a physical register, this returns the register that receives the
315 /// exception address on entry to an EH pad.
317 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
318 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
321 /// If a physical register, this returns the register that receives the
322 /// exception typeid on entry to a landing pad.
324 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
325 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
328 /// Returns true if a cast between SrcAS and DestAS is a noop.
329 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
330 // Mips doesn't have any special address spaces so we just reserve
331 // the first 256 for software use (e.g. OpenCL) and treat casts
332 // between them as noops.
333 return SrcAS < 256 && DestAS < 256;
336 bool isJumpTableRelative() const override {
337 return getTargetMachine().isPositionIndependent();
341 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
343 // This method creates the following nodes, which are necessary for
344 // computing a local symbol's address:
346 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
347 template <class NodeTy>
348 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
349 bool IsN32OrN64) const {
350 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
351 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
352 getTargetNode(N, Ty, DAG, GOTFlag));
354 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
355 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
356 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
357 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
358 getTargetNode(N, Ty, DAG, LoFlag));
359 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
362 // This method creates the following nodes, which are necessary for
363 // computing a global symbol's address:
365 // (load (wrapper $gp, %got(sym)))
366 template <class NodeTy>
367 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
368 unsigned Flag, SDValue Chain,
369 const MachinePointerInfo &PtrInfo) const {
370 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
371 getTargetNode(N, Ty, DAG, Flag));
372 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
375 // This method creates the following nodes, which are necessary for
376 // computing a global symbol's address in large-GOT mode:
378 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
379 template <class NodeTy>
380 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
381 SelectionDAG &DAG, unsigned HiFlag,
382 unsigned LoFlag, SDValue Chain,
383 const MachinePointerInfo &PtrInfo) const {
384 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
385 getTargetNode(N, Ty, DAG, HiFlag));
386 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
387 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
388 getTargetNode(N, Ty, DAG, LoFlag));
389 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
392 // This method creates the following nodes, which are necessary for
393 // computing a symbol's address in non-PIC mode:
395 // (add %hi(sym), %lo(sym))
397 // This method covers O32, N32 and N64 in sym32 mode.
398 template <class NodeTy>
399 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
400 SelectionDAG &DAG) const {
401 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
402 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
403 return DAG.getNode(ISD::ADD, DL, Ty,
404 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
405 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
408 // This method creates the following nodes, which are necessary for
409 // computing a symbol's address in non-PIC mode for N64.
411 // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
414 // FIXME: This method is not efficent for (micro)MIPS64R6.
415 template <class NodeTy>
416 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
417 SelectionDAG &DAG) const {
418 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
419 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
422 DAG.getNode(MipsISD::Highest, DL, Ty,
423 getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
424 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
426 DAG.getNode(ISD::ADD, DL, Ty, Highest,
427 DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
428 SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
429 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
430 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
431 DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
432 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
434 return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
435 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
438 // This method creates the following nodes, which are necessary for
439 // computing a symbol's address using gp-relative addressing:
441 // (add $gp, %gp_rel(sym))
442 template <class NodeTy>
443 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
444 SelectionDAG &DAG) const {
445 assert(Ty == MVT::i32);
446 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
447 return DAG.getNode(ISD::ADD, DL, Ty,
448 DAG.getRegister(Mips::GP, Ty),
449 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
453 /// This function fills Ops, which is the list of operands that will later
454 /// be used when a function call node is created. It also generates
455 /// copyToReg nodes to set up argument registers.
457 getOpndList(SmallVectorImpl<SDValue> &Ops,
458 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
459 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
460 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
461 SDValue Chain) const;
464 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
465 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
468 const MipsSubtarget &Subtarget;
469 // Cache the ABI from the TargetMachine, we use it everywhere.
470 const MipsABIInfo &ABI;
473 // Create a TargetGlobalAddress node.
474 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
475 unsigned Flag) const;
477 // Create a TargetExternalSymbol node.
478 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
479 unsigned Flag) const;
481 // Create a TargetBlockAddress node.
482 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
483 unsigned Flag) const;
485 // Create a TargetJumpTable node.
486 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
487 unsigned Flag) const;
489 // Create a TargetConstantPool node.
490 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
491 unsigned Flag) const;
493 // Lower Operand helpers
494 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
495 CallingConv::ID CallConv, bool isVarArg,
496 const SmallVectorImpl<ISD::InputArg> &Ins,
497 const SDLoc &dl, SelectionDAG &DAG,
498 SmallVectorImpl<SDValue> &InVals,
499 TargetLowering::CallLoweringInfo &CLI) const;
501 // Lower Operand specifics
502 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
503 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
504 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
505 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
506 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
507 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
508 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
509 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
510 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
511 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
512 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
513 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
514 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
515 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
516 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
517 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
518 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
519 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
521 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
522 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
524 /// isEligibleForTailCallOptimization - Check whether the call is eligible
525 /// for tail call optimization.
527 isEligibleForTailCallOptimization(const CCState &CCInfo,
528 unsigned NextStackOffset,
529 const MipsFunctionInfo &FI) const = 0;
531 /// copyByValArg - Copy argument registers which were used to pass a byval
532 /// argument to the stack. Create a stack frame object for the byval
534 void copyByValRegs(SDValue Chain, const SDLoc &DL,
535 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
536 const ISD::ArgFlagsTy &Flags,
537 SmallVectorImpl<SDValue> &InVals,
538 const Argument *FuncArg, unsigned FirstReg,
539 unsigned LastReg, const CCValAssign &VA,
540 MipsCCState &State) const;
542 /// passByValArg - Pass a byval argument in registers or on stack.
543 void passByValArg(SDValue Chain, const SDLoc &DL,
544 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
545 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
546 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
547 unsigned FirstReg, unsigned LastReg,
548 const ISD::ArgFlagsTy &Flags, bool isLittle,
549 const CCValAssign &VA) const;
551 /// writeVarArgRegs - Write variable function arguments passed in registers
552 /// to the stack. Also create a stack frame object for the first variable
554 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
555 const SDLoc &DL, SelectionDAG &DAG,
556 CCState &State) const;
559 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
560 const SmallVectorImpl<ISD::InputArg> &Ins,
561 const SDLoc &dl, SelectionDAG &DAG,
562 SmallVectorImpl<SDValue> &InVals) const override;
564 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
565 SDValue Arg, const SDLoc &DL, bool IsTailCall,
566 SelectionDAG &DAG) const;
568 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
569 SmallVectorImpl<SDValue> &InVals) const override;
571 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
573 const SmallVectorImpl<ISD::OutputArg> &Outs,
574 LLVMContext &Context) const override;
576 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
577 const SmallVectorImpl<ISD::OutputArg> &Outs,
578 const SmallVectorImpl<SDValue> &OutVals,
579 const SDLoc &dl, SelectionDAG &DAG) const override;
581 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
582 const SDLoc &DL, SelectionDAG &DAG) const;
584 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
586 // Inline asm support
587 ConstraintType getConstraintType(StringRef Constraint) const override;
589 /// Examine constraint string and operand type and determine a weight value.
590 /// The operand object must already have been set up with the operand type.
591 ConstraintWeight getSingleConstraintMatchWeight(
592 AsmOperandInfo &info, const char *constraint) const override;
594 /// This function parses registers that appear in inline-asm constraints.
595 /// It returns pair (0, 0) on failure.
596 std::pair<unsigned, const TargetRegisterClass *>
597 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
599 std::pair<unsigned, const TargetRegisterClass *>
600 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
601 StringRef Constraint, MVT VT) const override;
603 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
604 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
605 /// true it means one of the asm constraint of the inline asm instruction
606 /// being processed is 'm'.
607 void LowerAsmOperandForConstraint(SDValue Op,
608 std::string &Constraint,
609 std::vector<SDValue> &Ops,
610 SelectionDAG &DAG) const override;
613 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
614 if (ConstraintCode == "R")
615 return InlineAsm::Constraint_R;
616 else if (ConstraintCode == "ZC")
617 return InlineAsm::Constraint_ZC;
618 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
621 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
622 Type *Ty, unsigned AS) const override;
624 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
626 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
628 bool IsMemset, bool ZeroMemset,
630 MachineFunction &MF) const override;
632 /// isFPImmLegal - Returns true if the target can instruction select the
633 /// specified FP immediate natively. If false, the legalizer will
634 /// materialize the FP immediate as a load from a constant pool.
635 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
637 unsigned getJumpTableEncoding() const override;
638 bool useSoftFloat() const override;
640 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
644 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
645 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
646 MachineBasicBlock *BB,
647 unsigned Size, unsigned DstReg,
648 unsigned SrcRec) const;
650 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
651 unsigned Size, unsigned BinOpcode,
652 bool Nand = false) const;
653 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
654 MachineBasicBlock *BB,
657 bool Nand = false) const;
658 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
659 MachineBasicBlock *BB,
660 unsigned Size) const;
661 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
662 MachineBasicBlock *BB,
663 unsigned Size) const;
664 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
665 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
666 bool isFPCmp, unsigned Opc) const;
669 /// Create MipsTargetLowering objects.
670 const MipsTargetLowering *
671 createMips16TargetLowering(const MipsTargetMachine &TM,
672 const MipsSubtarget &STI);
673 const MipsTargetLowering *
674 createMipsSETargetLowering(const MipsTargetMachine &TM,
675 const MipsSubtarget &STI);
678 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
679 const TargetLibraryInfo *libInfo);