1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "MCTargetDesc/MipsMCTargetDesc.h"
22 #include "llvm/CodeGen/ISDOpcodes.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineValueType.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/TargetLowering.h"
28 #include "llvm/CodeGen/ValueTypes.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Target/TargetMachine.h"
46 class FunctionLoweringInfo;
47 class MachineBasicBlock;
48 class MachineFrameInfo;
51 class MipsFunctionInfo;
53 class MipsTargetMachine;
54 class TargetLibraryInfo;
55 class TargetRegisterClass;
59 enum NodeType : unsigned {
60 // Start the numbering from where ISD NodeType finishes.
61 FIRST_NUMBER = ISD::BUILTIN_OP_END,
63 // Jump and link (call)
69 // Get the Highest (63-48) 16 bits from a 64-bit immediate
72 // Get the Higher (47-32) 16 bits from a 64-bit immediate
75 // Get the High 16 bits from a 32/64-bit immediate
76 // No relation with Mips Hi register
79 // Get the Lower 16 bits from a 32/64-bit immediate
80 // No relation with Mips Lo register
83 // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
86 // Handle gp_rel (small data/bss sections) relocation.
92 // Floating Point Branch Conditional
95 // Floating Point Compare
98 // Floating point select
101 // Node used to generate an MTC1 i32 to f64 instruction
104 // Floating Point Conditional Moves
108 // FP-to-int truncation node.
114 // Interrupt, exception, error trap Return
117 // Software Exception Return.
120 // Node used to extract integer from accumulator.
124 // Node used to insert integers to accumulator.
156 // EXTR.W instrinsic nodes.
166 // DPA.W intrinsic nodes.
202 // DSP setcc and select_cc nodes.
206 // Vector comparisons.
207 // These take a vector and return a boolean.
213 // These take a vector and return a vector bitmask.
220 // Element-wise vector max/min.
226 // Vector Shuffle with mask as an operand
227 VSHF, // Generic shuffle
228 SHF, // 4-element set shuffle.
229 ILVEV, // Interleave even elements
230 ILVOD, // Interleave odd elements
231 ILVL, // Interleave left elements
232 ILVR, // Interleave right elements
233 PCKEV, // Pack even elements
234 PCKOD, // Pack odd elements
237 INSVE, // Copy element from one vector to another
239 // Combined (XOR (OR $a, $b), -1)
242 // Extended vector element extraction
246 // Load/Store Left/Right nodes.
247 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
257 } // ene namespace MipsISD
259 //===--------------------------------------------------------------------===//
260 // TargetLowering Implementation
261 //===--------------------------------------------------------------------===//
263 class MipsTargetLowering : public TargetLowering {
267 explicit MipsTargetLowering(const MipsTargetMachine &TM,
268 const MipsSubtarget &STI);
270 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
271 const MipsSubtarget &STI);
273 /// createFastISel - This method returns a target specific FastISel object,
274 /// or null if the target does not support "fast" ISel.
275 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
276 const TargetLibraryInfo *libInfo) const override;
278 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
282 bool isCheapToSpeculateCttz() const override;
283 bool isCheapToSpeculateCtlz() const override;
285 /// Return the register type for a given MVT, ensuring vectors are treated
286 /// as a series of gpr sized integers.
287 MVT getRegisterTypeForCallingConv(MVT VT) const override;
289 /// Return the register type for a given MVT, ensuring vectors are treated
290 /// as a series of gpr sized integers.
291 MVT getRegisterTypeForCallingConv(LLVMContext &Context,
292 EVT VT) const override;
294 /// Return the number of registers for a given MVT, ensuring vectors are
295 /// treated as a series of gpr sized integers.
296 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
297 EVT VT) const override;
299 /// Break down vectors to the correct number of gpr sized integers.
300 unsigned getVectorTypeBreakdownForCallingConv(
301 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
302 unsigned &NumIntermediates, MVT &RegisterVT) const override;
304 /// Return the correct alignment for the current calling convention.
305 unsigned getABIAlignmentForCallingConv(Type *ArgTy,
306 DataLayout DL) const override {
307 if (ArgTy->isVectorTy())
308 return std::min(DL.getABITypeAlignment(ArgTy), 8U);
309 return DL.getABITypeAlignment(ArgTy);
312 ISD::NodeType getExtendForAtomicOps() const override {
313 return ISD::SIGN_EXTEND;
316 void LowerOperationWrapper(SDNode *N,
317 SmallVectorImpl<SDValue> &Results,
318 SelectionDAG &DAG) const override;
320 /// LowerOperation - Provide custom lowering hooks for some operations.
321 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
323 /// ReplaceNodeResults - Replace the results of node with an illegal result
324 /// type with new values built out of custom code.
326 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
327 SelectionDAG &DAG) const override;
329 /// getTargetNodeName - This method returns the name of a target specific
331 const char *getTargetNodeName(unsigned Opcode) const override;
333 /// getSetCCResultType - get the ISD::SETCC result ValueType
334 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
335 EVT VT) const override;
337 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
340 EmitInstrWithCustomInserter(MachineInstr &MI,
341 MachineBasicBlock *MBB) const override;
343 void HandleByVal(CCState *, unsigned &, unsigned) const override;
345 unsigned getRegisterByName(const char* RegName, EVT VT,
346 SelectionDAG &DAG) const override;
348 /// If a physical register, this returns the register that receives the
349 /// exception address on entry to an EH pad.
351 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
352 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
355 /// If a physical register, this returns the register that receives the
356 /// exception typeid on entry to a landing pad.
358 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
359 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
362 /// Returns true if a cast between SrcAS and DestAS is a noop.
363 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
364 // Mips doesn't have any special address spaces so we just reserve
365 // the first 256 for software use (e.g. OpenCL) and treat casts
366 // between them as noops.
367 return SrcAS < 256 && DestAS < 256;
370 bool isJumpTableRelative() const override {
371 return getTargetMachine().isPositionIndependent();
375 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
377 // This method creates the following nodes, which are necessary for
378 // computing a local symbol's address:
380 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
381 template <class NodeTy>
382 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
383 bool IsN32OrN64) const {
384 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
385 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
386 getTargetNode(N, Ty, DAG, GOTFlag));
388 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
389 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
390 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
391 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
392 getTargetNode(N, Ty, DAG, LoFlag));
393 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
396 // This method creates the following nodes, which are necessary for
397 // computing a global symbol's address:
399 // (load (wrapper $gp, %got(sym)))
400 template <class NodeTy>
401 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
402 unsigned Flag, SDValue Chain,
403 const MachinePointerInfo &PtrInfo) const {
404 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
405 getTargetNode(N, Ty, DAG, Flag));
406 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
409 // This method creates the following nodes, which are necessary for
410 // computing a global symbol's address in large-GOT mode:
412 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
413 template <class NodeTy>
414 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
415 SelectionDAG &DAG, unsigned HiFlag,
416 unsigned LoFlag, SDValue Chain,
417 const MachinePointerInfo &PtrInfo) const {
418 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
419 getTargetNode(N, Ty, DAG, HiFlag));
420 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
421 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
422 getTargetNode(N, Ty, DAG, LoFlag));
423 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
426 // This method creates the following nodes, which are necessary for
427 // computing a symbol's address in non-PIC mode:
429 // (add %hi(sym), %lo(sym))
431 // This method covers O32, N32 and N64 in sym32 mode.
432 template <class NodeTy>
433 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
434 SelectionDAG &DAG) const {
435 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
436 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
437 return DAG.getNode(ISD::ADD, DL, Ty,
438 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
439 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
442 // This method creates the following nodes, which are necessary for
443 // computing a symbol's address in non-PIC mode for N64.
445 // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
448 // FIXME: This method is not efficent for (micro)MIPS64R6.
449 template <class NodeTy>
450 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
451 SelectionDAG &DAG) const {
452 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
453 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
456 DAG.getNode(MipsISD::Highest, DL, Ty,
457 getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
458 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
460 DAG.getNode(ISD::ADD, DL, Ty, Highest,
461 DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
462 SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
463 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
464 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
465 DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
466 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
468 return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
469 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
472 // This method creates the following nodes, which are necessary for
473 // computing a symbol's address using gp-relative addressing:
475 // (add $gp, %gp_rel(sym))
476 template <class NodeTy>
477 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
478 SelectionDAG &DAG, bool IsN64) const {
479 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
482 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
483 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
486 /// This function fills Ops, which is the list of operands that will later
487 /// be used when a function call node is created. It also generates
488 /// copyToReg nodes to set up argument registers.
490 getOpndList(SmallVectorImpl<SDValue> &Ops,
491 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
492 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
493 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
494 SDValue Chain) const;
497 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
498 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
501 const MipsSubtarget &Subtarget;
502 // Cache the ABI from the TargetMachine, we use it everywhere.
503 const MipsABIInfo &ABI;
506 // Create a TargetGlobalAddress node.
507 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
508 unsigned Flag) const;
510 // Create a TargetExternalSymbol node.
511 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
512 unsigned Flag) const;
514 // Create a TargetBlockAddress node.
515 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
516 unsigned Flag) const;
518 // Create a TargetJumpTable node.
519 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
520 unsigned Flag) const;
522 // Create a TargetConstantPool node.
523 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
524 unsigned Flag) const;
526 // Lower Operand helpers
527 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
528 CallingConv::ID CallConv, bool isVarArg,
529 const SmallVectorImpl<ISD::InputArg> &Ins,
530 const SDLoc &dl, SelectionDAG &DAG,
531 SmallVectorImpl<SDValue> &InVals,
532 TargetLowering::CallLoweringInfo &CLI) const;
534 // Lower Operand specifics
535 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
536 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
537 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
538 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
539 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
542 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
543 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
544 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
547 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
548 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
549 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
550 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
551 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
552 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
554 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
555 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
557 /// isEligibleForTailCallOptimization - Check whether the call is eligible
558 /// for tail call optimization.
560 isEligibleForTailCallOptimization(const CCState &CCInfo,
561 unsigned NextStackOffset,
562 const MipsFunctionInfo &FI) const = 0;
564 /// copyByValArg - Copy argument registers which were used to pass a byval
565 /// argument to the stack. Create a stack frame object for the byval
567 void copyByValRegs(SDValue Chain, const SDLoc &DL,
568 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
569 const ISD::ArgFlagsTy &Flags,
570 SmallVectorImpl<SDValue> &InVals,
571 const Argument *FuncArg, unsigned FirstReg,
572 unsigned LastReg, const CCValAssign &VA,
573 MipsCCState &State) const;
575 /// passByValArg - Pass a byval argument in registers or on stack.
576 void passByValArg(SDValue Chain, const SDLoc &DL,
577 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
578 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
579 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
580 unsigned FirstReg, unsigned LastReg,
581 const ISD::ArgFlagsTy &Flags, bool isLittle,
582 const CCValAssign &VA) const;
584 /// writeVarArgRegs - Write variable function arguments passed in registers
585 /// to the stack. Also create a stack frame object for the first variable
587 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
588 const SDLoc &DL, SelectionDAG &DAG,
589 CCState &State) const;
592 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
593 const SmallVectorImpl<ISD::InputArg> &Ins,
594 const SDLoc &dl, SelectionDAG &DAG,
595 SmallVectorImpl<SDValue> &InVals) const override;
597 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
598 SDValue Arg, const SDLoc &DL, bool IsTailCall,
599 SelectionDAG &DAG) const;
601 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
602 SmallVectorImpl<SDValue> &InVals) const override;
604 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
606 const SmallVectorImpl<ISD::OutputArg> &Outs,
607 LLVMContext &Context) const override;
609 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
610 const SmallVectorImpl<ISD::OutputArg> &Outs,
611 const SmallVectorImpl<SDValue> &OutVals,
612 const SDLoc &dl, SelectionDAG &DAG) const override;
614 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
615 const SDLoc &DL, SelectionDAG &DAG) const;
617 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
619 // Inline asm support
620 ConstraintType getConstraintType(StringRef Constraint) const override;
622 /// Examine constraint string and operand type and determine a weight value.
623 /// The operand object must already have been set up with the operand type.
624 ConstraintWeight getSingleConstraintMatchWeight(
625 AsmOperandInfo &info, const char *constraint) const override;
627 /// This function parses registers that appear in inline-asm constraints.
628 /// It returns pair (0, 0) on failure.
629 std::pair<unsigned, const TargetRegisterClass *>
630 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
632 std::pair<unsigned, const TargetRegisterClass *>
633 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
634 StringRef Constraint, MVT VT) const override;
636 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
637 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
638 /// true it means one of the asm constraint of the inline asm instruction
639 /// being processed is 'm'.
640 void LowerAsmOperandForConstraint(SDValue Op,
641 std::string &Constraint,
642 std::vector<SDValue> &Ops,
643 SelectionDAG &DAG) const override;
646 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
647 if (ConstraintCode == "R")
648 return InlineAsm::Constraint_R;
649 else if (ConstraintCode == "ZC")
650 return InlineAsm::Constraint_ZC;
651 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
654 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
655 Type *Ty, unsigned AS,
656 Instruction *I = nullptr) const override;
658 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
660 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
662 bool IsMemset, bool ZeroMemset,
664 MachineFunction &MF) const override;
666 /// isFPImmLegal - Returns true if the target can instruction select the
667 /// specified FP immediate natively. If false, the legalizer will
668 /// materialize the FP immediate as a load from a constant pool.
669 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
671 unsigned getJumpTableEncoding() const override;
672 bool useSoftFloat() const override;
674 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
678 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
679 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
680 MachineBasicBlock *BB,
681 unsigned Size, unsigned DstReg,
682 unsigned SrcRec) const;
684 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
685 unsigned Size, unsigned BinOpcode,
686 bool Nand = false) const;
687 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
688 MachineBasicBlock *BB,
691 bool Nand = false) const;
692 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
693 MachineBasicBlock *BB,
694 unsigned Size) const;
695 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
696 MachineBasicBlock *BB,
697 unsigned Size) const;
698 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
699 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
700 bool isFPCmp, unsigned Opc) const;
703 /// Create MipsTargetLowering objects.
704 const MipsTargetLowering *
705 createMips16TargetLowering(const MipsTargetMachine &TM,
706 const MipsSubtarget &STI);
707 const MipsTargetLowering *
708 createMipsSETargetLowering(const MipsTargetMachine &TM,
709 const MipsSubtarget &STI);
713 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
714 const TargetLibraryInfo *libInfo);
716 } // end namespace Mips
718 } // end namespace llvm
720 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H