1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Target/TargetLowering.h"
30 enum NodeType : unsigned {
31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 // Jump and link (call)
40 // Get the Higher 16 bits from a 32-bit immediate
41 // No relation with Mips Hi register
44 // Get the Lower 16 bits from a 32-bit immediate
45 // No relation with Mips Lo register
48 // Handle gp_rel (small data/bss sections) relocation.
54 // Floating Point Branch Conditional
57 // Floating Point Compare
60 // Floating Point Conditional Moves
64 // FP-to-int truncation node.
70 // Interrupt, exception, error trap Return
73 // Software Exception Return.
76 // Node used to extract integer from accumulator.
80 // Node used to insert integers to accumulator.
111 // EXTR.W instrinsic nodes.
121 // DPA.W intrinsic nodes.
157 // DSP setcc and select_cc nodes.
161 // Vector comparisons.
162 // These take a vector and return a boolean.
168 // These take a vector and return a vector bitmask.
175 // Element-wise vector max/min.
181 // Vector Shuffle with mask as an operand
182 VSHF, // Generic shuffle
183 SHF, // 4-element set shuffle.
184 ILVEV, // Interleave even elements
185 ILVOD, // Interleave odd elements
186 ILVL, // Interleave left elements
187 ILVR, // Interleave right elements
188 PCKEV, // Pack even elements
189 PCKOD, // Pack odd elements
192 INSVE, // Copy element from one vector to another
194 // Combined (XOR (OR $a, $b), -1)
197 // Extended vector element extraction
201 // Load/Store Left/Right nodes.
202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
213 //===--------------------------------------------------------------------===//
214 // TargetLowering Implementation
215 //===--------------------------------------------------------------------===//
216 class MipsFunctionInfo;
220 class MipsTargetLowering : public TargetLowering {
223 explicit MipsTargetLowering(const MipsTargetMachine &TM,
224 const MipsSubtarget &STI);
226 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
227 const MipsSubtarget &STI);
229 /// createFastISel - This method returns a target specific FastISel object,
230 /// or null if the target does not support "fast" ISel.
231 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
232 const TargetLibraryInfo *libInfo) const override;
234 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
238 bool isCheapToSpeculateCttz() const override;
239 bool isCheapToSpeculateCtlz() const override;
241 ISD::NodeType getExtendForAtomicOps() const override {
242 return ISD::SIGN_EXTEND;
245 void LowerOperationWrapper(SDNode *N,
246 SmallVectorImpl<SDValue> &Results,
247 SelectionDAG &DAG) const override;
249 /// LowerOperation - Provide custom lowering hooks for some operations.
250 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
252 /// ReplaceNodeResults - Replace the results of node with an illegal result
253 /// type with new values built out of custom code.
255 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
256 SelectionDAG &DAG) const override;
258 /// getTargetNodeName - This method returns the name of a target specific
260 const char *getTargetNodeName(unsigned Opcode) const override;
262 /// getSetCCResultType - get the ISD::SETCC result ValueType
263 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
264 EVT VT) const override;
266 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
269 EmitInstrWithCustomInserter(MachineInstr &MI,
270 MachineBasicBlock *MBB) const override;
272 void HandleByVal(CCState *, unsigned &, unsigned) const override;
274 unsigned getRegisterByName(const char* RegName, EVT VT,
275 SelectionDAG &DAG) const override;
277 /// If a physical register, this returns the register that receives the
278 /// exception address on entry to an EH pad.
280 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
281 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
284 /// If a physical register, this returns the register that receives the
285 /// exception typeid on entry to a landing pad.
287 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
288 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
291 /// Returns true if a cast between SrcAS and DestAS is a noop.
292 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
293 // Mips doesn't have any special address spaces so we just reserve
294 // the first 256 for software use (e.g. OpenCL) and treat casts
295 // between them as noops.
296 return SrcAS < 256 && DestAS < 256;
299 bool isJumpTableRelative() const override {
300 return getTargetMachine().isPositionIndependent() || ABI.IsN64();
304 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
306 // This method creates the following nodes, which are necessary for
307 // computing a local symbol's address:
309 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
310 template <class NodeTy>
311 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
312 bool IsN32OrN64) const {
313 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
314 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
315 getTargetNode(N, Ty, DAG, GOTFlag));
317 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
318 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
319 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
320 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
321 getTargetNode(N, Ty, DAG, LoFlag));
322 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
325 // This method creates the following nodes, which are necessary for
326 // computing a global symbol's address:
328 // (load (wrapper $gp, %got(sym)))
329 template <class NodeTy>
330 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
331 unsigned Flag, SDValue Chain,
332 const MachinePointerInfo &PtrInfo) const {
333 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
334 getTargetNode(N, Ty, DAG, Flag));
335 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
338 // This method creates the following nodes, which are necessary for
339 // computing a global symbol's address in large-GOT mode:
341 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
342 template <class NodeTy>
343 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
344 SelectionDAG &DAG, unsigned HiFlag,
345 unsigned LoFlag, SDValue Chain,
346 const MachinePointerInfo &PtrInfo) const {
348 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
349 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
350 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
351 getTargetNode(N, Ty, DAG, LoFlag));
352 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
355 // This method creates the following nodes, which are necessary for
356 // computing a symbol's address in non-PIC mode:
358 // (add %hi(sym), %lo(sym))
359 template <class NodeTy>
360 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
361 SelectionDAG &DAG) const {
362 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
363 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
364 return DAG.getNode(ISD::ADD, DL, Ty,
365 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
366 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
369 // This method creates the following nodes, which are necessary for
370 // computing a symbol's address using gp-relative addressing:
372 // (add $gp, %gp_rel(sym))
373 template <class NodeTy>
374 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
375 SelectionDAG &DAG) const {
376 assert(Ty == MVT::i32);
377 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
378 return DAG.getNode(ISD::ADD, DL, Ty,
379 DAG.getRegister(Mips::GP, Ty),
380 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
384 /// This function fills Ops, which is the list of operands that will later
385 /// be used when a function call node is created. It also generates
386 /// copyToReg nodes to set up argument registers.
388 getOpndList(SmallVectorImpl<SDValue> &Ops,
389 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
390 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
391 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
392 SDValue Chain) const;
395 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
396 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
399 const MipsSubtarget &Subtarget;
400 // Cache the ABI from the TargetMachine, we use it everywhere.
401 const MipsABIInfo &ABI;
404 // Create a TargetGlobalAddress node.
405 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
406 unsigned Flag) const;
408 // Create a TargetExternalSymbol node.
409 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
410 unsigned Flag) const;
412 // Create a TargetBlockAddress node.
413 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
414 unsigned Flag) const;
416 // Create a TargetJumpTable node.
417 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
418 unsigned Flag) const;
420 // Create a TargetConstantPool node.
421 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
422 unsigned Flag) const;
424 // Lower Operand helpers
425 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
426 CallingConv::ID CallConv, bool isVarArg,
427 const SmallVectorImpl<ISD::InputArg> &Ins,
428 const SDLoc &dl, SelectionDAG &DAG,
429 SmallVectorImpl<SDValue> &InVals,
430 TargetLowering::CallLoweringInfo &CLI) const;
432 // Lower Operand specifics
433 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
434 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
435 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
436 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
437 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
438 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
439 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
440 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
441 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
442 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
443 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
444 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
445 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
446 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
447 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
448 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
449 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
450 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
452 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
453 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
455 /// isEligibleForTailCallOptimization - Check whether the call is eligible
456 /// for tail call optimization.
458 isEligibleForTailCallOptimization(const CCState &CCInfo,
459 unsigned NextStackOffset,
460 const MipsFunctionInfo &FI) const = 0;
462 /// copyByValArg - Copy argument registers which were used to pass a byval
463 /// argument to the stack. Create a stack frame object for the byval
465 void copyByValRegs(SDValue Chain, const SDLoc &DL,
466 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
467 const ISD::ArgFlagsTy &Flags,
468 SmallVectorImpl<SDValue> &InVals,
469 const Argument *FuncArg, unsigned FirstReg,
470 unsigned LastReg, const CCValAssign &VA,
471 MipsCCState &State) const;
473 /// passByValArg - Pass a byval argument in registers or on stack.
474 void passByValArg(SDValue Chain, const SDLoc &DL,
475 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
476 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
477 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
478 unsigned FirstReg, unsigned LastReg,
479 const ISD::ArgFlagsTy &Flags, bool isLittle,
480 const CCValAssign &VA) const;
482 /// writeVarArgRegs - Write variable function arguments passed in registers
483 /// to the stack. Also create a stack frame object for the first variable
485 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
486 const SDLoc &DL, SelectionDAG &DAG,
487 CCState &State) const;
490 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
491 const SmallVectorImpl<ISD::InputArg> &Ins,
492 const SDLoc &dl, SelectionDAG &DAG,
493 SmallVectorImpl<SDValue> &InVals) const override;
495 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
496 SDValue Arg, const SDLoc &DL, bool IsTailCall,
497 SelectionDAG &DAG) const;
499 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
500 SmallVectorImpl<SDValue> &InVals) const override;
502 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
504 const SmallVectorImpl<ISD::OutputArg> &Outs,
505 LLVMContext &Context) const override;
507 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
508 const SmallVectorImpl<ISD::OutputArg> &Outs,
509 const SmallVectorImpl<SDValue> &OutVals,
510 const SDLoc &dl, SelectionDAG &DAG) const override;
512 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
513 const SDLoc &DL, SelectionDAG &DAG) const;
515 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
517 // Inline asm support
518 ConstraintType getConstraintType(StringRef Constraint) const override;
520 /// Examine constraint string and operand type and determine a weight value.
521 /// The operand object must already have been set up with the operand type.
522 ConstraintWeight getSingleConstraintMatchWeight(
523 AsmOperandInfo &info, const char *constraint) const override;
525 /// This function parses registers that appear in inline-asm constraints.
526 /// It returns pair (0, 0) on failure.
527 std::pair<unsigned, const TargetRegisterClass *>
528 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
530 std::pair<unsigned, const TargetRegisterClass *>
531 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
532 StringRef Constraint, MVT VT) const override;
534 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
535 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
536 /// true it means one of the asm constraint of the inline asm instruction
537 /// being processed is 'm'.
538 void LowerAsmOperandForConstraint(SDValue Op,
539 std::string &Constraint,
540 std::vector<SDValue> &Ops,
541 SelectionDAG &DAG) const override;
544 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
545 if (ConstraintCode == "R")
546 return InlineAsm::Constraint_R;
547 else if (ConstraintCode == "ZC")
548 return InlineAsm::Constraint_ZC;
549 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
552 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
553 Type *Ty, unsigned AS) const override;
555 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
557 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
559 bool IsMemset, bool ZeroMemset,
561 MachineFunction &MF) const override;
563 /// isFPImmLegal - Returns true if the target can instruction select the
564 /// specified FP immediate natively. If false, the legalizer will
565 /// materialize the FP immediate as a load from a constant pool.
566 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
568 unsigned getJumpTableEncoding() const override;
569 bool useSoftFloat() const override;
571 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
575 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
576 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
577 MachineBasicBlock *BB,
578 unsigned Size, unsigned DstReg,
579 unsigned SrcRec) const;
581 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
582 unsigned Size, unsigned BinOpcode,
583 bool Nand = false) const;
584 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
585 MachineBasicBlock *BB,
588 bool Nand = false) const;
589 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
590 MachineBasicBlock *BB,
591 unsigned Size) const;
592 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
593 MachineBasicBlock *BB,
594 unsigned Size) const;
595 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
596 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
597 bool isFPCmp, unsigned Opc) const;
600 /// Create MipsTargetLowering objects.
601 const MipsTargetLowering *
602 createMips16TargetLowering(const MipsTargetMachine &TM,
603 const MipsSubtarget &STI);
604 const MipsTargetLowering *
605 createMipsSETargetLowering(const MipsTargetMachine &TM,
606 const MipsSubtarget &STI);
609 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
610 const TargetLibraryInfo *libInfo);