1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
42 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
43 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
44 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
45 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
46 [SDNPHasChain, SDNPOptInGlue]>;
47 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
48 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
49 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
50 SDT_MipsExtractElementF64>;
52 // Operand for printing out a condition code.
53 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
54 def condcode : Operand<i32>;
56 //===----------------------------------------------------------------------===//
57 // Feature predicates.
58 //===----------------------------------------------------------------------===//
60 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
61 AssemblerPredicate<"FeatureFP64Bit">;
62 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
63 AssemblerPredicate<"!FeatureFP64Bit">;
64 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
65 AssemblerPredicate<"FeatureSingleFloat">;
66 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
67 AssemblerPredicate<"!FeatureSingleFloat">;
68 def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">,
69 AssemblerPredicate<"!FeatureSoftFloat">;
71 //===----------------------------------------------------------------------===//
72 // Mips FGR size adjectives.
73 // They are mutually exclusive.
74 //===----------------------------------------------------------------------===//
76 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
77 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
78 class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; }
80 //===----------------------------------------------------------------------===//
82 // FP immediate patterns.
83 def fpimm0 : PatLeaf<(fpimm), [{
84 return N->isExactlyValue(+0.0);
87 def fpimm0neg : PatLeaf<(fpimm), [{
88 return N->isExactlyValue(-0.0);
91 //===----------------------------------------------------------------------===//
92 // Instruction Class Templates
94 // A set of multiclasses is used to address the register usage.
96 // S32 - single precision in 16 32bit even fp registers
97 // single precision in 32 32bit fp registers in SingleOnly mode
98 // S64 - single precision in 32 64bit fp registers (In64BitMode)
99 // D32 - double precision in 16 32bit even fp registers
100 // D64 - double precision in 32 64bit fp registers (In64BitMode)
102 // Only S32 and D32 are supported right now.
103 //===----------------------------------------------------------------------===//
104 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
105 SDPatternOperator OpNode= null_frag> :
106 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
107 !strconcat(opstr, "\t$fd, $fs, $ft"),
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
110 let isCommutable = IsComm;
113 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
114 SDPatternOperator OpNode = null_frag> {
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
117 string DecoderNamespace = "Mips64";
121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
128 multiclass ABSS_M<string opstr, InstrItinClass Itin,
129 SDPatternOperator OpNode= null_frag> {
130 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
132 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
133 string DecoderNamespace = "Mips64";
137 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
139 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
140 let DecoderNamespace = "Mips64";
144 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
145 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
149 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
154 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
155 InstrItinClass Itin> :
156 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
157 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {
158 // $fs_in is part of a white lie to work around a widespread bug in the FPU
159 // implementation. See expandBuildPairF64 for details.
160 let Constraints = "$fs = $fs_in";
163 class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
164 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
165 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
166 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
168 let DecoderMethod = "DecodeFMem";
172 class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
173 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
174 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
175 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
176 let DecoderMethod = "DecodeFMem";
180 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
181 SDPatternOperator OpNode = null_frag> :
182 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
183 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
184 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
185 FrmFR, opstr>, HARDFLOAT;
187 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
188 SDPatternOperator OpNode = null_frag> :
189 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
190 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
191 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
192 Itin, FrmFR, opstr>, HARDFLOAT;
194 class LWXC1_FT<string opstr, RegisterOperand DRC,
195 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
196 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
197 !strconcat(opstr, "\t$fd, ${index}(${base})"),
198 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
199 FrmFI, opstr>, HARDFLOAT {
200 let AddedComplexity = 20;
203 class SWXC1_FT<string opstr, RegisterOperand DRC,
204 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
205 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
206 !strconcat(opstr, "\t$fs, ${index}(${base})"),
207 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
208 FrmFI, opstr>, HARDFLOAT {
209 let AddedComplexity = 20;
212 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
213 SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
214 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
215 !strconcat(opstr, "\t$fcc, $offset"),
216 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
217 FrmFI, opstr>, HARDFLOAT {
219 let isTerminator = 1;
220 let hasDelaySlot = DelaySlot;
222 let hasFCCRegOperand = 1;
225 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
226 SDPatternOperator OpNode = null_frag> :
227 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
228 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
229 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
230 !strconcat("c.$cond.", typestr)>, HARDFLOAT {
232 let isCodeGenOnly = 1;
233 let hasFCCRegOperand = 1;
237 // Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather
238 // duplicating the instruction definition for MIPS1 - MIPS3, we expand
239 // c.cond.ft if necessary, and reject it after constructing the
240 // instruction if the ISA doesn't support it.
241 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
242 InstrItinClass itin> :
243 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
244 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,
247 let hasFCCRegOperand = 1;
251 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
252 InstrItinClass itin> {
253 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
255 let BaseOpcode = "c.f."#NAME;
256 let isCommutable = 1;
258 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
260 let BaseOpcode = "c.un."#NAME;
261 let isCommutable = 1;
263 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
265 let BaseOpcode = "c.eq."#NAME;
266 let isCommutable = 1;
268 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
270 let BaseOpcode = "c.ueq."#NAME;
271 let isCommutable = 1;
273 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
275 let BaseOpcode = "c.olt."#NAME;
277 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
279 let BaseOpcode = "c.ult."#NAME;
281 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
283 let BaseOpcode = "c.ole."#NAME;
285 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
287 let BaseOpcode = "c.ule."#NAME;
289 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
291 let BaseOpcode = "c.sf."#NAME;
292 let isCommutable = 1;
294 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
296 let BaseOpcode = "c.ngle."#NAME;
298 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
300 let BaseOpcode = "c.seq."#NAME;
301 let isCommutable = 1;
303 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
305 let BaseOpcode = "c.ngl."#NAME;
307 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
309 let BaseOpcode = "c.lt."#NAME;
311 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
313 let BaseOpcode = "c.nge."#NAME;
315 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
317 let BaseOpcode = "c.le."#NAME;
319 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
321 let BaseOpcode = "c.ngt."#NAME;
325 let AdditionalPredicates = [NotInMicroMips] in {
326 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
327 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
329 let DecoderNamespace = "Mips64" in
330 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
333 //===----------------------------------------------------------------------===//
334 // Floating Point Instructions
335 //===----------------------------------------------------------------------===//
336 def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
337 ABSS_FM<0xc, 16>, ISA_MIPS2;
338 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
339 def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
340 ABSS_FM<0xd, 16>, ISA_MIPS2;
341 def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
342 ABSS_FM<0xe, 16>, ISA_MIPS2;
343 def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
344 ABSS_FM<0xf, 16>, ISA_MIPS2;
345 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
348 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
349 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
350 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
351 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
353 let AdditionalPredicates = [NotInMicroMips] in {
354 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
355 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
356 def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
357 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
358 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
359 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
360 def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
361 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
363 let DecoderNamespace = "Mips64" in {
364 let AdditionalPredicates = [NotInMicroMips] in {
365 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
366 ABSS_FM<0x8, 16>, FGR_64;
367 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
368 ABSS_FM<0x8, 17>, FGR_64;
369 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
370 ABSS_FM<0x9, 16>, FGR_64;
371 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
372 ABSS_FM<0x9, 17>, FGR_64;
373 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
374 ABSS_FM<0xa, 16>, FGR_64;
375 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
376 ABSS_FM<0xa, 17>, FGR_64;
377 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
378 ABSS_FM<0xb, 16>, FGR_64;
379 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
380 ABSS_FM<0xb, 17>, FGR_64;
384 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
386 let AdditionalPredicates = [NotInMicroMips] in{
387 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
388 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
389 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
390 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
393 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
394 ABSS_FM<0x20, 17>, FGR_32;
395 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
396 ABSS_FM<0x21, 20>, FGR_32;
397 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
398 ABSS_FM<0x21, 16>, FGR_32;
400 let DecoderNamespace = "Mips64" in {
401 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
402 ABSS_FM<0x20, 17>, FGR_64;
403 let AdditionalPredicates = [NotInMicroMips] in{
404 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
405 ABSS_FM<0x20, 21>, FGR_64;
407 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
408 ABSS_FM<0x21, 20>, FGR_64;
409 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
410 ABSS_FM<0x21, 16>, FGR_64;
411 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
412 ABSS_FM<0x21, 21>, FGR_64;
415 let isPseudo = 1, isCodeGenOnly = 1 in {
416 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
417 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
418 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
419 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
420 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
423 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
425 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
427 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
428 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
430 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
431 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
432 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
434 // The odd-numbered registers are only referenced when doing loads,
435 // stores, and moves between floating-point and integer registers.
436 // When defining instructions, we reference all 32-bit registers,
437 // regardless of register aliasing.
439 /// Move Control Registers From/To CPU Registers
440 let AdditionalPredicates = [NotInMicroMips] in {
441 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
442 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
444 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
445 bitconvert>, MFC1_FM<0>;
446 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
448 let DecoderNamespace = "Mips64";
450 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
451 bitconvert>, MFC1_FM<4>;
452 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
454 let DecoderNamespace = "Mips64";
457 let AdditionalPredicates = [NotInMicroMips] in {
458 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
459 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
460 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
461 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
462 let DecoderNamespace = "Mips64";
465 let AdditionalPredicates = [NotInMicroMips] in {
466 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
467 MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
468 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
469 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
470 let DecoderNamespace = "Mips64";
473 let AdditionalPredicates = [NotInMicroMips] in {
474 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
475 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
476 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
477 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
480 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
482 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
483 ABSS_FM<0x6, 17>, FGR_32;
484 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
485 ABSS_FM<0x6, 17>, FGR_64 {
486 let DecoderNamespace = "Mips64";
489 /// Floating Point Memory Instructions
490 let AdditionalPredicates = [NotInMicroMips] in {
491 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
493 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
497 let DecoderNamespace = "Mips64", AdditionalPredicates = [NotInMicroMips] in {
498 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
499 LW_FM<0x35>, ISA_MIPS2, FGR_64 {
500 let BaseOpcode = "LDC164";
502 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,
503 LW_FM<0x3d>, ISA_MIPS2, FGR_64;
506 let AdditionalPredicates = [NotInMicroMips] in {
507 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
508 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 {
509 let BaseOpcode = "LDC132";
511 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
512 LW_FM<0x3d>, ISA_MIPS2, FGR_32;
515 // Indexed loads and stores.
516 // Base register + offset register addressing mode (indicated by "x" in the
517 // instruction mnemonic) is disallowed under NaCl.
518 let AdditionalPredicates = [IsNotNaCl] in {
519 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
520 INSN_MIPS4_32R2_NOT_32R6_64R6;
521 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
522 INSN_MIPS4_32R2_NOT_32R6_64R6;
525 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
526 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
527 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
528 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
529 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
532 let DecoderNamespace="Mips64" in {
533 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
534 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
535 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
536 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
539 // Load/store doubleword indexed unaligned.
540 let AdditionalPredicates = [IsNotNaCl] in {
541 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
542 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
543 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
544 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
547 let DecoderNamespace="Mips64" in {
548 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
549 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
550 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
551 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
554 /// Floating-point Aritmetic
555 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
557 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
558 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
560 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
561 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
563 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
564 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
566 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
568 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
569 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
570 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
571 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
573 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
574 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
575 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
576 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
577 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
580 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
581 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
582 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
583 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
585 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
586 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
587 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
588 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
589 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
592 let DecoderNamespace = "Mips64" in {
593 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
594 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
595 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
596 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
599 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
600 DecoderNamespace = "Mips64" in {
601 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
602 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
603 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
604 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
607 //===----------------------------------------------------------------------===//
608 // Floating Point Branch Codes
609 //===----------------------------------------------------------------------===//
610 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
611 // They must be kept in synch.
612 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
613 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
615 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
616 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
617 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
618 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
619 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
620 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
621 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
622 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
624 /// Floating Point Compare
625 let AdditionalPredicates = [NotInMicroMips] in {
626 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
627 ISA_MIPS1_NOT_32R6_64R6 {
629 // FIXME: This is a required to work around the fact that these instructions
630 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
631 // fcc register set is used directly.
634 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
635 ISA_MIPS1_NOT_32R6_64R6, FGR_32 {
636 // FIXME: This is a required to work around the fact that these instructions
637 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
638 // fcc register set is used directly.
642 let DecoderNamespace = "Mips64" in
643 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
644 ISA_MIPS1_NOT_32R6_64R6, FGR_64 {
645 // FIXME: This is a required to work around the fact that thiese instructions
646 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
647 // fcc register set is used directly.
651 //===----------------------------------------------------------------------===//
652 // Floating Point Pseudo-Instructions
653 //===----------------------------------------------------------------------===//
655 // This pseudo instr gets expanded into 2 mtc1 instrs after register
657 class BuildPairF64Base<RegisterOperand RO> :
658 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
659 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
662 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
663 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
665 // This pseudo instr gets expanded into 2 mfc1 instrs after register
667 // if n is 0, lower part of src is extracted.
668 // if n is 1, higher part of src is extracted.
669 // This node has associated scheduling information as the pre RA scheduler
670 // asserts otherwise.
671 class ExtractElementF64Base<RegisterOperand RO> :
672 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
673 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
676 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
677 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
679 def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
680 (ins FGR32Opnd:$fs, GPR32Opnd:$rs),
681 "trunc.w.s\t$fd, $fs, $rs">;
683 def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
684 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs),
685 "trunc.w.d\t$fd, $fs, $rs">,
688 def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
689 (ins FGR64Opnd:$fs, GPR32Opnd:$rs),
690 "trunc.w.d\t$fd, $fs, $rs">,
693 def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
695 "li.s\t$rd, $fpimm">;
697 def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd),
699 "li.s\t$rd, $fpimm">,
702 def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
704 "li.d\t$rd, $fpimm">;
706 def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd),
708 "li.d\t$rd, $fpimm">,
711 def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd),
713 "li.d\t$rd, $fpimm">,
716 //===----------------------------------------------------------------------===//
718 //===----------------------------------------------------------------------===//
720 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
721 ISA_MIPS2, HARDFLOAT;
723 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
724 FGR_32, ISA_MIPS2, HARDFLOAT;
726 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,
727 FGR_64, ISA_MIPS2, HARDFLOAT;
730 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
731 ISA_MIPS2, HARDFLOAT;
733 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
734 FGR_32, ISA_MIPS2, HARDFLOAT;
736 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,
737 FGR_64, ISA_MIPS2, HARDFLOAT;
739 multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> {
740 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"),
741 (!cast<Instruction>("C_F_"#NAME) FCC0,
743 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"),
744 (!cast<Instruction>("C_UN_"#NAME) FCC0,
746 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"),
747 (!cast<Instruction>("C_EQ_"#NAME) FCC0,
749 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"),
750 (!cast<Instruction>("C_UEQ_"#NAME) FCC0,
752 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"),
753 (!cast<Instruction>("C_OLT_"#NAME) FCC0,
755 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"),
756 (!cast<Instruction>("C_ULT_"#NAME) FCC0,
758 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"),
759 (!cast<Instruction>("C_OLE_"#NAME) FCC0,
761 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"),
762 (!cast<Instruction>("C_ULE_"#NAME) FCC0,
764 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"),
765 (!cast<Instruction>("C_SF_"#NAME) FCC0,
767 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"),
768 (!cast<Instruction>("C_NGLE_"#NAME) FCC0,
770 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"),
771 (!cast<Instruction>("C_SEQ_"#NAME) FCC0,
773 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"),
774 (!cast<Instruction>("C_NGL_"#NAME) FCC0,
776 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"),
777 (!cast<Instruction>("C_LT_"#NAME) FCC0,
779 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"),
780 (!cast<Instruction>("C_NGE_"#NAME) FCC0,
782 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"),
783 (!cast<Instruction>("C_LE_"#NAME) FCC0,
785 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"),
786 (!cast<Instruction>("C_NGT_"#NAME) FCC0,
790 multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString,
791 Instruction BCFalse, string BCFalseString> {
792 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"),
793 (BCTrue FCC0, brtarget:$offset), 1>;
795 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"),
796 (BCFalse FCC0, brtarget:$offset), 1>;
799 let AdditionalPredicates = [NotInMicroMips] in {
800 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,
801 ISA_MIPS1_NOT_32R6_64R6;
802 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT,
803 ISA_MIPS1_NOT_32R6_64R6, FGR_32;
804 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT,
805 ISA_MIPS1_NOT_32R6_64R6, FGR_64;
807 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,
809 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,
812 //===----------------------------------------------------------------------===//
813 // Floating Point Patterns
814 //===----------------------------------------------------------------------===//
815 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
816 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
818 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
819 (PseudoCVT_S_W GPR32Opnd:$src)>;
820 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
821 (TRUNC_W_S FGR32Opnd:$src)>;
823 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
824 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
825 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
826 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
827 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
828 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
829 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
830 (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
832 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
833 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
835 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
836 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
837 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
838 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
839 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
840 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
842 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
843 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
844 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
845 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
846 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
847 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
849 def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
850 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
851 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
852 (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
854 // Patterns for loads/stores with a reg+imm operand.
855 let AdditionalPredicates = [NotInMicroMips] in {
856 let AddedComplexity = 40 in {
857 def : LoadRegImmPat<LWC1, f32, load>;
858 def : StoreRegImmPat<SWC1, f32>;
860 def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
861 def : StoreRegImmPat<SDC164, f64>, FGR_64;
863 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
864 def : StoreRegImmPat<SDC1, f64>, FGR_32;