1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
55 def Std2MicroMipsR6 : InstrMapping {
56 let FilterClass = "StdMMR6Rel";
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
59 // Instructions with the same predicate sense form a column.
60 let ColFields = ["Arch"];
61 // The key column is the unpredicated instructions.
63 // Value columns are PredSense=true and PredSense=false
64 let ValueCols = [["se"], ["micromipsr6"]];
71 // Generic Mips Format
72 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
73 InstrItinClass itin, Format f>: Instruction
78 let Namespace = "Mips";
84 // Top 6 bits are the 'opcode' field
85 let Inst{31-26} = Opcode;
87 let OutOperandList = outs;
88 let InOperandList = ins;
90 let AsmString = asmstr;
91 let Pattern = pattern;
95 // Attributes specific to Mips instructions...
97 bits<4> FormBits = Form.Value;
98 bit isCTI = 0; // Any form of Control Transfer Instruction.
99 // Required for MIPSR6
100 bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
101 bit IsPCRelativeLoad = 0; // Load instruction with implicit source register
102 // ($pc) and with explicit offset and destination
104 bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
105 // present in MIPS-I to MIPS-III.
107 // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h.
108 let TSFlags{3-0} = FormBits;
109 let TSFlags{4} = isCTI;
110 let TSFlags{5} = hasForbiddenSlot;
111 let TSFlags{6} = IsPCRelativeLoad;
112 let TSFlags{7} = hasFCCRegOperand;
114 let DecoderNamespace = "Mips";
116 field bits<32> SoftFail = 0;
119 // Mips32/64 Instruction Format
120 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
121 InstrItinClass itin, Format f, string opstr = ""> :
122 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
123 let EncodingPredicates = [HasStdEnc];
124 string BaseOpcode = opstr;
128 // Mips Pseudo Instructions Format
129 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
130 InstrItinClass itin = IIPseudo> :
131 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
132 let isCodeGenOnly = 1;
136 // Mips32/64 Pseudo Instruction Format
137 class PseudoSE<dag outs, dag ins, list<dag> pattern,
138 InstrItinClass itin = IIPseudo> :
139 MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
140 let EncodingPredicates = [HasStdEnc];
143 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
144 // These are aliases that require C++ handling to convert to the target
145 // instruction, while InstAliases can be handled directly by tblgen.
146 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
147 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
151 //===----------------------------------------------------------------------===//
152 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
153 //===----------------------------------------------------------------------===//
155 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
156 list<dag> pattern, InstrItinClass itin>:
157 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
168 let Inst{25-21} = rs;
169 let Inst{20-16} = rt;
170 let Inst{15-11} = rd;
171 let Inst{10-6} = shamt;
172 let Inst{5-0} = funct;
175 //===----------------------------------------------------------------------===//
176 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
177 //===----------------------------------------------------------------------===//
179 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
180 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
188 let Inst{25-21} = rs;
189 let Inst{20-16} = rt;
190 let Inst{15-0} = imm16;
193 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
194 list<dag> pattern, InstrItinClass itin>:
195 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
203 let Inst{25-21} = rs;
204 let Inst{20-16} = rt;
205 let Inst{15-0} = imm16;
208 //===----------------------------------------------------------------------===//
209 // Format J instruction class in Mips : <|opcode|address|>
210 //===----------------------------------------------------------------------===//
212 class FJ<bits<6> op> : StdArch
218 let Inst{31-26} = op;
219 let Inst{25-0} = target;
222 //===----------------------------------------------------------------------===//
223 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
224 //===----------------------------------------------------------------------===//
225 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
233 let Inst{31-26} = op;
234 let Inst{25-21} = mfmt;
235 let Inst{20-16} = rt;
236 let Inst{15-11} = rd;
241 class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
247 let Inst{31-26} = op;
248 let Inst{25-21} = mfmt;
249 let Inst{20-16} = rt;
250 let Inst{15-0} = imm16;
253 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
260 let Inst{31-26} = op;
261 let Inst{25-21} = rs;
262 let Inst{20-16} = rt;
263 let Inst{15-11} = rd;
265 let Inst{5-0} = funct;
268 class ADDI_FM<bits<6> op> : StdArch {
275 let Inst{31-26} = op;
276 let Inst{25-21} = rs;
277 let Inst{20-16} = rt;
278 let Inst{15-0} = imm16;
281 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
290 let Inst{21} = rotate;
291 let Inst{20-16} = rt;
292 let Inst{15-11} = rd;
293 let Inst{10-6} = shamt;
294 let Inst{5-0} = funct;
297 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
305 let Inst{25-21} = rs;
306 let Inst{20-16} = rt;
307 let Inst{15-11} = rd;
309 let Inst{6} = rotate;
310 let Inst{5-0} = funct;
313 class BEQ_FM<bits<6> op> : StdArch {
320 let Inst{31-26} = op;
321 let Inst{25-21} = rs;
322 let Inst{20-16} = rt;
323 let Inst{15-0} = offset;
326 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
332 let Inst{31-26} = op;
333 let Inst{25-21} = rs;
334 let Inst{20-16} = funct;
335 let Inst{15-0} = offset;
338 class BBIT_FM<bits<6> op> : StdArch {
345 let Inst{31-26} = op;
346 let Inst{25-21} = rs;
348 let Inst{15-0} = offset;
351 class SLTI_FM<bits<6> op> : StdArch {
358 let Inst{31-26} = op;
359 let Inst{25-21} = rs;
360 let Inst{20-16} = rt;
361 let Inst{15-0} = imm16;
364 class MFLO_FM<bits<6> funct> : StdArch {
371 let Inst{15-11} = rd;
373 let Inst{5-0} = funct;
376 class MTLO_FM<bits<6> funct> : StdArch {
382 let Inst{25-21} = rs;
384 let Inst{5-0} = funct;
387 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
393 let Inst{31-26} = 0x1f;
395 let Inst{20-16} = rt;
396 let Inst{15-11} = rd;
397 let Inst{10-6} = funct;
398 let Inst{5-0} = funct2;
401 class CLO_FM<bits<6> funct> : StdArch {
408 let Inst{31-26} = 0x1c;
409 let Inst{25-21} = rs;
410 let Inst{20-16} = rt;
411 let Inst{15-11} = rd;
413 let Inst{5-0} = funct;
417 class LUI_FM : StdArch {
423 let Inst{31-26} = 0xf;
425 let Inst{20-16} = rt;
426 let Inst{15-0} = imm16;
436 let Inst{25-21} = rs;
438 let Inst{15-11} = rd;
443 class BGEZAL_FM<bits<5> funct> : StdArch {
450 let Inst{25-21} = rs;
451 let Inst{20-16} = funct;
452 let Inst{15-0} = offset;
455 class SYNC_FM : StdArch {
461 let Inst{10-6} = stype;
465 class SYNCI_FM : StdArch {
466 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
468 bits<5> rs = addr{20-16};
469 bits<16> offset = addr{15-0};
473 let Inst{31-26} = 0b000001;
474 let Inst{25-21} = rs;
475 let Inst{20-16} = 0b11111;
476 let Inst{15-0} = offset;
479 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
485 let Inst{31-26} = op;
486 let Inst{25-21} = rs;
487 let Inst{20-16} = rt;
489 let Inst{5-0} = funct;
492 class EXT_FM<bits<6> funct> : StdArch {
500 let Inst{31-26} = 0x1f;
501 let Inst{25-21} = rs;
502 let Inst{20-16} = rt;
503 let Inst{15-11} = size;
504 let Inst{10-6} = pos;
505 let Inst{5-0} = funct;
508 class RDHWR_FM : StdArch {
514 let Inst{31-26} = 0x1f;
516 let Inst{20-16} = rt;
517 let Inst{15-11} = rd;
519 let Inst{5-0} = 0x3b;
522 class TEQ_FM<bits<6> funct> : StdArch {
530 let Inst{25-21} = rs;
531 let Inst{20-16} = rt;
532 let Inst{15-6} = code_;
533 let Inst{5-0} = funct;
536 class TEQI_FM<bits<5> funct> : StdArch {
543 let Inst{25-21} = rs;
544 let Inst{20-16} = funct;
545 let Inst{15-0} = imm16;
548 class WAIT_FM : StdArch {
551 let Inst{31-26} = 0x10;
554 let Inst{5-0} = 0x20;
557 class EXTS_FM<bits<6> funct> : StdArch {
565 let Inst{31-26} = 0x1c;
566 let Inst{25-21} = rs;
567 let Inst{20-16} = rt;
568 let Inst{15-11} = lenm1;
569 let Inst{10-6} = pos;
570 let Inst{5-0} = funct;
573 class MTMR_FM<bits<6> funct> : StdArch {
578 let Inst{31-26} = 0x1c;
579 let Inst{25-21} = rs;
581 let Inst{5-0} = funct;
584 class POP_FM<bits<6> funct> : StdArch {
590 let Inst{31-26} = 0x1c;
591 let Inst{25-21} = rs;
593 let Inst{15-11} = rd;
595 let Inst{5-0} = funct;
598 class SEQ_FM<bits<6> funct> : StdArch {
605 let Inst{31-26} = 0x1c;
606 let Inst{25-21} = rs;
607 let Inst{20-16} = rt;
608 let Inst{15-11} = rd;
610 let Inst{5-0} = funct;
613 class SEQI_FM<bits<6> funct> : StdArch {
620 let Inst{31-26} = 0x1c;
621 let Inst{25-21} = rs;
622 let Inst{20-16} = rt;
623 let Inst{15-6} = imm10;
624 let Inst{5-0} = funct;
627 //===----------------------------------------------------------------------===//
628 // System calls format <op|code_|funct>
629 //===----------------------------------------------------------------------===//
631 class SYS_FM<bits<6> funct> : StdArch
635 let Inst{31-26} = 0x0;
636 let Inst{25-6} = code_;
637 let Inst{5-0} = funct;
640 //===----------------------------------------------------------------------===//
641 // Break instruction format <op|code_1|funct>
642 //===----------------------------------------------------------------------===//
644 class BRK_FM<bits<6> funct> : StdArch
649 let Inst{31-26} = 0x0;
650 let Inst{25-16} = code_1;
651 let Inst{15-6} = code_2;
652 let Inst{5-0} = funct;
655 //===----------------------------------------------------------------------===//
656 // Exception return format <Cop0|1|0|funct>
657 //===----------------------------------------------------------------------===//
659 class ER_FM<bits<6> funct, bit LLBit> : StdArch
662 let Inst{31-26} = 0x10;
666 let Inst{5-0} = funct;
669 //===----------------------------------------------------------------------===//
670 // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
671 //===----------------------------------------------------------------------===//
673 class EI_FM<bits<1> sc> : StdArch
677 let Inst{31-26} = 0x10;
678 let Inst{25-21} = 0xb;
679 let Inst{20-16} = rt;
680 let Inst{15-11} = 0xc;
686 //===----------------------------------------------------------------------===//
688 // FLOATING POINT INSTRUCTION FORMATS
690 // opcode - operation code.
692 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
693 // fd - dst reg, only used on 3 regs instr.
694 // fmt - double or single precision.
695 // funct - combined with opcode field give us an operation code.
697 //===----------------------------------------------------------------------===//
699 //===----------------------------------------------------------------------===//
700 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
701 //===----------------------------------------------------------------------===//
703 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
704 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
712 let Inst{25-21} = base;
713 let Inst{20-16} = ft;
714 let Inst{15-0} = imm16;
717 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
724 let Inst{31-26} = 0x11;
725 let Inst{25-21} = fmt;
726 let Inst{20-16} = ft;
727 let Inst{15-11} = fs;
729 let Inst{5-0} = funct;
732 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
738 let Inst{31-26} = 0x11;
739 let Inst{25-21} = fmt;
741 let Inst{15-11} = fs;
743 let Inst{5-0} = funct;
746 class MFC1_FM<bits<5> funct> : StdArch {
752 let Inst{31-26} = 0x11;
753 let Inst{25-21} = funct;
754 let Inst{20-16} = rt;
755 let Inst{15-11} = fs;
759 class LW_FM<bits<6> op> : StdArch {
765 let Inst{31-26} = op;
766 let Inst{25-21} = addr{20-16};
767 let Inst{20-16} = rt;
768 let Inst{15-0} = addr{15-0};
771 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
779 let Inst{31-26} = 0x13;
780 let Inst{25-21} = fr;
781 let Inst{20-16} = ft;
782 let Inst{15-11} = fs;
784 let Inst{5-3} = funct;
788 class LWXC1_FM<bits<6> funct> : StdArch {
795 let Inst{31-26} = 0x13;
796 let Inst{25-21} = base;
797 let Inst{20-16} = index;
800 let Inst{5-0} = funct;
803 class SWXC1_FM<bits<6> funct> : StdArch {
810 let Inst{31-26} = 0x13;
811 let Inst{25-21} = base;
812 let Inst{20-16} = index;
813 let Inst{15-11} = fs;
815 let Inst{5-0} = funct;
818 class BC1F_FM<bit nd, bit tf> : StdArch {
824 let Inst{31-26} = 0x11;
825 let Inst{25-21} = 0x8;
826 let Inst{20-18} = fcc;
829 let Inst{15-0} = offset;
832 class CEQS_FM<bits<5> fmt> : StdArch {
840 let Inst{31-26} = 0x11;
841 let Inst{25-21} = fmt;
842 let Inst{20-16} = ft;
843 let Inst{15-11} = fs;
844 let Inst{10-8} = fcc;
846 let Inst{3-0} = cond;
849 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
853 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
860 let Inst{31-26} = 0x11;
861 let Inst{25-21} = fmt;
862 let Inst{20-16} = rt;
863 let Inst{15-11} = fs;
865 let Inst{5-0} = funct;
868 class CMov_F_I_FM<bit tf> : StdArch {
876 let Inst{25-21} = rs;
877 let Inst{20-18} = fcc;
880 let Inst{15-11} = rd;
885 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
892 let Inst{31-26} = 0x11;
893 let Inst{25-21} = fmt;
894 let Inst{20-18} = fcc;
897 let Inst{15-11} = fs;
899 let Inst{5-0} = 0x11;
902 class BARRIER_FM<bits<5> op> : StdArch {
905 let Inst{31-26} = 0; // SPECIAL
907 let Inst{20-16} = 0; // rt = 0
908 let Inst{15-11} = 0; // rd = 0
909 let Inst{10-6} = op; // Operation
910 let Inst{5-0} = 0; // SLL
913 class SDBBP_FM : StdArch {
918 let Inst{31-26} = 0b011100; // SPECIAL2
919 let Inst{25-6} = code_;
920 let Inst{5-0} = 0b111111; // SDBBP
923 class JR_HB_FM<bits<6> op> : StdArch{
928 let Inst{31-26} = 0; // SPECIAL
929 let Inst{25-21} = rs;
936 class JALR_HB_FM<bits<6> op> : StdArch {
942 let Inst{31-26} = 0; // SPECIAL
943 let Inst{25-21} = rs;
945 let Inst{15-11} = rd;
951 class COP0_TLB_FM<bits<6> op> : StdArch {
954 let Inst{31-26} = 0x10; // COP0
955 let Inst{25} = 1; // CO
957 let Inst{5-0} = op; // Operation
960 class CACHEOP_FM<bits<6> op> : StdArch {
963 bits<5> base = addr{20-16};
964 bits<16> offset = addr{15-0};
968 let Inst{31-26} = op;
969 let Inst{25-21} = base;
970 let Inst{20-16} = hint;
971 let Inst{15-0} = offset;