1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
55 def Std2MicroMipsR6 : InstrMapping {
56 let FilterClass = "StdMMR6Rel";
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
59 // Instructions with the same predicate sense form a column.
60 let ColFields = ["Arch"];
61 // The key column is the unpredicated instructions.
63 // Value columns are PredSense=true and PredSense=false
64 let ValueCols = [["se"], ["micromipsr6"]];
71 // Generic Mips Format
72 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
73 InstrItinClass itin, Format f>: Instruction
78 let Namespace = "Mips";
84 // Top 6 bits are the 'opcode' field
85 let Inst{31-26} = Opcode;
87 let OutOperandList = outs;
88 let InOperandList = ins;
90 let AsmString = asmstr;
91 let Pattern = pattern;
95 // Attributes specific to Mips instructions...
97 bits<4> FormBits = Form.Value;
98 bit isCTI = 0; // Any form of Control Transfer Instruction.
99 // Required for MIPSR6
100 bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
102 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
103 let TSFlags{3-0} = FormBits;
104 let TSFlags{4} = isCTI;
105 let TSFlags{5} = hasForbiddenSlot;
107 let DecoderNamespace = "Mips";
109 field bits<32> SoftFail = 0;
112 // Mips32/64 Instruction Format
113 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
114 InstrItinClass itin, Format f, string opstr = ""> :
115 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
116 let EncodingPredicates = [HasStdEnc];
117 string BaseOpcode = opstr;
121 // Mips Pseudo Instructions Format
122 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
123 InstrItinClass itin = IIPseudo> :
124 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
125 let isCodeGenOnly = 1;
129 // Mips32/64 Pseudo Instruction Format
130 class PseudoSE<dag outs, dag ins, list<dag> pattern,
131 InstrItinClass itin = IIPseudo> :
132 MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
133 let EncodingPredicates = [HasStdEnc];
136 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
137 // These are aliases that require C++ handling to convert to the target
138 // instruction, while InstAliases can be handled directly by tblgen.
139 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
140 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
144 //===----------------------------------------------------------------------===//
145 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
146 //===----------------------------------------------------------------------===//
148 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
149 list<dag> pattern, InstrItinClass itin>:
150 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
161 let Inst{25-21} = rs;
162 let Inst{20-16} = rt;
163 let Inst{15-11} = rd;
164 let Inst{10-6} = shamt;
165 let Inst{5-0} = funct;
168 //===----------------------------------------------------------------------===//
169 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
170 //===----------------------------------------------------------------------===//
172 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
173 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
181 let Inst{25-21} = rs;
182 let Inst{20-16} = rt;
183 let Inst{15-0} = imm16;
186 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
187 list<dag> pattern, InstrItinClass itin>:
188 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
196 let Inst{25-21} = rs;
197 let Inst{20-16} = rt;
198 let Inst{15-0} = imm16;
201 //===----------------------------------------------------------------------===//
202 // Format J instruction class in Mips : <|opcode|address|>
203 //===----------------------------------------------------------------------===//
205 class FJ<bits<6> op> : StdArch
211 let Inst{31-26} = op;
212 let Inst{25-0} = target;
215 //===----------------------------------------------------------------------===//
216 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
217 //===----------------------------------------------------------------------===//
218 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
226 let Inst{31-26} = op;
227 let Inst{25-21} = mfmt;
228 let Inst{20-16} = rt;
229 let Inst{15-11} = rd;
234 class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
240 let Inst{31-26} = op;
241 let Inst{25-21} = mfmt;
242 let Inst{20-16} = rt;
243 let Inst{15-0} = imm16;
246 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
253 let Inst{31-26} = op;
254 let Inst{25-21} = rs;
255 let Inst{20-16} = rt;
256 let Inst{15-11} = rd;
258 let Inst{5-0} = funct;
261 class ADDI_FM<bits<6> op> : StdArch {
268 let Inst{31-26} = op;
269 let Inst{25-21} = rs;
270 let Inst{20-16} = rt;
271 let Inst{15-0} = imm16;
274 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
283 let Inst{21} = rotate;
284 let Inst{20-16} = rt;
285 let Inst{15-11} = rd;
286 let Inst{10-6} = shamt;
287 let Inst{5-0} = funct;
290 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
298 let Inst{25-21} = rs;
299 let Inst{20-16} = rt;
300 let Inst{15-11} = rd;
302 let Inst{6} = rotate;
303 let Inst{5-0} = funct;
306 class BEQ_FM<bits<6> op> : StdArch {
313 let Inst{31-26} = op;
314 let Inst{25-21} = rs;
315 let Inst{20-16} = rt;
316 let Inst{15-0} = offset;
319 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
325 let Inst{31-26} = op;
326 let Inst{25-21} = rs;
327 let Inst{20-16} = funct;
328 let Inst{15-0} = offset;
331 class BBIT_FM<bits<6> op> : StdArch {
338 let Inst{31-26} = op;
339 let Inst{25-21} = rs;
341 let Inst{15-0} = offset;
344 class SLTI_FM<bits<6> op> : StdArch {
351 let Inst{31-26} = op;
352 let Inst{25-21} = rs;
353 let Inst{20-16} = rt;
354 let Inst{15-0} = imm16;
357 class MFLO_FM<bits<6> funct> : StdArch {
364 let Inst{15-11} = rd;
366 let Inst{5-0} = funct;
369 class MTLO_FM<bits<6> funct> : StdArch {
375 let Inst{25-21} = rs;
377 let Inst{5-0} = funct;
380 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
386 let Inst{31-26} = 0x1f;
388 let Inst{20-16} = rt;
389 let Inst{15-11} = rd;
390 let Inst{10-6} = funct;
391 let Inst{5-0} = funct2;
394 class CLO_FM<bits<6> funct> : StdArch {
401 let Inst{31-26} = 0x1c;
402 let Inst{25-21} = rs;
403 let Inst{20-16} = rt;
404 let Inst{15-11} = rd;
406 let Inst{5-0} = funct;
410 class LUI_FM : StdArch {
416 let Inst{31-26} = 0xf;
418 let Inst{20-16} = rt;
419 let Inst{15-0} = imm16;
429 let Inst{25-21} = rs;
431 let Inst{15-11} = rd;
436 class BGEZAL_FM<bits<5> funct> : StdArch {
443 let Inst{25-21} = rs;
444 let Inst{20-16} = funct;
445 let Inst{15-0} = offset;
448 class SYNC_FM : StdArch {
454 let Inst{10-6} = stype;
458 class SYNCI_FM : StdArch {
459 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
461 bits<5> rs = addr{20-16};
462 bits<16> offset = addr{15-0};
466 let Inst{31-26} = 0b000001;
467 let Inst{25-21} = rs;
468 let Inst{20-16} = 0b11111;
469 let Inst{15-0} = offset;
472 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
478 let Inst{31-26} = op;
479 let Inst{25-21} = rs;
480 let Inst{20-16} = rt;
482 let Inst{5-0} = funct;
485 class EXT_FM<bits<6> funct> : StdArch {
493 let Inst{31-26} = 0x1f;
494 let Inst{25-21} = rs;
495 let Inst{20-16} = rt;
496 let Inst{15-11} = size;
497 let Inst{10-6} = pos;
498 let Inst{5-0} = funct;
501 class RDHWR_FM : StdArch {
507 let Inst{31-26} = 0x1f;
509 let Inst{20-16} = rt;
510 let Inst{15-11} = rd;
512 let Inst{5-0} = 0x3b;
515 class TEQ_FM<bits<6> funct> : StdArch {
523 let Inst{25-21} = rs;
524 let Inst{20-16} = rt;
525 let Inst{15-6} = code_;
526 let Inst{5-0} = funct;
529 class TEQI_FM<bits<5> funct> : StdArch {
536 let Inst{25-21} = rs;
537 let Inst{20-16} = funct;
538 let Inst{15-0} = imm16;
541 class WAIT_FM : StdArch {
544 let Inst{31-26} = 0x10;
547 let Inst{5-0} = 0x20;
550 class EXTS_FM<bits<6> funct> : StdArch {
558 let Inst{31-26} = 0x1c;
559 let Inst{25-21} = rs;
560 let Inst{20-16} = rt;
561 let Inst{15-11} = lenm1;
562 let Inst{10-6} = pos;
563 let Inst{5-0} = funct;
566 class MTMR_FM<bits<6> funct> : StdArch {
571 let Inst{31-26} = 0x1c;
572 let Inst{25-21} = rs;
574 let Inst{5-0} = funct;
577 class POP_FM<bits<6> funct> : StdArch {
583 let Inst{31-26} = 0x1c;
584 let Inst{25-21} = rs;
586 let Inst{15-11} = rd;
588 let Inst{5-0} = funct;
591 class SEQ_FM<bits<6> funct> : StdArch {
598 let Inst{31-26} = 0x1c;
599 let Inst{25-21} = rs;
600 let Inst{20-16} = rt;
601 let Inst{15-11} = rd;
603 let Inst{5-0} = funct;
606 class SEQI_FM<bits<6> funct> : StdArch {
613 let Inst{31-26} = 0x1c;
614 let Inst{25-21} = rs;
615 let Inst{20-16} = rt;
616 let Inst{15-6} = imm10;
617 let Inst{5-0} = funct;
620 //===----------------------------------------------------------------------===//
621 // System calls format <op|code_|funct>
622 //===----------------------------------------------------------------------===//
624 class SYS_FM<bits<6> funct> : StdArch
628 let Inst{31-26} = 0x0;
629 let Inst{25-6} = code_;
630 let Inst{5-0} = funct;
633 //===----------------------------------------------------------------------===//
634 // Break instruction format <op|code_1|funct>
635 //===----------------------------------------------------------------------===//
637 class BRK_FM<bits<6> funct> : StdArch
642 let Inst{31-26} = 0x0;
643 let Inst{25-16} = code_1;
644 let Inst{15-6} = code_2;
645 let Inst{5-0} = funct;
648 //===----------------------------------------------------------------------===//
649 // Exception return format <Cop0|1|0|funct>
650 //===----------------------------------------------------------------------===//
652 class ER_FM<bits<6> funct, bit LLBit> : StdArch
655 let Inst{31-26} = 0x10;
659 let Inst{5-0} = funct;
662 //===----------------------------------------------------------------------===//
663 // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
664 //===----------------------------------------------------------------------===//
666 class EI_FM<bits<1> sc> : StdArch
670 let Inst{31-26} = 0x10;
671 let Inst{25-21} = 0xb;
672 let Inst{20-16} = rt;
673 let Inst{15-11} = 0xc;
679 //===----------------------------------------------------------------------===//
681 // FLOATING POINT INSTRUCTION FORMATS
683 // opcode - operation code.
685 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
686 // fd - dst reg, only used on 3 regs instr.
687 // fmt - double or single precision.
688 // funct - combined with opcode field give us an operation code.
690 //===----------------------------------------------------------------------===//
692 //===----------------------------------------------------------------------===//
693 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
694 //===----------------------------------------------------------------------===//
696 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
697 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
705 let Inst{25-21} = base;
706 let Inst{20-16} = ft;
707 let Inst{15-0} = imm16;
710 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
717 let Inst{31-26} = 0x11;
718 let Inst{25-21} = fmt;
719 let Inst{20-16} = ft;
720 let Inst{15-11} = fs;
722 let Inst{5-0} = funct;
725 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
731 let Inst{31-26} = 0x11;
732 let Inst{25-21} = fmt;
734 let Inst{15-11} = fs;
736 let Inst{5-0} = funct;
739 class MFC1_FM<bits<5> funct> : StdArch {
745 let Inst{31-26} = 0x11;
746 let Inst{25-21} = funct;
747 let Inst{20-16} = rt;
748 let Inst{15-11} = fs;
752 class LW_FM<bits<6> op> : StdArch {
758 let Inst{31-26} = op;
759 let Inst{25-21} = addr{20-16};
760 let Inst{20-16} = rt;
761 let Inst{15-0} = addr{15-0};
764 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
772 let Inst{31-26} = 0x13;
773 let Inst{25-21} = fr;
774 let Inst{20-16} = ft;
775 let Inst{15-11} = fs;
777 let Inst{5-3} = funct;
781 class LWXC1_FM<bits<6> funct> : StdArch {
788 let Inst{31-26} = 0x13;
789 let Inst{25-21} = base;
790 let Inst{20-16} = index;
793 let Inst{5-0} = funct;
796 class SWXC1_FM<bits<6> funct> : StdArch {
803 let Inst{31-26} = 0x13;
804 let Inst{25-21} = base;
805 let Inst{20-16} = index;
806 let Inst{15-11} = fs;
808 let Inst{5-0} = funct;
811 class BC1F_FM<bit nd, bit tf> : StdArch {
817 let Inst{31-26} = 0x11;
818 let Inst{25-21} = 0x8;
819 let Inst{20-18} = fcc;
822 let Inst{15-0} = offset;
825 class CEQS_FM<bits<5> fmt> : StdArch {
832 let Inst{31-26} = 0x11;
833 let Inst{25-21} = fmt;
834 let Inst{20-16} = ft;
835 let Inst{15-11} = fs;
836 let Inst{10-8} = 0; // cc
838 let Inst{3-0} = cond;
841 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
845 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
852 let Inst{31-26} = 0x11;
853 let Inst{25-21} = fmt;
854 let Inst{20-16} = rt;
855 let Inst{15-11} = fs;
857 let Inst{5-0} = funct;
860 class CMov_F_I_FM<bit tf> : StdArch {
868 let Inst{25-21} = rs;
869 let Inst{20-18} = fcc;
872 let Inst{15-11} = rd;
877 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
884 let Inst{31-26} = 0x11;
885 let Inst{25-21} = fmt;
886 let Inst{20-18} = fcc;
889 let Inst{15-11} = fs;
891 let Inst{5-0} = 0x11;
894 class BARRIER_FM<bits<5> op> : StdArch {
897 let Inst{31-26} = 0; // SPECIAL
899 let Inst{20-16} = 0; // rt = 0
900 let Inst{15-11} = 0; // rd = 0
901 let Inst{10-6} = op; // Operation
902 let Inst{5-0} = 0; // SLL
905 class SDBBP_FM : StdArch {
910 let Inst{31-26} = 0b011100; // SPECIAL2
911 let Inst{25-6} = code_;
912 let Inst{5-0} = 0b111111; // SDBBP
915 class JR_HB_FM<bits<6> op> : StdArch{
920 let Inst{31-26} = 0; // SPECIAL
921 let Inst{25-21} = rs;
928 class JALR_HB_FM<bits<6> op> : StdArch {
934 let Inst{31-26} = 0; // SPECIAL
935 let Inst{25-21} = rs;
937 let Inst{15-11} = rd;
943 class COP0_TLB_FM<bits<6> op> : StdArch {
946 let Inst{31-26} = 0x10; // COP0
947 let Inst{25} = 1; // CO
949 let Inst{5-0} = op; // Operation
952 class CACHEOP_FM<bits<6> op> : StdArch {
955 bits<5> base = addr{20-16};
956 bits<16> offset = addr{15-0};
960 let Inst{31-26} = op;
961 let Inst{25-21} = base;
962 let Inst{20-16} = hint;
963 let Inst{15-0} = offset;