1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/TargetOpcodes.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Target/TargetMachine.h"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
37 // Pin the vtable to this file.
38 void MipsInstrInfo::anchor() {}
40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
41 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42 Subtarget(STI), UncondBrOpc(UncondBr) {}
44 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
45 if (STI.inMips16Mode())
46 return createMips16InstrInfo(STI);
48 return createMipsSEInstrInfo(STI);
51 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
52 return op.isImm() && op.getImm() == 0;
55 /// insertNoop - If data hazard condition is found insert the target nop
57 // FIXME: This appears to be dead code.
59 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
62 BuildMI(MBB, MI, DL, get(Mips::NOP));
66 MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
67 MachineMemOperand::Flags Flags) const {
68 MachineFunction &MF = *MBB.getParent();
69 MachineFrameInfo &MFI = MF.getFrameInfo();
70 unsigned Align = MFI.getObjectAlignment(FI);
72 return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
73 Flags, MFI.getObjectSize(FI), Align);
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
81 MachineBasicBlock *&BB,
82 SmallVectorImpl<MachineOperand> &Cond) const {
83 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
84 int NumOp = Inst->getNumExplicitOperands();
86 // for both int and fp branches, the last explicit operand is the
88 BB = Inst->getOperand(NumOp-1).getMBB();
89 Cond.push_back(MachineOperand::CreateImm(Opc));
91 for (int i = 0; i < NumOp-1; i++)
92 Cond.push_back(Inst->getOperand(i));
95 bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
96 MachineBasicBlock *&TBB,
97 MachineBasicBlock *&FBB,
98 SmallVectorImpl<MachineOperand> &Cond,
99 bool AllowModify) const {
100 SmallVector<MachineInstr*, 2> BranchInstrs;
101 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
103 return (BT == BT_None) || (BT == BT_Indirect);
106 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
108 ArrayRef<MachineOperand> Cond) const {
109 unsigned Opc = Cond[0].getImm();
110 const MCInstrDesc &MCID = get(Opc);
111 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
113 for (unsigned i = 1; i < Cond.size(); ++i) {
114 assert((Cond[i].isImm() || Cond[i].isReg()) &&
115 "Cannot copy operand for conditional branch!");
121 unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
122 MachineBasicBlock *TBB,
123 MachineBasicBlock *FBB,
124 ArrayRef<MachineOperand> Cond,
126 int *BytesAdded) const {
127 // Shouldn't be a fall through.
128 assert(TBB && "insertBranch must not be told to insert a fallthrough");
129 assert(!BytesAdded && "code size not handled");
131 // # of condition operands:
132 // Unconditional branches: 0
133 // Floating point branches: 1 (opc)
134 // Int BranchZero: 2 (opc, reg)
135 // Int Branch: 3 (opc, reg0, reg1)
136 assert((Cond.size() <= 3) &&
137 "# of Mips branch conditions must be <= 3!");
139 // Two-way Conditional branch.
141 BuildCondBr(MBB, TBB, DL, Cond);
142 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
147 // Unconditional branch.
149 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
150 else // Conditional branch.
151 BuildCondBr(MBB, TBB, DL, Cond);
155 unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
156 int *BytesRemoved) const {
157 assert(!BytesRemoved && "code size not handled");
159 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
160 unsigned removed = 0;
162 // Up to 2 branches are removed.
163 // Note that indirect branches are not removed.
164 while (I != REnd && removed < 2) {
165 // Skip past debug instructions.
166 if (I->isDebugValue()) {
170 if (!getAnalyzableBrOpc(I->getOpcode()))
172 // Remove the branch.
173 I->eraseFromParent();
181 /// reverseBranchCondition - Return the inverse opcode of the
182 /// specified Branch instruction.
183 bool MipsInstrInfo::reverseBranchCondition(
184 SmallVectorImpl<MachineOperand> &Cond) const {
185 assert( (Cond.size() && Cond.size() <= 3) &&
186 "Invalid Mips branch condition!");
187 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
191 MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
192 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
193 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
194 SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
195 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
197 // Skip all the debug instructions.
198 while (I != REnd && I->isDebugValue())
201 if (I == REnd || !isUnpredicatedTerminator(*I)) {
202 // This block ends with no branches (it just falls through to its succ).
203 // Leave TBB/FBB null.
208 MachineInstr *LastInst = &*I;
209 unsigned LastOpc = LastInst->getOpcode();
210 BranchInstrs.push_back(LastInst);
212 // Not an analyzable branch (e.g., indirect jump).
213 if (!getAnalyzableBrOpc(LastOpc))
214 return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
216 // Get the second to last instruction in the block.
217 unsigned SecondLastOpc = 0;
218 MachineInstr *SecondLastInst = nullptr;
220 // Skip past any debug instruction to see if the second last actual
223 while (I != REnd && I->isDebugValue())
227 SecondLastInst = &*I;
228 SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
230 // Not an analyzable branch (must be an indirect jump).
231 if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
235 // If there is only one terminator instruction, process it.
236 if (!SecondLastOpc) {
237 // Unconditional branch.
238 if (LastInst->isUnconditionalBranch()) {
239 TBB = LastInst->getOperand(0).getMBB();
243 // Conditional branch
244 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
248 // If we reached here, there are two branches.
249 // If there are three terminators, we don't know what sort of block this is.
250 if (++I != REnd && isUnpredicatedTerminator(*I))
253 BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
255 // If second to last instruction is an unconditional branch,
256 // analyze it and remove the last instruction.
257 if (SecondLastInst->isUnconditionalBranch()) {
258 // Return if the last instruction cannot be removed.
262 TBB = SecondLastInst->getOperand(0).getMBB();
263 LastInst->eraseFromParent();
264 BranchInstrs.pop_back();
268 // Conditional branch followed by an unconditional branch.
269 // The last one must be unconditional.
270 if (!LastInst->isUnconditionalBranch())
273 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
274 FBB = LastInst->getOperand(0).getMBB();
276 return BT_CondUncond;
279 /// Return the corresponding compact (no delay slot) form of a branch.
280 unsigned MipsInstrInfo::getEquivalentCompactForm(
281 const MachineBasicBlock::iterator I) const {
282 unsigned Opcode = I->getOpcode();
283 bool canUseShortMicroMipsCTI = false;
285 if (Subtarget.inMicroMipsMode()) {
291 // microMIPS has NE,EQ branches that do not have delay slots provided one
292 // of the operands is zero.
293 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
294 canUseShortMicroMipsCTI = true;
296 // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
297 // expanded to JR_MM, so they can be replaced with JRC16_MM.
299 case Mips::PseudoReturn:
300 case Mips::PseudoIndirectBranch:
301 case Mips::TAILCALLREG:
302 canUseShortMicroMipsCTI = true;
307 // MIPSR6 forbids both operands being the zero register.
308 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
309 (I->getOperand(0).isReg() &&
310 (I->getOperand(0).getReg() == Mips::ZERO ||
311 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
312 (I->getOperand(1).isReg() &&
313 (I->getOperand(1).getReg() == Mips::ZERO ||
314 I->getOperand(1).getReg() == Mips::ZERO_64)))
317 if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
325 if (canUseShortMicroMipsCTI)
326 return Mips::BEQZC_MM;
327 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
332 if (canUseShortMicroMipsCTI)
333 return Mips::BNEZC_MM;
334 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
338 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
342 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
352 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
356 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
362 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
366 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
370 return Mips::BGTZC64;
372 return Mips::BGEZC64;
374 return Mips::BLTZC64;
376 return Mips::BLEZC64;
377 // For MIPSR6, the instruction 'jic' can be used for these cases. Some
378 // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
380 case Mips::PseudoReturn:
381 case Mips::PseudoIndirectBranch:
382 case Mips::TAILCALLREG:
383 if (canUseShortMicroMipsCTI)
384 return Mips::JRC16_MM;
386 case Mips::JALRPseudo:
389 case Mips::PseudoReturn64:
390 case Mips::PseudoIndirectBranch64:
391 case Mips::TAILCALLREG64:
393 case Mips::JALR64Pseudo:
394 return Mips::JIALC64;
403 /// Predicate for distingushing between control transfer instructions and all
404 /// other instructions for handling forbidden slots. Consider inline assembly
405 /// as unsafe as well.
406 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
407 if (MI.isInlineAsm())
410 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
413 /// Predicate for distingushing instructions that have forbidden slots.
414 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
415 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
418 /// Return the number of bytes of code the specified instruction may be.
419 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
420 switch (MI.getOpcode()) {
422 return MI.getDesc().getSize();
423 case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
424 const MachineFunction *MF = MI.getParent()->getParent();
425 const char *AsmStr = MI.getOperand(0).getSymbolName();
426 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
428 case Mips::CONSTPOOL_ENTRY:
429 // If this machine instr is a constant pool entry, its size is recorded as
431 return MI.getOperand(2).getImm();
436 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
437 MachineBasicBlock::iterator I) const {
438 MachineInstrBuilder MIB;
440 // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
441 // Pick the zero form of the branch for readable assembly and for greater
442 // branch distance in non-microMIPS mode.
443 // Additional MIPSR6 does not permit the use of register $zero for compact
445 // FIXME: Certain atomic sequences on mips64 generate 32bit references to
446 // Mips::ZERO, which is incorrect. This test should be updated to use
447 // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
449 int ZeroOperandPosition = -1;
450 bool BranchWithZeroOperand = false;
451 if (I->isBranch() && !I->isPseudo()) {
452 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
453 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
454 BranchWithZeroOperand = ZeroOperandPosition != -1;
457 if (BranchWithZeroOperand) {
460 NewOpc = Mips::BEQZC;
463 NewOpc = Mips::BNEZC;
466 NewOpc = Mips::BGEZC;
469 NewOpc = Mips::BLTZC;
472 NewOpc = Mips::BEQZC64;
475 NewOpc = Mips::BNEZC64;
480 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
482 // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
483 // immediate 0 as an operand and requires the removal of it's implicit-def %ra
484 // implicit operand as copying the implicit operations of the instructio we're
485 // looking at will give us the correct flags.
486 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
487 NewOpc == Mips::JIALC64) {
489 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
490 MIB->RemoveOperand(0);
492 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
493 MIB.add(I->getOperand(J));
499 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
500 if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
503 MIB.add(I->getOperand(J));
507 MIB.copyImplicitOps(*I);
509 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
513 bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
514 unsigned &SrcOpIdx2) const {
515 assert(!MI.isBundle() &&
516 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
518 const MCInstrDesc &MCID = MI.getDesc();
519 if (!MCID.isCommutable())
522 switch (MI.getOpcode()) {
523 case Mips::DPADD_U_H:
524 case Mips::DPADD_U_W:
525 case Mips::DPADD_U_D:
526 case Mips::DPADD_S_H:
527 case Mips::DPADD_S_W:
528 case Mips::DPADD_S_D:
529 // The first operand is both input and output, so it should not commute
530 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
533 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
537 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
540 // ins, ext, dext*, dins have the following constraints:
545 // dinsm and dinsu have the following constraints:
550 // The callee of verifyInsExtInstruction however gives the bounds of
551 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
552 // function doesn't have to vary it's behaviour based on the instruction
554 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
555 const int64_t PosLow, const int64_t PosHigh,
556 const int64_t SizeLow,
557 const int64_t SizeHigh,
558 const int64_t BothLow,
559 const int64_t BothHigh) {
560 MachineOperand MOPos = MI.getOperand(2);
561 if (!MOPos.isImm()) {
562 ErrInfo = "Position is not an immediate!";
565 int64_t Pos = MOPos.getImm();
566 if (!((PosLow <= Pos) && (Pos < PosHigh))) {
567 ErrInfo = "Position operand is out of range!";
571 MachineOperand MOSize = MI.getOperand(3);
572 if (!MOSize.isImm()) {
573 ErrInfo = "Size operand is not an immediate!";
576 int64_t Size = MOSize.getImm();
577 if (!((SizeLow < Size) && (Size <= SizeHigh))) {
578 ErrInfo = "Size operand is out of range!";
582 if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
583 ErrInfo = "Position + Size is out of range!";
590 // Perform target specific instruction verification.
591 bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
592 StringRef &ErrInfo) const {
593 // Verify that ins and ext instructions are well formed.
594 switch (MI.getOpcode()) {
600 return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
602 // The ISA spec has a subtle difference difference between dinsm and dextm
604 // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
605 // To make the bounds checks similar, the range 1 < size <= 64 is checked
607 return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
609 // The ISA spec has a subtle difference between dinsu and dextu in that
610 // the size range of dinsu is specified as 1 <= size <= 32 whereas size
611 // for dextu is 0 < size <= 32. The range checked for dinsu here is
612 // 0 < size <= 32, which is equivalent and similar to dextu.
613 return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
615 return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
617 return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
619 return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
627 std::pair<unsigned, unsigned>
628 MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
629 return std::make_pair(TF, 0u);
632 ArrayRef<std::pair<unsigned, const char*>>
633 MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
634 using namespace MipsII;
636 static const std::pair<unsigned, const char*> Flags[] = {
637 {MO_GOT, "mips-got"},
638 {MO_GOT_CALL, "mips-got-call"},
639 {MO_GPREL, "mips-gprel"},
640 {MO_ABS_HI, "mips-abs-hi"},
641 {MO_ABS_LO, "mips-abs-lo"},
642 {MO_TLSGD, "mips-tlsgd"},
643 {MO_TLSLDM, "mips-tlsldm"},
644 {MO_DTPREL_HI, "mips-dtprel-hi"},
645 {MO_DTPREL_LO, "mips-dtprel-lo"},
646 {MO_GOTTPREL, "mips-gottprel"},
647 {MO_TPREL_HI, "mips-tprel-hi"},
648 {MO_TPREL_LO, "mips-tprel-lo"},
649 {MO_GPOFF_HI, "mips-gpoff-hi"},
650 {MO_GPOFF_LO, "mips-gpoff-lo"},
651 {MO_GOT_DISP, "mips-got-disp"},
652 {MO_GOT_PAGE, "mips-got-page"},
653 {MO_GOT_OFST, "mips-got-ofst"},
654 {MO_HIGHER, "mips-higher"},
655 {MO_HIGHEST, "mips-highest"},
656 {MO_GOT_HI16, "mips-got-hi16"},
657 {MO_GOT_LO16, "mips-got-lo16"},
658 {MO_CALL_HI16, "mips-call-hi16"},
659 {MO_CALL_LO16, "mips-call-lo16"}
661 return makeArrayRef(Flags);