1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
30 def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
34 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
35 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
36 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
37 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
38 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
39 [SDNPCommutative, SDNPAssociative]>;
40 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
41 [SDNPCommutative, SDNPAssociative]>;
42 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
43 [SDNPCommutative, SDNPAssociative]>;
44 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
45 [SDNPCommutative, SDNPAssociative]>;
46 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
49 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
50 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
51 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
52 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
53 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
54 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
55 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
56 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
58 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
59 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
61 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
63 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
66 def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
67 def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
68 def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
69 def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
73 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
76 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
77 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
78 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
79 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
80 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
81 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
82 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
83 (MipsVExtractSExt node:$vec, node:$idx, i64)>;
85 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
86 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
87 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
88 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
89 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
90 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
91 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
92 (MipsVExtractZExt node:$vec, node:$idx, i64)>;
94 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
95 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
96 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
97 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
98 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
99 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
100 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
101 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
103 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
104 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
105 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
106 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
107 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
108 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
109 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
110 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
112 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
113 PatFrag<(ops node:$lhs, node:$rhs),
114 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
116 // ISD::SETFALSE cannot occur
117 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
118 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
119 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
120 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
121 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
122 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
123 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
124 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
125 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
126 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
127 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
128 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
129 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
130 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
131 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
132 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
133 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
134 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
135 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
136 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
137 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
138 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
139 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
140 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
141 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
142 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
143 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
144 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
145 // ISD::SETTRUE cannot occur
146 // ISD::SETFALSE2 cannot occur
147 // ISD::SETTRUE2 cannot occur
149 class vsetcc_type<ValueType ResTy, CondCode CC> :
150 PatFrag<(ops node:$lhs, node:$rhs),
151 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
153 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
154 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
155 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
156 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
157 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
158 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
159 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
160 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
161 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
162 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
163 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
164 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
165 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
166 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
167 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
168 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
169 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
170 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
171 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
172 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
174 def vsplati8 : PatFrag<(ops node:$e0),
175 (v16i8 (build_vector node:$e0, node:$e0,
182 node:$e0, node:$e0))>;
183 def vsplati16 : PatFrag<(ops node:$e0),
184 (v8i16 (build_vector node:$e0, node:$e0,
187 node:$e0, node:$e0))>;
188 def vsplati32 : PatFrag<(ops node:$e0),
189 (v4i32 (build_vector node:$e0, node:$e0,
190 node:$e0, node:$e0))>;
191 def vsplati64 : PatFrag<(ops node:$e0),
192 (v2i64 (build_vector node:$e0, node:$e0))>;
193 def vsplatf32 : PatFrag<(ops node:$e0),
194 (v4f32 (build_vector node:$e0, node:$e0,
195 node:$e0, node:$e0))>;
196 def vsplatf64 : PatFrag<(ops node:$e0),
197 (v2f64 (build_vector node:$e0, node:$e0))>;
199 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
200 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
201 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
202 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
203 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
204 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
205 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
206 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
208 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
209 SDNodeXForm xform = NOOP_SDNodeXForm>
210 : PatLeaf<frag, pred, xform> {
211 Operand OpClass = opclass;
214 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
215 list<SDNode> roots = [],
216 list<SDNodeProperty> props = []> :
217 ComplexPattern<ty, numops, fn, roots, props> {
218 Operand OpClass = opclass;
221 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
223 [build_vector, bitconvert]>;
225 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
227 [build_vector, bitconvert]>;
229 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
231 [build_vector, bitconvert]>;
233 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
235 [build_vector, bitconvert]>;
237 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
239 [build_vector, bitconvert]>;
241 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
243 [build_vector, bitconvert]>;
245 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
247 [build_vector, bitconvert]>;
249 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
251 [build_vector, bitconvert]>;
253 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
255 [build_vector, bitconvert]>;
257 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
259 [build_vector, bitconvert]>;
261 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
263 [build_vector, bitconvert]>;
265 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
267 [build_vector, bitconvert]>;
269 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
271 [build_vector, bitconvert]>;
273 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
275 [build_vector, bitconvert]>;
277 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
279 [build_vector, bitconvert]>;
281 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
283 [build_vector, bitconvert]>;
285 // Any build_vector that is a constant splat with a value that is an exact
287 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
288 [build_vector, bitconvert]>;
290 // Any build_vector that is a constant splat with a value that is the bitwise
291 // inverse of an exact power of 2
292 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
293 [build_vector, bitconvert]>;
295 // Any build_vector that is a constant splat with only a consecutive sequence
296 // of left-most bits set.
297 def vsplat_maskl_bits_uimm3
298 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL",
299 [build_vector, bitconvert]>;
300 def vsplat_maskl_bits_uimm4
301 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL",
302 [build_vector, bitconvert]>;
303 def vsplat_maskl_bits_uimm5
304 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL",
305 [build_vector, bitconvert]>;
306 def vsplat_maskl_bits_uimm6
307 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL",
308 [build_vector, bitconvert]>;
310 // Any build_vector that is a constant splat with only a consecutive sequence
311 // of right-most bits set.
312 def vsplat_maskr_bits_uimm3
313 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR",
314 [build_vector, bitconvert]>;
315 def vsplat_maskr_bits_uimm4
316 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR",
317 [build_vector, bitconvert]>;
318 def vsplat_maskr_bits_uimm5
319 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR",
320 [build_vector, bitconvert]>;
321 def vsplat_maskr_bits_uimm6
322 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR",
323 [build_vector, bitconvert]>;
325 // Any build_vector that is a constant splat with a value that equals 1
326 // FIXME: These should be a ComplexPattern but we can't use them because the
327 // ISel generator requires the uses to have a name, but providing a name
328 // causes other errors ("used in pattern but not operand list")
329 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
331 EVT EltTy = N->getValueType(0).getVectorElementType();
333 return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
334 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
337 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
339 SDNode *BV = N->getOperand(0).getNode();
340 EVT EltTy = N->getValueType(0).getVectorElementType();
342 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
343 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
346 def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
347 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
349 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
350 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
352 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
353 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
355 def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
356 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
358 (bitconvert (v4i32 immAllOnesV))))>;
360 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
361 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
362 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
363 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
364 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
365 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
366 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
367 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
370 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
371 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
372 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
373 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
374 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
375 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
376 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
377 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
380 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
381 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
383 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
384 (add node:$wd, (mul node:$ws, node:$wt))>;
386 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
387 (sub node:$wd, (mul node:$ws, node:$wt))>;
389 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
390 (fmul node:$ws, (fexp2 node:$wt))>;
392 // Instruction encoding.
393 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
394 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
395 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
396 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
398 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
399 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
400 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
401 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
403 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
404 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
405 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
406 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
408 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
409 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
410 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
411 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
413 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
414 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
415 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
416 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
418 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
419 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
420 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
421 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
423 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
425 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
427 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
428 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
429 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
430 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
432 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
433 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
434 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
435 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
437 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
438 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
439 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
440 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
442 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
443 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
444 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
445 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
447 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
448 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
449 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
450 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
452 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
453 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
454 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
455 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
457 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
458 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
459 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
460 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
462 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
463 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
464 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
465 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
467 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
468 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
469 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
470 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
472 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
473 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
474 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
475 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
477 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
478 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
479 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
480 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
482 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
483 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
484 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
485 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
487 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
489 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
491 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
493 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
495 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
496 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
497 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
498 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
500 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
501 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
502 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
503 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
505 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
506 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
507 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
508 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
510 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
512 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
514 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
516 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
517 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
518 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
519 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
521 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
522 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
523 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
524 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
526 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
527 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
528 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
529 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
531 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
533 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
534 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
535 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
536 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
538 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
539 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
540 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
541 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
543 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
545 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
546 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
547 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
548 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
550 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
551 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
552 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
553 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
555 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
556 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
557 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
558 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
560 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
561 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
562 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
563 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
565 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
566 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
567 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
568 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
570 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
571 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
572 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
573 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
575 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
576 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
577 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
578 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
580 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
581 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
582 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
583 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
585 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
586 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
587 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
588 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
590 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
591 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
592 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
594 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
596 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
597 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
598 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
599 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
601 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
602 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
603 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
604 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
606 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
607 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
608 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
610 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
611 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
612 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
614 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
615 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
616 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
618 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
619 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
620 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
622 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
623 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
624 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
626 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
627 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
628 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
630 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
631 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
633 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
634 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
636 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
637 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
639 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
640 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
642 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
643 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
645 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
646 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
648 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
649 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
651 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
652 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
654 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
655 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
657 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
658 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
660 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
661 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
663 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
664 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
666 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
667 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
669 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
670 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
672 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
673 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
675 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
676 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
678 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
679 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
681 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
682 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
684 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
685 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
687 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
688 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
690 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
691 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
693 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
694 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
696 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
697 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
698 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
699 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
701 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
702 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
704 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
705 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
707 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
708 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
710 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
711 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
713 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
714 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
716 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
717 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
719 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
720 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
722 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
723 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
725 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
726 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
728 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
729 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
731 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
732 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
734 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
735 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
737 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
738 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
740 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
741 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
743 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
744 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
746 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
747 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
749 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
750 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
752 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
753 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
755 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
756 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
758 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
759 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
761 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
762 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
764 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
765 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
767 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
768 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
770 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
771 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
773 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
774 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
776 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
777 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
779 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
780 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
782 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
783 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
785 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
786 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
788 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
789 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
790 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
792 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
793 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
794 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
796 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
797 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
798 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
800 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
801 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
802 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
804 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
805 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
806 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
807 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
809 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
810 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
811 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
812 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
814 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
815 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
816 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
817 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
819 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
820 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
821 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
822 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
824 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
825 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
826 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
827 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
829 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
830 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
831 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
832 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
834 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
835 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
836 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
837 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
839 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
840 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
841 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
842 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
844 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
845 class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
847 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
848 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
850 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
851 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
853 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
854 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
855 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
856 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
858 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
859 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
860 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
861 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
863 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
864 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
865 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
866 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
868 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
869 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
870 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
871 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
873 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
874 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
875 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
876 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
878 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
879 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
880 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
881 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
883 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
884 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
885 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
886 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
888 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
889 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
890 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
891 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
893 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
894 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
895 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
896 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
898 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
899 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
900 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
901 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
903 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
904 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
905 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
906 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
908 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
909 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
910 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
911 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
913 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
914 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
915 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
916 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
918 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
920 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
921 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
923 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
924 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
926 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
927 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
928 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
929 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
931 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
932 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
934 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
935 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
937 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
938 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
939 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
940 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
942 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
943 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
944 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
945 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
947 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
948 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
949 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
950 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
952 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
954 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
956 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
958 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
960 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
961 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
962 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
963 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
965 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
966 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
967 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
968 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
970 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
971 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
972 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
973 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
975 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
976 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
977 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
978 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
980 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
981 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
982 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
983 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
985 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
986 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
987 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
989 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
990 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
991 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
992 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
994 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
995 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
996 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
997 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
999 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1000 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1001 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1002 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1004 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1005 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1006 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1007 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1009 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1010 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1011 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1012 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1014 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1015 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1016 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1017 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1019 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1020 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1021 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1022 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1024 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1025 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1026 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1027 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1029 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1030 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1031 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1032 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1034 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1035 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1036 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1037 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1039 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1040 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1041 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1042 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1044 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1045 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1046 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1047 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1049 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1050 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1051 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1052 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1054 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1055 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1056 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1057 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1059 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1060 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1061 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1062 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1064 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1065 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1066 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1067 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1069 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1070 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1071 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1072 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1074 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1075 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1076 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1077 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1079 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1080 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1081 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1082 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1084 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1085 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1086 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1087 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1089 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1090 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1091 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1092 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1094 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1095 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1096 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1097 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1099 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1101 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1103 // Instruction desc.
1104 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1105 ComplexPattern Imm, RegisterOperand ROWD,
1106 RegisterOperand ROWS = ROWD,
1107 InstrItinClass itin = NoItinerary> {
1108 dag OutOperandList = (outs ROWD:$wd);
1109 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1110 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1111 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1112 InstrItinClass Itinerary = itin;
1115 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1116 ComplexPattern Imm, RegisterOperand ROWD,
1117 RegisterOperand ROWS = ROWD,
1118 InstrItinClass itin = NoItinerary> {
1119 dag OutOperandList = (outs ROWD:$wd);
1120 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1121 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1122 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1123 InstrItinClass Itinerary = itin;
1126 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1127 ComplexPattern Imm, RegisterOperand ROWD,
1128 RegisterOperand ROWS = ROWD,
1129 InstrItinClass itin = NoItinerary> {
1130 dag OutOperandList = (outs ROWD:$wd);
1131 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1132 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1133 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1134 InstrItinClass Itinerary = itin;
1137 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1138 ComplexPattern Imm, RegisterOperand ROWD,
1139 RegisterOperand ROWS = ROWD,
1140 InstrItinClass itin = NoItinerary> {
1141 dag OutOperandList = (outs ROWD:$wd);
1142 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1143 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1144 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1145 InstrItinClass Itinerary = itin;
1148 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1149 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1150 RegisterOperand ROWS = ROWD,
1151 InstrItinClass itin = NoItinerary> {
1152 dag OutOperandList = (outs ROWD:$wd);
1153 dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
1154 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1155 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1156 InstrItinClass Itinerary = itin;
1159 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1160 SplatComplexPattern Mask, RegisterOperand ROWD,
1161 RegisterOperand ROWS = ROWD,
1162 InstrItinClass itin = NoItinerary> {
1163 dag OutOperandList = (outs ROWD:$wd);
1164 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m);
1165 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1166 // Note that binsxi and vselect treat the condition operand the opposite
1167 // way to each other.
1168 // (vselect cond, if_set, if_clear)
1169 // (BSEL_V cond, if_clear, if_set)
1170 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1172 InstrItinClass Itinerary = itin;
1173 string Constraints = "$wd = $wd_in";
1176 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1177 SplatComplexPattern ImmOp, RegisterOperand ROWD,
1178 RegisterOperand ROWS = ROWD,
1179 InstrItinClass itin = NoItinerary> :
1180 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1182 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1183 SplatComplexPattern ImmOp, RegisterOperand ROWD,
1184 RegisterOperand ROWS = ROWD,
1185 InstrItinClass itin = NoItinerary> :
1186 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1188 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1189 SplatComplexPattern SplatImm,
1190 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1191 InstrItinClass itin = NoItinerary> {
1192 dag OutOperandList = (outs ROWD:$wd);
1193 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1194 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1195 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1196 InstrItinClass Itinerary = itin;
1199 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1200 ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
1201 RegisterOperand ROD, RegisterOperand ROWS,
1202 InstrItinClass itin = NoItinerary> {
1203 dag OutOperandList = (outs ROD:$rd);
1204 dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
1205 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1206 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))];
1207 InstrItinClass Itinerary = itin;
1210 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1211 RegisterOperand ROWD, RegisterOperand ROWS,
1212 Operand ImmOp, ImmLeaf Imm,
1213 InstrItinClass itin = NoItinerary> {
1214 dag OutOperandList = (outs ROWD:$wd);
1215 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
1216 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1217 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1219 string Constraints = "$wd = $wd_in";
1220 InstrItinClass Itinerary = itin;
1223 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1224 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD,
1225 RegisterClass RCWS> :
1226 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n),
1227 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> {
1228 bit usesCustomInserter = 1;
1231 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1232 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1233 RegisterOperand ROWS = ROWD,
1234 InstrItinClass itin = NoItinerary> {
1235 dag OutOperandList = (outs ROWD:$wd);
1236 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1237 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1238 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1239 InstrItinClass Itinerary = itin;
1242 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1243 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1244 RegisterOperand ROWS = ROWD,
1245 InstrItinClass itin = NoItinerary> {
1246 dag OutOperandList = (outs ROWD:$wd);
1247 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1248 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1249 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1250 InstrItinClass Itinerary = itin;
1253 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1254 RegisterOperand ROWS = ROWD,
1255 InstrItinClass itin = NoItinerary> {
1256 dag OutOperandList = (outs ROWD:$wd);
1257 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1258 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1259 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1260 InstrItinClass Itinerary = itin;
1263 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1264 InstrItinClass itin = NoItinerary> {
1265 dag OutOperandList = (outs ROWD:$wd);
1266 dag InOperandList = (ins vsplat_simm10:$s10);
1267 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1268 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1269 list<dag> Pattern = [];
1270 bit hasSideEffects = 0;
1271 InstrItinClass Itinerary = itin;
1274 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1275 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1276 InstrItinClass itin = NoItinerary> {
1277 dag OutOperandList = (outs ROWD:$wd);
1278 dag InOperandList = (ins ROWS:$ws);
1279 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1280 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1281 InstrItinClass Itinerary = itin;
1284 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1285 SDPatternOperator OpNode, RegisterOperand ROWD,
1286 RegisterOperand ROS = ROWD,
1287 InstrItinClass itin = NoItinerary> {
1288 dag OutOperandList = (outs ROWD:$wd);
1289 dag InOperandList = (ins ROS:$rs);
1290 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1291 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1292 InstrItinClass Itinerary = itin;
1295 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1296 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1297 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1298 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1299 let usesCustomInserter = 1;
1302 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1303 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1304 InstrItinClass itin = NoItinerary> {
1305 dag OutOperandList = (outs ROWD:$wd);
1306 dag InOperandList = (ins ROWS:$ws);
1307 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1308 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1309 InstrItinClass Itinerary = itin;
1312 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1313 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1314 RegisterOperand ROWT = ROWD,
1315 InstrItinClass itin = NoItinerary> {
1316 dag OutOperandList = (outs ROWD:$wd);
1317 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1318 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1319 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1320 InstrItinClass Itinerary = itin;
1323 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1324 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1325 RegisterOperand ROWT = ROWD,
1326 InstrItinClass itin = NoItinerary> {
1327 dag OutOperandList = (outs ROWD:$wd);
1328 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1329 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1330 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1332 string Constraints = "$wd = $wd_in";
1333 InstrItinClass Itinerary = itin;
1336 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1337 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1338 InstrItinClass itin = NoItinerary> {
1339 dag OutOperandList = (outs ROWD:$wd);
1340 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1341 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1342 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1343 InstrItinClass Itinerary = itin;
1346 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1347 RegisterOperand ROWS = ROWD,
1348 RegisterOperand ROWT = ROWD,
1349 InstrItinClass itin = NoItinerary> {
1350 dag OutOperandList = (outs ROWD:$wd);
1351 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1352 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1353 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1355 string Constraints = "$wd = $wd_in";
1356 InstrItinClass Itinerary = itin;
1359 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1360 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1361 InstrItinClass itin = NoItinerary> {
1362 dag OutOperandList = (outs ROWD:$wd);
1363 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1364 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1365 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1367 InstrItinClass Itinerary = itin;
1368 string Constraints = "$wd = $wd_in";
1371 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1372 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1373 RegisterOperand ROWT = ROWD,
1374 InstrItinClass itin = NoItinerary> {
1375 dag OutOperandList = (outs ROWD:$wd);
1376 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1377 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1378 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1380 InstrItinClass Itinerary = itin;
1381 string Constraints = "$wd = $wd_in";
1384 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1385 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1386 RegisterOperand ROWT = ROWD,
1387 InstrItinClass itin = NoItinerary> :
1388 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1390 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1391 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1392 RegisterOperand ROWT = ROWD,
1393 InstrItinClass itin = NoItinerary> :
1394 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1396 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1397 dag OutOperandList = (outs);
1398 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1399 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1400 list<dag> Pattern = [];
1401 InstrItinClass Itinerary = NoItinerary;
1403 bit isTerminator = 1;
1404 bit hasDelaySlot = 1;
1405 list<Register> Defs = [AT];
1408 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1409 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1410 RegisterOperand ROS,
1411 InstrItinClass itin = NoItinerary> {
1412 dag OutOperandList = (outs ROWD:$wd);
1413 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n);
1414 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1415 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))];
1416 InstrItinClass Itinerary = itin;
1417 string Constraints = "$wd = $wd_in";
1420 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1421 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1422 RegisterOperand ROFS> :
1423 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs),
1424 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> {
1425 bit usesCustomInserter = 1;
1426 string Constraints = "$wd = $wd_in";
1429 class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1430 RegisterOperand ROWD, RegisterOperand ROFS,
1431 RegisterOperand ROIdx> :
1432 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
1433 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1435 bit usesCustomInserter = 1;
1436 string Constraints = "$wd = $wd_in";
1439 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1440 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1441 RegisterOperand ROWS = ROWD,
1442 InstrItinClass itin = NoItinerary> {
1443 dag OutOperandList = (outs ROWD:$wd);
1444 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
1445 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1446 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1450 InstrItinClass Itinerary = itin;
1451 string Constraints = "$wd = $wd_in";
1454 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1455 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1456 RegisterOperand ROWT = ROWD,
1457 InstrItinClass itin = NoItinerary> {
1458 dag OutOperandList = (outs ROWD:$wd);
1459 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1460 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1461 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1462 InstrItinClass Itinerary = itin;
1465 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1466 RegisterOperand ROWD,
1467 RegisterOperand ROWS = ROWD,
1468 InstrItinClass itin = NoItinerary> {
1469 dag OutOperandList = (outs ROWD:$wd);
1470 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1471 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1472 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1474 InstrItinClass Itinerary = itin;
1477 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1478 RegisterOperand ROWS = ROWD,
1479 RegisterOperand ROWT = ROWD> :
1480 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1481 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1483 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1485 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1487 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1489 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1492 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1493 MSA128BOpnd>, IsCommutable;
1494 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1495 MSA128HOpnd>, IsCommutable;
1496 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1497 MSA128WOpnd>, IsCommutable;
1498 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1499 MSA128DOpnd>, IsCommutable;
1501 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1502 MSA128BOpnd>, IsCommutable;
1503 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1504 MSA128HOpnd>, IsCommutable;
1505 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1506 MSA128WOpnd>, IsCommutable;
1507 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1508 MSA128DOpnd>, IsCommutable;
1510 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1511 MSA128BOpnd>, IsCommutable;
1512 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1513 MSA128HOpnd>, IsCommutable;
1514 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1515 MSA128WOpnd>, IsCommutable;
1516 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1517 MSA128DOpnd>, IsCommutable;
1519 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1520 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1521 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1522 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1524 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1526 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1528 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1530 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1533 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1534 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1535 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1536 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1538 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1541 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1543 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1545 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1547 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1550 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1552 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1554 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1556 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1559 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1561 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1563 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1565 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1568 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1570 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1572 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1574 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1577 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1578 MSA128BOpnd>, IsCommutable;
1579 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1580 MSA128HOpnd>, IsCommutable;
1581 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1582 MSA128WOpnd>, IsCommutable;
1583 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1584 MSA128DOpnd>, IsCommutable;
1586 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1587 MSA128BOpnd>, IsCommutable;
1588 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1589 MSA128HOpnd>, IsCommutable;
1590 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1591 MSA128WOpnd>, IsCommutable;
1592 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1593 MSA128DOpnd>, IsCommutable;
1595 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1596 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1597 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1598 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1600 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1602 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1604 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1606 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1609 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1611 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1613 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1615 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1618 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>;
1619 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>;
1620 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>;
1621 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>;
1623 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1625 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1627 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1629 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1633 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3,
1636 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4,
1639 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5,
1642 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6,
1646 dag OutOperandList = (outs MSA128BOpnd:$wd);
1647 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1649 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1650 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1652 MSA128BOpnd:$wd_in))];
1653 InstrItinClass Itinerary = NoItinerary;
1654 string Constraints = "$wd = $wd_in";
1657 class BMNZI_B_DESC {
1658 dag OutOperandList = (outs MSA128BOpnd:$wd);
1659 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1661 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1662 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1664 MSA128BOpnd:$wd_in))];
1665 InstrItinClass Itinerary = NoItinerary;
1666 string Constraints = "$wd = $wd_in";
1670 dag OutOperandList = (outs MSA128BOpnd:$wd);
1671 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1673 string AsmString = "bmz.v\t$wd, $ws, $wt";
1674 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1677 InstrItinClass Itinerary = NoItinerary;
1678 string Constraints = "$wd = $wd_in";
1682 dag OutOperandList = (outs MSA128BOpnd:$wd);
1683 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1685 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1686 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1689 InstrItinClass Itinerary = NoItinerary;
1690 string Constraints = "$wd = $wd_in";
1693 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1694 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1695 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1696 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1698 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1700 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1702 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1704 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1707 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1708 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1709 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1710 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1712 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1715 dag OutOperandList = (outs MSA128BOpnd:$wd);
1716 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1718 string AsmString = "bsel.v\t$wd, $ws, $wt";
1719 // Note that vselect and BSEL_V treat the condition operand the opposite way
1721 // (vselect cond, if_set, if_clear)
1722 // (BSEL_V cond, if_clear, if_set)
1723 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1724 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1726 InstrItinClass Itinerary = NoItinerary;
1727 string Constraints = "$wd = $wd_in";
1730 class BSELI_B_DESC {
1731 dag OutOperandList = (outs MSA128BOpnd:$wd);
1732 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1734 string AsmString = "bseli.b\t$wd, $ws, $u8";
1735 // Note that vselect and BSEL_V treat the condition operand the opposite way
1737 // (vselect cond, if_set, if_clear)
1738 // (BSEL_V cond, if_clear, if_set)
1739 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1742 InstrItinClass Itinerary = NoItinerary;
1743 string Constraints = "$wd = $wd_in";
1746 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1747 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1748 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1749 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1751 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1753 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1755 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1757 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1760 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1761 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1762 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1763 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1765 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1767 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1769 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1771 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1773 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1776 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1778 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1780 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1782 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1786 dag OutOperandList = (outs GPR32Opnd:$rd);
1787 dag InOperandList = (ins MSA128CROpnd:$cs);
1788 string AsmString = "cfcmsa\t$rd, $cs";
1789 InstrItinClass Itinerary = NoItinerary;
1790 bit hasSideEffects = 1;
1793 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1794 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1795 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1796 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1798 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1799 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1800 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1801 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1803 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1804 vsplati8_simm5, MSA128BOpnd>;
1805 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1806 vsplati16_simm5, MSA128HOpnd>;
1807 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1808 vsplati32_simm5, MSA128WOpnd>;
1809 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1810 vsplati64_simm5, MSA128DOpnd>;
1812 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1813 vsplati8_uimm5, MSA128BOpnd>;
1814 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1815 vsplati16_uimm5, MSA128HOpnd>;
1816 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1817 vsplati32_uimm5, MSA128WOpnd>;
1818 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1819 vsplati64_uimm5, MSA128DOpnd>;
1821 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1822 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1823 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1824 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1826 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1827 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1828 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1829 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1831 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1832 vsplati8_simm5, MSA128BOpnd>;
1833 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1834 vsplati16_simm5, MSA128HOpnd>;
1835 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1836 vsplati32_simm5, MSA128WOpnd>;
1837 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1838 vsplati64_simm5, MSA128DOpnd>;
1840 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1841 vsplati8_uimm5, MSA128BOpnd>;
1842 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1843 vsplati16_uimm5, MSA128HOpnd>;
1844 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1845 vsplati32_uimm5, MSA128WOpnd>;
1846 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1847 vsplati64_uimm5, MSA128DOpnd>;
1849 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1850 uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1852 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1853 uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1855 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1856 uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1858 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1859 uimm1_ptr, immZExt1Ptr, GPR64Opnd,
1862 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1863 uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1865 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1866 uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1868 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1869 uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1872 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32,
1873 uimm2_ptr, immZExt2Ptr, FGR32,
1875 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64,
1876 uimm1_ptr, immZExt1Ptr, FGR64,
1880 dag OutOperandList = (outs);
1881 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1882 string AsmString = "ctcmsa\t$cd, $rs";
1883 InstrItinClass Itinerary = NoItinerary;
1884 bit hasSideEffects = 1;
1887 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1888 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1889 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1890 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1892 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1893 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1894 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1895 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1897 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1898 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1900 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1901 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1903 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1904 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1907 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1908 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1910 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1911 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1913 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1914 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1917 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1918 MSA128HOpnd, MSA128BOpnd,
1919 MSA128BOpnd>, IsCommutable;
1920 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1921 MSA128WOpnd, MSA128HOpnd,
1922 MSA128HOpnd>, IsCommutable;
1923 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1924 MSA128DOpnd, MSA128WOpnd,
1925 MSA128WOpnd>, IsCommutable;
1927 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1928 MSA128HOpnd, MSA128BOpnd,
1929 MSA128BOpnd>, IsCommutable;
1930 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1931 MSA128WOpnd, MSA128HOpnd,
1932 MSA128HOpnd>, IsCommutable;
1933 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1934 MSA128DOpnd, MSA128WOpnd,
1935 MSA128WOpnd>, IsCommutable;
1937 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1938 MSA128HOpnd, MSA128BOpnd,
1940 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1941 MSA128WOpnd, MSA128HOpnd,
1943 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1944 MSA128DOpnd, MSA128WOpnd,
1947 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1948 MSA128HOpnd, MSA128BOpnd,
1950 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1951 MSA128WOpnd, MSA128HOpnd,
1953 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1954 MSA128DOpnd, MSA128WOpnd,
1957 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1959 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1962 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1964 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1967 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1969 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1972 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1974 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1977 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1978 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1980 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1981 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1983 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1985 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
1988 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
1990 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
1993 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
1995 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
1998 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2000 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2003 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2005 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2008 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2010 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2013 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2015 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2018 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2019 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2021 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2022 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2023 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2024 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2026 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2027 // the second operand. We therefore need a pseudo-insn in order to invent the
2028 // 1.0 when we only need to match ISD::FEXP2.
2029 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2030 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2031 let usesCustomInserter = 1 in {
2032 class FEXP2_W_1_PSEUDO_DESC :
2033 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2034 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2035 class FEXP2_D_1_PSEUDO_DESC :
2036 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2037 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2040 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2041 MSA128WOpnd, MSA128HOpnd>;
2042 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2043 MSA128DOpnd, MSA128WOpnd>;
2045 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2046 MSA128WOpnd, MSA128HOpnd>;
2047 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2048 MSA128DOpnd, MSA128WOpnd>;
2050 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2051 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2053 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2054 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2056 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2057 MSA128WOpnd, MSA128HOpnd>;
2058 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2059 MSA128DOpnd, MSA128WOpnd>;
2061 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2062 MSA128WOpnd, MSA128HOpnd>;
2063 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2064 MSA128DOpnd, MSA128WOpnd>;
2066 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2067 MSA128BOpnd, GPR32Opnd>;
2068 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2069 MSA128HOpnd, GPR32Opnd>;
2070 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2071 MSA128WOpnd, GPR32Opnd>;
2072 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2073 MSA128DOpnd, GPR64Opnd>;
2075 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2077 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2080 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2081 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2083 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2084 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2086 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2087 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2089 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2091 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2094 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2095 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2097 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2099 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2102 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2103 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2105 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2106 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2108 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2109 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2111 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2112 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2114 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2116 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2119 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2120 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2122 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2123 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2125 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2126 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2128 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2129 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2131 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2132 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2134 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2135 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2137 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2138 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2140 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2141 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2143 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2145 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2148 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2150 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2153 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2155 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2158 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2160 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2163 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2165 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2168 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2170 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2173 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2175 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2178 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2179 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2180 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2181 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2183 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2185 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2188 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2190 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2193 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2194 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2195 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2196 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2197 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2198 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2200 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2201 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2202 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2203 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2204 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2205 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2207 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2208 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2209 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2210 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2211 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2212 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2214 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2215 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2216 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2217 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2218 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2219 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2221 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2222 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2223 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2224 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2226 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2227 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2228 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2229 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2231 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2232 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2233 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2234 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2236 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2237 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2238 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2239 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2241 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4,
2242 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>;
2243 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3,
2244 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>;
2245 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2,
2246 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>;
2247 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1,
2248 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>;
2250 class INSERT_B_VIDX_PSEUDO_DESC :
2251 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
2252 class INSERT_H_VIDX_PSEUDO_DESC :
2253 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
2254 class INSERT_W_VIDX_PSEUDO_DESC :
2255 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
2256 class INSERT_D_VIDX_PSEUDO_DESC :
2257 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
2259 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2261 MSA128WOpnd, FGR32Opnd>;
2262 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2264 MSA128DOpnd, FGR64Opnd>;
2266 class INSERT_FW_VIDX_PSEUDO_DESC :
2267 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
2268 class INSERT_FD_VIDX_PSEUDO_DESC :
2269 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
2271 class INSERT_B_VIDX64_PSEUDO_DESC :
2272 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
2273 class INSERT_H_VIDX64_PSEUDO_DESC :
2274 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
2275 class INSERT_W_VIDX64_PSEUDO_DESC :
2276 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
2277 class INSERT_D_VIDX64_PSEUDO_DESC :
2278 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
2280 class INSERT_FW_VIDX64_PSEUDO_DESC :
2281 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
2282 class INSERT_FD_VIDX64_PSEUDO_DESC :
2283 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
2285 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4,
2287 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3,
2289 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2,
2291 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1,
2294 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2295 ValueType TyNode, RegisterOperand ROWD,
2296 Operand MemOpnd, ComplexPattern Addr = addrimm10,
2297 InstrItinClass itin = NoItinerary> {
2298 dag OutOperandList = (outs ROWD:$wd);
2299 dag InOperandList = (ins MemOpnd:$addr);
2300 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2301 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2302 InstrItinClass Itinerary = itin;
2303 string DecoderMethod = "DecodeMSA128Mem";
2306 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
2307 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd,
2308 mem_simm10_lsl1, addrimm10lsl1>;
2309 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd,
2310 mem_simm10_lsl2, addrimm10lsl2>;
2311 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd,
2312 mem_simm10_lsl3, addrimm10lsl3>;
2314 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2315 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2316 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2317 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2319 class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2320 InstrItinClass itin = NoItinerary> {
2321 dag OutOperandList = (outs RORD:$rd);
2322 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa);
2323 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2324 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt,
2326 immZExt2Lsa:$sa)))];
2327 InstrItinClass Itinerary = itin;
2330 class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>;
2331 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
2333 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2335 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2338 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2340 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2343 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2344 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2345 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2346 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2348 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2349 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2350 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2351 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2353 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2354 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2355 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2356 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2358 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2359 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2360 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2361 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2363 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2365 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2367 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2369 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2372 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2374 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2376 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2378 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2381 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2382 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2383 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2384 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2386 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2387 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2388 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2389 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2391 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2392 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2393 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2394 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2396 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2398 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2400 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2402 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2405 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2407 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2409 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2411 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2414 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2415 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2416 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2417 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2419 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2420 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2421 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2422 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2425 dag OutOperandList = (outs MSA128BOpnd:$wd);
2426 dag InOperandList = (ins MSA128BOpnd:$ws);
2427 string AsmString = "move.v\t$wd, $ws";
2428 list<dag> Pattern = [];
2429 InstrItinClass Itinerary = NoItinerary;
2432 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2434 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2437 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2439 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2442 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2443 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2444 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2445 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2447 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2449 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2452 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2454 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2457 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2458 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2459 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2460 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2462 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2463 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2464 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2465 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2467 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2468 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2469 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2470 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2472 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2473 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2474 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2475 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2477 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2480 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2481 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2482 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2483 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2485 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2487 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2488 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2489 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2490 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2492 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2493 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2494 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2495 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2497 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2498 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2499 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2500 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2502 class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3,
2503 immZExt3, MSA128BOpnd>;
2504 class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4,
2505 immZExt4, MSA128HOpnd>;
2506 class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5,
2507 immZExt5, MSA128WOpnd>;
2508 class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6,
2509 immZExt6, MSA128DOpnd>;
2511 class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3,
2512 immZExt3, MSA128BOpnd>;
2513 class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4,
2514 immZExt4, MSA128HOpnd>;
2515 class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5,
2516 immZExt5, MSA128WOpnd>;
2517 class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6,
2518 immZExt6, MSA128DOpnd>;
2520 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2521 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2522 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2524 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2525 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2526 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2527 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2529 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2530 MSA128BOpnd, MSA128BOpnd, uimm4,
2532 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2533 MSA128HOpnd, MSA128HOpnd, uimm3,
2535 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2536 MSA128WOpnd, MSA128WOpnd, uimm2,
2538 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2539 MSA128DOpnd, MSA128DOpnd, uimm1,
2542 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2543 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2544 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2545 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2547 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2549 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2551 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2553 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2556 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2558 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2560 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2562 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2565 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2567 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2569 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2571 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2574 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2575 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2576 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2577 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2579 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2581 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2583 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2585 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2588 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2589 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2590 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2591 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2593 class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3,
2594 immZExt3, MSA128BOpnd>;
2595 class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4,
2596 immZExt4, MSA128HOpnd>;
2597 class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5,
2598 immZExt5, MSA128WOpnd>;
2599 class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6,
2600 immZExt6, MSA128DOpnd>;
2602 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2603 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2604 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2605 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2607 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2609 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2611 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2613 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2616 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2617 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2618 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2619 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2621 class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3,
2622 immZExt3, MSA128BOpnd>;
2623 class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4,
2624 immZExt4, MSA128HOpnd>;
2625 class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5,
2626 immZExt5, MSA128WOpnd>;
2627 class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
2628 immZExt6, MSA128DOpnd>;
2630 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2631 ValueType TyNode, RegisterOperand ROWD,
2632 Operand MemOpnd, ComplexPattern Addr = addrimm10,
2633 InstrItinClass itin = NoItinerary> {
2634 dag OutOperandList = (outs);
2635 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2636 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2637 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2638 InstrItinClass Itinerary = itin;
2639 string DecoderMethod = "DecodeMSA128Mem";
2642 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
2643 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd,
2644 mem_simm10_lsl1, addrimm10lsl1>;
2645 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd,
2646 mem_simm10_lsl2, addrimm10lsl2>;
2647 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd,
2648 mem_simm10_lsl3, addrimm10lsl3>;
2650 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2652 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2654 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2656 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2659 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2661 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2663 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2665 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2668 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2670 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2672 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2674 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2677 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2679 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2681 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2683 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2686 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2687 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2688 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2689 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2691 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2693 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2695 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2697 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2700 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2701 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2702 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2703 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2705 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2706 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2707 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2708 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2710 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2713 // Instruction defs.
2714 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2715 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2716 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2717 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2719 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2720 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2721 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2722 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2724 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2725 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2726 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2727 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2729 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2730 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2731 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2732 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2734 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2735 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2736 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2737 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2739 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2740 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2741 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2742 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2744 def AND_V : AND_V_ENC, AND_V_DESC;
2745 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2746 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2749 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2750 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2753 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2754 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2758 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2760 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2761 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2762 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2763 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2765 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2766 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2767 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2768 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2770 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2771 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2772 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2773 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2775 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2776 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2777 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2778 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2780 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2781 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2782 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2783 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2785 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2786 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2787 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2788 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2790 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2791 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2792 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2793 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2795 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2796 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2797 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2798 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2800 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2801 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2802 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2803 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2805 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2806 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2807 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2808 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2810 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2811 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2812 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2813 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2815 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2816 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2817 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2818 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2820 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2822 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2824 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2826 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2828 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2829 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2830 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2831 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2833 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2834 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2835 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2836 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2838 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2839 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2840 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2841 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2843 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2845 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2847 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2848 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2849 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2850 // Note that vselect and BSEL_V treat the condition operand the opposite way
2852 // (vselect cond, if_set, if_clear)
2853 // (BSEL_V cond, if_clear, if_set)
2854 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2855 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2856 let Constraints = "$wd_in = $wd";
2859 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2860 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2861 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2862 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2863 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2865 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2867 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2868 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2869 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2870 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2872 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2873 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2874 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2875 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2877 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2878 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2879 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2880 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2882 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2884 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2885 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2886 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2887 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2889 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2890 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2891 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2892 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2894 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2896 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2897 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2898 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2899 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2901 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2902 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2903 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2904 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2906 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2907 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2908 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2909 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2911 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2912 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2913 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2914 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2916 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2917 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2918 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2919 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2921 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2922 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2923 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2924 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2926 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2927 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2928 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2929 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2931 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2932 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2933 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2934 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2936 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2937 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2938 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2939 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
2941 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2942 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2943 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64;
2945 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2946 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2948 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2950 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2951 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2952 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2953 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2955 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2956 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2957 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2958 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2960 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2961 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2962 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2964 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2965 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2966 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2968 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2969 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2970 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2972 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2973 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2974 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2976 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2977 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2978 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2980 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2981 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2982 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2984 def FADD_W : FADD_W_ENC, FADD_W_DESC;
2985 def FADD_D : FADD_D_ENC, FADD_D_DESC;
2987 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2988 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2990 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2991 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2993 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2994 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2996 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2997 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2999 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
3000 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
3002 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
3003 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
3005 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
3006 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
3008 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
3009 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
3011 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
3012 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
3014 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
3015 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
3017 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
3018 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
3020 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
3021 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
3023 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3024 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3026 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3027 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3029 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3030 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3031 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3032 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3034 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3035 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3037 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3038 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3040 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3041 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3043 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3044 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3046 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3047 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3049 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3050 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3052 def FILL_B : FILL_B_ENC, FILL_B_DESC;
3053 def FILL_H : FILL_H_ENC, FILL_H_DESC;
3054 def FILL_W : FILL_W_ENC, FILL_W_DESC;
3055 def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
3056 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3057 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3059 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3060 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3062 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3063 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3065 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3066 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3068 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3069 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3071 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3072 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3074 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3075 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3077 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3078 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3080 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3081 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3083 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3084 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3086 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3087 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3089 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3090 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3092 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3093 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3095 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3096 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3098 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3099 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3101 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3102 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3104 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3105 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3107 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3108 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3110 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3111 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3113 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3114 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3116 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3117 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3119 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3120 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3122 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3123 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3125 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3126 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3128 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3129 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3131 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3132 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3134 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3135 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3137 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3138 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3140 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3141 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3143 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3144 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3146 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3147 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3148 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3150 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3151 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3152 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3154 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3155 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3156 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3158 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3159 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3160 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3162 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3163 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3164 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3165 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3167 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3168 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3169 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3170 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3172 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3173 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3174 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3175 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3177 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3178 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3179 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3180 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3182 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3183 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3184 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3185 def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
3187 // INSERT_FW_PSEUDO defined after INSVE_W
3188 // INSERT_FD_PSEUDO defined after INSVE_D
3190 // There is a fourth operand that is not present in the encoding. Use a
3191 // custom decoder to get a chance to add it.
3192 let DecoderMethod = "DecodeINSVE_DF" in {
3193 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3194 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3195 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3196 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3199 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3200 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3202 def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3203 def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3204 def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3205 def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3206 def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3207 def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3209 def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
3210 def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
3211 def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
3212 def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
3213 def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
3214 def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
3216 def LD_B: LD_B_ENC, LD_B_DESC;
3217 def LD_H: LD_H_ENC, LD_H_DESC;
3218 def LD_W: LD_W_ENC, LD_W_DESC;
3219 def LD_D: LD_D_ENC, LD_D_DESC;
3221 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3222 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3223 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3224 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3226 def LSA : LSA_ENC, LSA_DESC;
3227 def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
3229 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3230 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3232 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3233 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3235 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3236 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3237 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3238 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3240 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3241 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3242 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3243 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3245 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3246 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3247 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3248 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3250 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3251 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3252 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3253 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3255 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3256 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3257 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3258 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3260 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3261 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3262 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3263 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3265 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3266 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3267 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3268 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3270 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3271 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3272 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3273 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3275 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3276 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3277 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3278 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3280 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3281 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3282 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3283 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3285 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3286 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3287 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3288 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3290 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3291 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3292 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3293 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3295 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3296 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3297 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3298 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3300 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3302 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3303 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3305 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3306 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3308 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3309 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3310 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3311 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3313 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3314 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3316 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3317 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3319 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3320 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3321 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3322 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3324 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3325 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3326 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3327 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3329 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3330 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3331 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3332 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3334 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3335 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3336 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3339 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3340 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3343 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3344 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3348 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3350 def OR_V : OR_V_ENC, OR_V_DESC;
3351 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3352 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3355 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3356 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3359 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3360 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3364 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3366 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3367 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3368 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3369 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3371 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3372 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3373 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3374 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3376 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3377 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3378 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3379 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3381 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3382 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3383 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3384 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3386 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3387 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3388 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3389 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3391 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3392 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3393 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3395 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3396 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3397 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3398 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3400 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3401 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3402 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3403 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3405 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3406 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3407 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3408 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3410 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3411 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3412 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3413 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3415 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3416 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3417 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3418 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3420 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3421 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3422 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3423 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3425 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3426 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3427 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3428 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3430 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3431 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3432 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3433 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3435 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3436 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3437 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3438 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3440 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3441 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3442 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3443 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3445 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3446 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3447 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3448 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3450 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3451 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3452 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3453 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3455 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3456 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3457 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3458 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3460 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3461 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3462 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3463 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3465 def ST_B: ST_B_ENC, ST_B_DESC;
3466 def ST_H: ST_H_ENC, ST_H_DESC;
3467 def ST_W: ST_W_ENC, ST_W_DESC;
3468 def ST_D: ST_D_ENC, ST_D_DESC;
3470 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3471 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3472 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3473 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3475 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3476 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3477 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3478 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3480 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3481 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3482 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3483 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3485 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3486 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3487 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3488 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3490 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3491 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3492 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3493 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3495 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3496 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3497 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3498 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3500 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3501 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3502 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3503 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3505 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3506 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3507 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3510 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3511 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3514 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3515 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3519 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3522 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3523 Pat<pattern, result>, Requires<pred>;
3525 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3526 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3528 def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>;
3529 def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
3530 def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>;
3532 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr),
3533 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>;
3534 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr),
3535 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>;
3536 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr),
3537 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>;
3539 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3540 RegisterOperand ROWS = ROWD,
3541 InstrItinClass itin = NoItinerary> :
3542 MSAPseudo<(outs ROWD:$wd),
3544 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3545 InstrItinClass Itinerary = itin;
3547 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3548 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3550 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3551 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3554 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3555 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3556 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3557 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3559 // These are endian-independent because the element size doesnt change
3560 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3561 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3562 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3563 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3564 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3565 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3567 // Little endian bitcasts are always no-ops
3568 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3569 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3570 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3571 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3572 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3573 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3575 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3576 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3577 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3578 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3579 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3581 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3582 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3583 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3584 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3585 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3587 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3588 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3589 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3590 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3591 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3593 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3594 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3595 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3596 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3597 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3599 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3600 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3601 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3602 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3603 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3605 // Big endian bitcasts expand to shuffle instructions.
3606 // This is because bitcast is defined to be a store/load sequence and the
3607 // vector store/load instructions are mixed-endian with respect to the vector
3608 // as a whole (little endian with respect to element order, but big endian
3611 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3612 RegisterClass DstRC, MSAInst Insn,
3613 RegisterClass ViaRC> :
3614 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3615 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3619 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3620 RegisterClass DstRC, MSAInst Insn,
3621 RegisterClass ViaRC> :
3622 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3623 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3627 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3628 RegisterClass DstRC> :
3629 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3631 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3632 RegisterClass DstRC> :
3633 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3635 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3636 RegisterClass DstRC> :
3637 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3641 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3646 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3647 RegisterClass DstRC> :
3648 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3650 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3651 RegisterClass DstRC> :
3652 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3654 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3655 RegisterClass DstRC> :
3656 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3658 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3659 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3660 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3661 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3662 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3663 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3665 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3666 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3667 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3668 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3669 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3671 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3672 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3673 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3674 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3675 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3677 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3678 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3679 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3680 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3681 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3683 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3684 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3685 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3686 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3687 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3689 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3690 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3691 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3692 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3693 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3695 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3696 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3697 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3698 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3699 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3701 // Pseudos used to implement BNZ.df, and BZ.df
3703 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3705 InstrItinClass itin = NoItinerary> :
3706 MipsPseudo<(outs GPR32:$dst),
3708 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3709 bit usesCustomInserter = 1;
3712 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3713 MSA128B, NoItinerary>;
3714 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3715 MSA128H, NoItinerary>;
3716 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3717 MSA128W, NoItinerary>;
3718 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3719 MSA128D, NoItinerary>;
3720 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3721 MSA128B, NoItinerary>;
3723 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3724 MSA128B, NoItinerary>;
3725 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3726 MSA128H, NoItinerary>;
3727 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3728 MSA128W, NoItinerary>;
3729 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3730 MSA128D, NoItinerary>;
3731 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3732 MSA128B, NoItinerary>;
3734 // Pseudoes used to implement transparent fp16 support.
3736 let Predicates = [HasMSA] in {
3737 def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
3738 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> {
3739 let usesCustomInserter = 1;
3742 def LD_F16 : MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr),
3743 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]> {
3744 let usesCustomInserter = 1;
3747 def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd),
3748 (ins MSA128F16:$ws),
3749 [(set FGR32Opnd:$fd,
3750 (f32 (fpextend MSA128F16:$ws)))]> {
3751 let usesCustomInserter = 1;
3754 def MSA_FP_ROUND_W_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
3755 (ins FGR32Opnd:$fs),
3756 [(set MSA128F16:$wd,
3757 (f16 (fpround FGR32Opnd:$fs)))]> {
3758 let usesCustomInserter = 1;
3761 def MSA_FP_EXTEND_D_PSEUDO : MipsPseudo<(outs FGR64Opnd:$fd),
3762 (ins MSA128F16:$ws),
3763 [(set FGR64Opnd:$fd,
3764 (f64 (fpextend MSA128F16:$ws)))]> {
3765 let usesCustomInserter = 1;
3768 def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
3769 (ins FGR64Opnd:$fs),
3770 [(set MSA128F16:$wd,
3771 (f16 (fpround FGR64Opnd:$fs)))]> {
3772 let usesCustomInserter = 1;
3775 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
3776 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>;
3778 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
3779 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
3780 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
3781 ISA_MIPS1_NOT_32R6_64R6;
3784 def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
3786 SDNode *BV = N->getOperand(0).getNode();
3787 EVT EltTy = N->getValueType(0).getVectorElementType();
3789 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
3790 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
3793 def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>;
3794 def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>;
3795 def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>;
3797 def vsplati8imm7 : PatFrag<(ops node:$wt),
3798 (and node:$wt, (vsplati8 immi32Cst7))>;
3799 def vsplati16imm15 : PatFrag<(ops node:$wt),
3800 (and node:$wt, (vsplati16 immi32Cst15))>;
3801 def vsplati32imm31 : PatFrag<(ops node:$wt),
3802 (and node:$wt, (vsplati32 immi32Cst31))>;
3803 def vsplati64imm63 : PatFrag<(ops node:$wt),
3804 (and node:$wt, vsplati64_imm_eq_63)>;
3806 class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> :
3807 MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))),
3808 (VT (Insn VT:$ws, VT:$wt))>;
3810 class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> :
3811 MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))),
3812 (VT (Insn VT:$ws, VT:$wt))>;
3814 multiclass MSAShiftPats<SDNode Node, string Insn> {
3815 def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B),
3816 (vsplati8 immi32Cst7)>;
3817 def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H),
3818 (vsplati16 immi32Cst15)>;
3819 def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W),
3820 (vsplati32 immi32Cst31)>;
3821 def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt,
3822 vsplati64_imm_eq_63)))),
3823 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3826 multiclass MSABitPats<SDNode Node, string Insn> {
3827 def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>;
3828 def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>;
3829 def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>;
3830 def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1),
3831 (vsplati64imm63 v2i64:$wt))),
3832 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3835 defm : MSAShiftPats<shl, "SLL">;
3836 defm : MSAShiftPats<srl, "SRL">;
3837 defm : MSAShiftPats<sra, "SRA">;
3838 defm : MSABitPats<xor, "BNEG">;
3839 defm : MSABitPats<or, "BSET">;
3841 def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1,
3842 (vsplati8imm7 v16i8:$wt)),
3844 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>;
3845 def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1,
3846 (vsplati16imm15 v8i16:$wt)),
3848 (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>;
3849 def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1,
3850 (vsplati32imm31 v4i32:$wt)),
3852 (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>;
3853 def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
3854 (vsplati64imm63 v2i64:$wt)),
3855 (bitconvert (v4i32 immAllOnesV)))),
3856 (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>;
3858 // Vector extraction with fixed index.
3860 // Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
3861 // COPY_U_W, even for the zero-extended case. This is because our forward
3862 // compatibility strategy is to consider registers to be infinitely
3863 // sign-extended so that a MIPS64 can execute MIPS32 code without getting
3864 // different register values.
3865 def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx),
3866 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3867 def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx),
3868 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3870 // Extracting 64-bit values on MSA64 should always use COPY_S_D rather than
3871 // COPY_U_D, even for the zero-extended case. This is because our forward
3872 // compatibility strategy is to consider registers to be infinitely
3873 // sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64
3874 // code without getting different register values.
3875 def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx),
3876 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3877 def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx),
3878 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3880 // Vector extraction with variable index
3881 def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3882 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3886 def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3887 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3891 def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3892 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3896 def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3897 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3900 GPR64), [HasMSA, IsGP64bit]>;
3902 def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3903 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3907 def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3908 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3912 def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3913 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3917 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3918 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3921 GPR64), [HasMSA, IsGP64bit]>;
3923 def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3924 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3927 def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3928 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
3932 // Vector extraction with variable index (N64 ABI)
3934 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3935 (SRA (COPY_TO_REGCLASS
3936 (i32 (EXTRACT_SUBREG
3939 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3944 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
3945 (SRA (COPY_TO_REGCLASS
3946 (i32 (EXTRACT_SUBREG
3949 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3954 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
3956 (i32 (EXTRACT_SUBREG
3959 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3963 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
3965 (i64 (EXTRACT_SUBREG
3967 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3969 GPR64), [HasMSA, IsGP64bit]>;
3972 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
3973 (SRL (COPY_TO_REGCLASS
3974 (i32 (EXTRACT_SUBREG
3977 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3982 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
3983 (SRL (COPY_TO_REGCLASS
3984 (i32 (EXTRACT_SUBREG
3987 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3992 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
3994 (i32 (EXTRACT_SUBREG
3996 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4000 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
4002 (i64 (EXTRACT_SUBREG
4004 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4007 [HasMSA, IsGP64bit]>;
4010 (f32 (vector_extract v4f32:$ws, i64:$idx)),
4011 (f32 (EXTRACT_SUBREG
4013 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4016 (f64 (vector_extract v2f64:$ws, i64:$idx)),
4017 (f64 (EXTRACT_SUBREG
4019 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),