1 //===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe the MIPS MT instructions format
13 // opcode - operation code.
14 // rt - destination register
16 //===----------------------------------------------------------------------===//
18 class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
20 let DecoderNamespace = "Mips";
21 let EncodingPredicates = [HasStdEnc];
24 class OPCODE1<bits<1> Val> {
28 def OPCODE_SC_D : OPCODE1<0b0>;
29 def OPCODE_SC_E : OPCODE1<0b1>;
31 class FIELD5<bits<5> Val> {
35 def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
36 def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
37 def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
43 let Inst{31-26} = 0b010000; // COP0
44 let Inst{25-21} = 0b01011; // MFMC0
46 let Inst{15-11} = Op1.Value;
47 let Inst{10-6} = Op2.Value;
48 let Inst{5} = sc.Value;
50 let Inst{2-0} = 0b001;
53 class SPECIAL3_MT_FORK : MipsMTInst {
59 let Inst{31-26} = 0b011111; // SPECIAL3
63 let Inst{10-6} = 0b00000;
64 let Inst{5-0} = 0b001000; // FORK
67 class SPECIAL3_MT_YIELD : MipsMTInst {
72 let Inst{31-26} = 0b011111; // SPECIAL3
74 let Inst{20-16} = 0b00000;
76 let Inst{10-6} = 0b00000;
77 let Inst{5-0} = 0b001001; // FORK