1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsABIInfo.h"
11 #include "MipsMachineFunction.h"
12 #include "MipsSubtarget.h"
13 #include "MipsTargetMachine.h"
14 #include "llvm/CodeGen/MachineFrameInfo.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/CodeGen/PseudoSourceValue.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
23 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
24 cl::desc("Always use $gp as the global base register."));
26 MipsFunctionInfo::~MipsFunctionInfo() = default;
28 bool MipsFunctionInfo::globalBaseRegSet() const {
32 unsigned MipsFunctionInfo::getGlobalBaseReg() {
33 // Return if it has already been initialized.
37 MipsSubtarget const &STI =
38 static_cast<const MipsSubtarget &>(MF.getSubtarget());
40 const TargetRegisterClass *RC =
42 ? &Mips::CPU16RegsRegClass
43 : static_cast<const MipsTargetMachine &>(MF.getTarget())
46 ? &Mips::GPR64RegClass
47 : &Mips::GPR32RegClass;
48 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
51 void MipsFunctionInfo::createEhDataRegsFI() {
52 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
53 for (int I = 0; I < 4; ++I) {
54 const TargetRegisterClass &RC =
55 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
57 : Mips::GPR32RegClass;
59 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
60 TRI.getSpillAlignment(RC), false);
64 void MipsFunctionInfo::createISRRegFI() {
65 // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
66 // The current implementation only supports Mips32r2+ not Mips64rX. Status
67 // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
68 // however Mips32r2+ is the supported architecture.
69 const TargetRegisterClass &RC = Mips::GPR32RegClass;
70 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
72 for (int I = 0; I < 2; ++I)
73 ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
74 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
77 bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
78 return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
79 || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
82 bool MipsFunctionInfo::isISRRegFI(int FI) const {
83 return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
85 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) {
86 return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES));
89 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) {
90 return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV));
93 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
94 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
95 if (MoveF64ViaSpillFI == -1) {
96 MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
97 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
99 return MoveF64ViaSpillFI;
102 void MipsFunctionInfo::anchor() {}