1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/Dominators.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Instructions.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
38 #define DEBUG_TYPE "mips-isel"
40 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
41 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
42 if (Subtarget->inMips16Mode())
44 return MipsDAGToDAGISel::runOnMachineFunction(MF);
47 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
48 AU.addRequired<DominatorTreeWrapperPass>();
49 SelectionDAGISel::getAnalysisUsage(AU);
52 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
53 MachineFunction &MF) {
54 MachineInstrBuilder MIB(MF, &MI);
55 unsigned Mask = MI.getOperand(1).getImm();
57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
60 MIB.addReg(Mips::DSPPos, Flag);
63 MIB.addReg(Mips::DSPSCount, Flag);
66 MIB.addReg(Mips::DSPCarry, Flag);
69 MIB.addReg(Mips::DSPOutFlag, Flag);
72 MIB.addReg(Mips::DSPCCond, Flag);
75 MIB.addReg(Mips::DSPEFI, Flag);
78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
79 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
81 llvm_unreachable("Could not map int to register");
82 case 0: return Mips::MSAIR;
83 case 1: return Mips::MSACSR;
84 case 2: return Mips::MSAAccess;
85 case 3: return Mips::MSASave;
86 case 4: return Mips::MSAModify;
87 case 5: return Mips::MSARequest;
88 case 6: return Mips::MSAMap;
89 case 7: return Mips::MSAUnmap;
93 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
94 const MachineInstr& MI) {
95 unsigned DstReg = 0, ZeroReg = 0;
97 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
98 if ((MI.getOpcode() == Mips::ADDiu) &&
99 (MI.getOperand(1).getReg() == Mips::ZERO) &&
100 (MI.getOperand(2).isImm()) &&
101 (MI.getOperand(2).getImm() == 0)) {
102 DstReg = MI.getOperand(0).getReg();
103 ZeroReg = Mips::ZERO;
104 } else if ((MI.getOpcode() == Mips::DADDiu) &&
105 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
106 (MI.getOperand(2).isImm()) &&
107 (MI.getOperand(2).getImm() == 0)) {
108 DstReg = MI.getOperand(0).getReg();
109 ZeroReg = Mips::ZERO_64;
115 // Replace uses with ZeroReg.
116 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
117 E = MRI->use_end(); U != E;) {
118 MachineOperand &MO = *U;
119 unsigned OpNo = U.getOperandNo();
120 MachineInstr *MI = MO.getParent();
123 // Do not replace if it is a phi's operand or is tied to def operand.
124 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
127 // Also, we have to check that the register class of the operand
128 // contains the zero register.
129 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
138 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
139 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
141 if (!MipsFI->globalBaseRegSet())
144 MachineBasicBlock &MBB = MF.front();
145 MachineBasicBlock::iterator I = MBB.begin();
146 MachineRegisterInfo &RegInfo = MF.getRegInfo();
147 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
149 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
150 const TargetRegisterClass *RC;
151 const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
152 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
154 V0 = RegInfo.createVirtualRegister(RC);
155 V1 = RegInfo.createVirtualRegister(RC);
158 MF.getRegInfo().addLiveIn(Mips::T9_64);
159 MBB.addLiveIn(Mips::T9_64);
161 // lui $v0, %hi(%neg(%gp_rel(fname)))
162 // daddu $v1, $v0, $t9
163 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
164 const GlobalValue *FName = MF.getFunction();
165 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
166 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
167 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
168 .addReg(Mips::T9_64);
169 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
170 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
174 if (!MF.getTarget().isPositionIndependent()) {
175 // Set global register to __gnu_local_gp.
177 // lui $v0, %hi(__gnu_local_gp)
178 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
179 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
180 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
181 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
182 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
186 MF.getRegInfo().addLiveIn(Mips::T9);
187 MBB.addLiveIn(Mips::T9);
190 // lui $v0, %hi(%neg(%gp_rel(fname)))
191 // addu $v1, $v0, $t9
192 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
193 const GlobalValue *FName = MF.getFunction();
194 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
195 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
196 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
197 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
198 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
204 // For O32 ABI, the following instruction sequence is emitted to initialize
205 // the global base register:
207 // 0. lui $2, %hi(_gp_disp)
208 // 1. addiu $2, $2, %lo(_gp_disp)
209 // 2. addu $globalbasereg, $2, $t9
211 // We emit only the last instruction here.
213 // GNU linker requires that the first two instructions appear at the beginning
214 // of a function and no instructions be inserted before or between them.
215 // The two instructions are emitted during lowering to MC layer in order to
216 // avoid any reordering.
218 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
219 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
221 MF.getRegInfo().addLiveIn(Mips::V0);
222 MBB.addLiveIn(Mips::V0);
223 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
224 .addReg(Mips::V0).addReg(Mips::T9);
227 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
228 initGlobalBaseReg(MF);
230 MachineRegisterInfo *MRI = &MF.getRegInfo();
232 for (auto &MBB: MF) {
233 for (auto &MI: MBB) {
234 switch (MI.getOpcode()) {
236 addDSPCtrlRegOperands(false, MI, MF);
239 addDSPCtrlRegOperands(true, MI, MF);
242 replaceUsesWithZeroReg(MRI, MI);
248 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
249 SDValue InFlag = Node->getOperand(2);
250 unsigned Opc = InFlag.getOpcode();
251 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
252 EVT VT = LHS.getValueType();
254 // In the base case, we can rely on the carry bit from the addsc
256 if (Opc == ISD::ADDC) {
257 SDValue Ops[3] = {LHS, RHS, InFlag};
258 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
262 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
264 // The more complex case is when there is a chain of ISD::ADDE nodes like:
265 // (adde (adde (adde (addc a b) c) d) e).
267 // The addwc instruction does not write to the carry bit, instead it writes
268 // to bit 20 of the dsp control register. To match this series of nodes, each
269 // intermediate adde node must be expanded to write the carry bit before the
272 // Start by reading the overflow field for addsc and moving the value to the
273 // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
274 // corresponds to reading/writing the entire control register to/from a GPR.
276 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
278 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
280 SDNode *DSPCtrlField =
281 CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
283 SDNode *Carry = CurDAG->getMachineNode(
284 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
286 SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
287 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
289 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
291 // My reading of the the MIPS DSP 3.01 specification isn't as clear as I
292 // would like about whether bit 20 always gets overwritten by addwc.
293 // Hence take an extremely conservative view and presume it's sticky. We
294 // therefore need to clear it.
296 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
298 SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
299 SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
301 SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
302 SDValue(DSPCtrlFinal, 0), CstOne);
304 SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
305 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
309 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
310 SDValue &Offset) const {
311 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
312 EVT ValTy = Addr.getValueType();
314 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
315 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
321 /// Match frameindex+offset and frameindex|offset
322 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
323 SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
324 unsigned ShiftAmount = 0) const {
325 if (CurDAG->isBaseWithConstantOffset(Addr)) {
326 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
327 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
328 EVT ValTy = Addr.getValueType();
330 // If the first operand is a FI, get the TargetFI Node
331 if (FrameIndexSDNode *FIN =
332 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
333 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
335 Base = Addr.getOperand(0);
336 // If base is a FI, additional offset calculation is done in
337 // eliminateFrameIndex, otherwise we need to check the alignment
338 if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0)
342 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
350 /// ComplexPattern used on MipsInstrInfo
351 /// Used on Mips Load/Store instructions
352 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
353 SDValue &Offset) const {
354 // if Address is FI, get the TargetFrameIndex.
355 if (selectAddrFrameIndex(Addr, Base, Offset))
358 // on PIC code Load GA
359 if (Addr.getOpcode() == MipsISD::Wrapper) {
360 Base = Addr.getOperand(0);
361 Offset = Addr.getOperand(1);
365 if (!TM.isPositionIndependent()) {
366 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
367 Addr.getOpcode() == ISD::TargetGlobalAddress))
371 // Addresses of the form FI+const or FI|const
372 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
375 // Operand is a result from an ADD.
376 if (Addr.getOpcode() == ISD::ADD) {
377 // When loading from constant pools, load the lower address part in
378 // the instruction itself. Example, instead of:
379 // lui $2, %hi($CPI1_0)
380 // addiu $2, $2, %lo($CPI1_0)
383 // lui $2, %hi($CPI1_0)
384 // lwc1 $f0, %lo($CPI1_0)($2)
385 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
386 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
387 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
388 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
389 isa<JumpTableSDNode>(Opnd0)) {
390 Base = Addr.getOperand(0);
400 /// ComplexPattern used on MipsInstrInfo
401 /// Used on Mips Load/Store instructions
402 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
403 SDValue &Offset) const {
405 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
409 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
410 SDValue &Offset) const {
411 return selectAddrRegImm(Addr, Base, Offset) ||
412 selectAddrDefault(Addr, Base, Offset);
415 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
416 SDValue &Offset) const {
417 if (selectAddrFrameIndex(Addr, Base, Offset))
420 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
426 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
427 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
428 SDValue &Offset) const {
429 if (selectAddrFrameIndex(Addr, Base, Offset))
432 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
438 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
439 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
440 SDValue &Offset) const {
441 if (selectAddrFrameIndex(Addr, Base, Offset))
444 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
450 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
451 SDValue &Offset) const {
452 if (selectAddrFrameIndex(Addr, Base, Offset))
455 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
461 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
462 SDValue &Offset) const {
463 return selectAddrRegImm11(Addr, Base, Offset) ||
464 selectAddrDefault(Addr, Base, Offset);
467 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
468 SDValue &Offset) const {
469 return selectAddrRegImm12(Addr, Base, Offset) ||
470 selectAddrDefault(Addr, Base, Offset);
473 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
474 SDValue &Offset) const {
475 return selectAddrRegImm16(Addr, Base, Offset) ||
476 selectAddrDefault(Addr, Base, Offset);
479 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
480 SDValue &Offset) const {
481 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
482 if (isa<FrameIndexSDNode>(Base))
485 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
486 unsigned CnstOff = CN->getZExtValue();
487 return (CnstOff == (CnstOff & 0x3c));
493 // For all other cases where "lw" would be selected, don't select "lw16"
494 // because it would result in additional instructions to prepare operands.
495 if (selectAddrRegImm(Addr, Base, Offset))
498 return selectAddrDefault(Addr, Base, Offset);
501 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
502 SDValue &Offset) const {
504 if (selectAddrFrameIndex(Addr, Base, Offset))
507 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
510 return selectAddrDefault(Addr, Base, Offset);
513 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
514 SDValue &Offset) const {
515 if (selectAddrFrameIndex(Addr, Base, Offset))
518 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
521 return selectAddrDefault(Addr, Base, Offset);
524 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
525 SDValue &Offset) const {
526 if (selectAddrFrameIndex(Addr, Base, Offset))
529 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
532 return selectAddrDefault(Addr, Base, Offset);
535 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
536 SDValue &Offset) const {
537 if (selectAddrFrameIndex(Addr, Base, Offset))
540 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
543 return selectAddrDefault(Addr, Base, Offset);
546 // Select constant vector splats.
548 // Returns true and sets Imm if:
550 // * N is a ISD::BUILD_VECTOR representing a constant splat
551 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
552 unsigned MinSizeInBits) const {
553 if (!Subtarget->hasMSA())
556 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
561 APInt SplatValue, SplatUndef;
562 unsigned SplatBitSize;
565 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
566 MinSizeInBits, !Subtarget->isLittle()))
574 // Select constant vector splats.
576 // In addition to the requirements of selectVSplat(), this function returns
577 // true and sets Imm if:
578 // * The splat value is the same width as the elements of the vector
579 // * The splat value fits in an integer with the specified signed-ness and
582 // This function looks through ISD::BITCAST nodes.
583 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
584 // sometimes a shuffle in big-endian mode.
586 // It's worth noting that this function is not used as part of the selection
587 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
588 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
589 // MipsSEDAGToDAGISel::selectNode.
590 bool MipsSEDAGToDAGISel::
591 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
592 unsigned ImmBitSize) const {
594 EVT EltTy = N->getValueType(0).getVectorElementType();
596 if (N->getOpcode() == ISD::BITCAST)
597 N = N->getOperand(0);
599 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
600 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
602 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
603 (!Signed && ImmValue.isIntN(ImmBitSize))) {
604 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
612 // Select constant vector splats.
613 bool MipsSEDAGToDAGISel::
614 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
615 return selectVSplatCommon(N, Imm, false, 1);
618 bool MipsSEDAGToDAGISel::
619 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
620 return selectVSplatCommon(N, Imm, false, 2);
623 bool MipsSEDAGToDAGISel::
624 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
625 return selectVSplatCommon(N, Imm, false, 3);
628 // Select constant vector splats.
629 bool MipsSEDAGToDAGISel::
630 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
631 return selectVSplatCommon(N, Imm, false, 4);
634 // Select constant vector splats.
635 bool MipsSEDAGToDAGISel::
636 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
637 return selectVSplatCommon(N, Imm, false, 5);
640 // Select constant vector splats.
641 bool MipsSEDAGToDAGISel::
642 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
643 return selectVSplatCommon(N, Imm, false, 6);
646 // Select constant vector splats.
647 bool MipsSEDAGToDAGISel::
648 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
649 return selectVSplatCommon(N, Imm, false, 8);
652 // Select constant vector splats.
653 bool MipsSEDAGToDAGISel::
654 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
655 return selectVSplatCommon(N, Imm, true, 5);
658 // Select constant vector splats whose value is a power of 2.
660 // In addition to the requirements of selectVSplat(), this function returns
661 // true and sets Imm if:
662 // * The splat value is the same width as the elements of the vector
663 // * The splat value is a power of two.
665 // This function looks through ISD::BITCAST nodes.
666 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
667 // sometimes a shuffle in big-endian mode.
668 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
670 EVT EltTy = N->getValueType(0).getVectorElementType();
672 if (N->getOpcode() == ISD::BITCAST)
673 N = N->getOperand(0);
675 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
676 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
677 int32_t Log2 = ImmValue.exactLogBase2();
680 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
688 // Select constant vector splats whose value only has a consecutive sequence
689 // of left-most bits set (e.g. 0b11...1100...00).
691 // In addition to the requirements of selectVSplat(), this function returns
692 // true and sets Imm if:
693 // * The splat value is the same width as the elements of the vector
694 // * The splat value is a consecutive sequence of left-most bits.
696 // This function looks through ISD::BITCAST nodes.
697 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
698 // sometimes a shuffle in big-endian mode.
699 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
701 EVT EltTy = N->getValueType(0).getVectorElementType();
703 if (N->getOpcode() == ISD::BITCAST)
704 N = N->getOperand(0);
706 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
707 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
708 // Extract the run of set bits starting with bit zero from the bitwise
709 // inverse of ImmValue, and test that the inverse of this is the same
710 // as the original value.
711 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
713 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
722 // Select constant vector splats whose value only has a consecutive sequence
723 // of right-most bits set (e.g. 0b00...0011...11).
725 // In addition to the requirements of selectVSplat(), this function returns
726 // true and sets Imm if:
727 // * The splat value is the same width as the elements of the vector
728 // * The splat value is a consecutive sequence of right-most bits.
730 // This function looks through ISD::BITCAST nodes.
731 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
732 // sometimes a shuffle in big-endian mode.
733 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
735 EVT EltTy = N->getValueType(0).getVectorElementType();
737 if (N->getOpcode() == ISD::BITCAST)
738 N = N->getOperand(0);
740 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
741 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
742 // Extract the run of set bits starting with bit zero, and test that the
743 // result is the same as the original value
744 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
745 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
754 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
755 SDValue &Imm) const {
757 EVT EltTy = N->getValueType(0).getVectorElementType();
759 if (N->getOpcode() == ISD::BITCAST)
760 N = N->getOperand(0);
762 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
763 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
764 int32_t Log2 = (~ImmValue).exactLogBase2();
767 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
775 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
776 unsigned Opcode = Node->getOpcode();
780 // Instruction Selection not handled by the auto-generated
781 // tablegen selection should be handled here.
787 selectAddE(Node, DL);
791 case ISD::ConstantFP: {
792 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
793 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
794 if (Subtarget->isGP64bit()) {
795 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
796 Mips::ZERO_64, MVT::i64);
798 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
799 } else if (Subtarget->isFP64bit()) {
800 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
801 Mips::ZERO, MVT::i32);
802 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
803 MVT::f64, Zero, Zero));
805 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
806 Mips::ZERO, MVT::i32);
807 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
808 MVT::f64, Zero, Zero));
815 case ISD::Constant: {
816 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
817 int64_t Imm = CN->getSExtValue();
818 unsigned Size = CN->getValueSizeInBits(0);
823 MipsAnalyzeImmediate AnalyzeImm;
825 const MipsAnalyzeImmediate::InstSeq &Seq =
826 AnalyzeImm.Analyze(Imm, Size, false);
828 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
831 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
834 // The first instruction can be a LUi which is different from other
835 // instructions (ADDiu, ORI and SLL) in that it does not have a register
837 if (Inst->Opc == Mips::LUi64)
838 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
841 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
842 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
845 // The remaining instructions in the sequence are handled here.
846 for (++Inst; Inst != Seq.end(); ++Inst) {
847 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
849 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
850 SDValue(RegOpnd, 0), ImmOpnd);
853 ReplaceNode(Node, RegOpnd);
857 case ISD::INTRINSIC_W_CHAIN: {
858 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
862 case Intrinsic::mips_cfcmsa: {
863 SDValue ChainIn = Node->getOperand(0);
864 SDValue RegIdx = Node->getOperand(2);
865 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
866 getMSACtrlReg(RegIdx), MVT::i32);
867 ReplaceNode(Node, Reg.getNode());
874 case ISD::INTRINSIC_WO_CHAIN: {
875 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
879 case Intrinsic::mips_move_v:
880 // Like an assignment but will always produce a move.v even if
882 ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
883 Node->getValueType(0),
884 Node->getOperand(1)));
890 case ISD::INTRINSIC_VOID: {
891 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
895 case Intrinsic::mips_ctcmsa: {
896 SDValue ChainIn = Node->getOperand(0);
897 SDValue RegIdx = Node->getOperand(2);
898 SDValue Value = Node->getOperand(3);
899 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
900 getMSACtrlReg(RegIdx), Value);
901 ReplaceNode(Node, ChainOut.getNode());
908 case MipsISD::ThreadPointer: {
909 EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
910 unsigned RdhwrOpc, DestReg;
912 if (PtrVT == MVT::i32) {
913 RdhwrOpc = Mips::RDHWR;
916 RdhwrOpc = Mips::RDHWR64;
917 DestReg = Mips::V1_64;
921 CurDAG->getMachineNode(RdhwrOpc, DL,
922 Node->getValueType(0),
923 CurDAG->getRegister(Mips::HWR29, MVT::i32));
924 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
926 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
927 ReplaceNode(Node, ResNode.getNode());
931 case ISD::BUILD_VECTOR: {
932 // Select appropriate ldi.[bhwd] instructions for constant splats of
933 // 128-bit when MSA is enabled. Fixup any register class mismatches that
934 // occur as a result.
936 // This allows the compiler to use a wider range of immediates than would
937 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
938 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
939 // 0x01010101 } without using a constant pool. This would be sub-optimal
940 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
941 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
942 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
944 const MipsABIInfo &ABI =
945 static_cast<const MipsTargetMachine &>(TM).getABI();
947 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
948 APInt SplatValue, SplatUndef;
949 unsigned SplatBitSize;
952 EVT ResVecTy = BVN->getValueType(0);
955 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
958 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
960 !Subtarget->isLittle()))
963 switch (SplatBitSize) {
968 ViaVecTy = MVT::v16i8;
972 ViaVecTy = MVT::v8i16;
976 ViaVecTy = MVT::v4i32;
980 ViaVecTy = MVT::v2i64;
986 // If we have a signed 10 bit integer, we can splat it directly.
988 // If we have something bigger we can synthesize the value into a GPR and
990 if (SplatValue.isSignedIntN(10)) {
991 SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
992 ViaVecTy.getVectorElementType());
994 Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
995 } else if (SplatValue.isSignedIntN(16) &&
996 ((ABI.IsO32() && SplatBitSize < 64) ||
997 (ABI.IsN32() || ABI.IsN64()))) {
998 // Only handle signed 16 bit values when the element size is GPR width.
999 // MIPS64 can handle all the cases but MIPS32 would need to handle
1000 // negative cases specifically here. Instead, handle those cases as
1003 bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
1004 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1005 const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
1006 SDValue ZeroVal = CurDAG->getRegister(
1007 Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1009 const unsigned FILLOp =
1012 : (SplatBitSize == 32 ? Mips::FILL_W
1013 : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1015 assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1016 assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1017 "Attempting to use fill.d on MIPS32!");
1019 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1020 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1022 Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1023 Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1025 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
1026 // Only handle the cases where the splat size agrees with the size
1027 // of the SplatValue here.
1028 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1029 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1030 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1032 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1033 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1036 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1039 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1040 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1042 assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1043 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1045 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
1046 (ABI.IsN32() || ABI.IsN64())) {
1047 // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1048 // integers due to having 64bit registers. lui will cause the necessary
1049 // zero/sign extension.
1050 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1051 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1052 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1054 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1055 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1058 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1061 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1062 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1064 Res = CurDAG->getMachineNode(
1065 Mips::SUBREG_TO_REG, DL, MVT::i64,
1066 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1068 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1071 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1073 } else if (SplatValue.isSignedIntN(64)) {
1074 // If we have a 64 bit Splat value, we perform a similar sequence to the
1078 // lui $res, %highest(val) lui $res, %highest(val)
1079 // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1080 // lui $res2, %hi(val) lui $res2, %hi(val)
1081 // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1082 // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1083 // $res4 = insert.w $res3[1], $res fill.d $res
1086 // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1087 // having to materialize the value by shifts and ors.
1089 // FIXME: Implement the preferred sequence for MIPS64R6:
1092 // ori $res, $zero, %lo(val)
1093 // daui $res, $res, %hi(val)
1094 // dahi $res, $res, %higher(val)
1095 // dati $res, $res, %highest(cal)
1099 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1100 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1101 const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1102 const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1104 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1105 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1106 SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1107 SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1108 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1110 // Independent of whether we're targeting MIPS64 or not, the basic
1111 // operations are the same. Also, directly use the $zero register if
1112 // the 16 bit chunk is zero.
1114 // For optimization purposes we always synthesize the splat value as
1115 // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1116 // just before combining the values with dinsu to produce an i64. This
1117 // enables SelectionDAG to aggressively share components of splat values
1120 // FIXME: This is the general constant synthesis problem. This code
1121 // should be factored out into a class shared between all the
1122 // classes that need it. Specifically, for a splat size of 64
1123 // bits that's a negative number we can do better than LUi/ORi
1124 // for the upper 32bits.
1127 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1130 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1131 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1135 HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1138 HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1139 Highest ? SDValue(HiRes, 0) : ZeroVal,
1144 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1145 (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1147 Res = CurDAG->getMachineNode(
1148 Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1149 (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1150 CurDAG->getTargetConstant(1, DL, MVT::i32));
1152 const TargetLowering *TLI = getTargetLowering();
1153 const TargetRegisterClass *RC =
1154 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1156 Res = CurDAG->getMachineNode(
1157 Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1158 CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1160 Res = CurDAG->getMachineNode(
1161 Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1162 CurDAG->getTargetConstant(0, DL, MVT::i32));
1163 } else if (ABI.IsN64() || ABI.IsN32()) {
1165 SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1166 const bool HiResNonZero = Highest || Higher;
1167 const bool ResNonZero = Hi || Lo;
1170 HiRes = CurDAG->getMachineNode(
1171 Mips::SUBREG_TO_REG, DL, MVT::i64,
1172 CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1174 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1177 Res = CurDAG->getMachineNode(
1178 Mips::SUBREG_TO_REG, DL, MVT::i64,
1179 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1181 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1184 // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1185 // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1186 // Both are non zero => dinsu Res, HiRes, 32, 32
1188 // The obvious "missing" case is when both are zero, but that case is
1189 // handled by the ldi case.
1191 SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1192 CurDAG->getTargetConstant(64, DL, MVT::i32),
1193 CurDAG->getTargetConstant(32, DL, MVT::i32),
1196 Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1197 } else if (HiResNonZero) {
1198 Res = CurDAG->getMachineNode(
1199 Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1200 CurDAG->getTargetConstant(0, DL, MVT::i32));
1203 "Zero splat value handled by non-zero 64bit splat synthesis!");
1205 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1207 llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1212 if (ResVecTy != ViaVecTy) {
1213 // If LdiOp is writing to a different register class to ResVecTy, then
1214 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1215 // since the source and destination register sets contain the same
1217 const TargetLowering *TLI = getTargetLowering();
1218 MVT ResVecTySimple = ResVecTy.getSimpleVT();
1219 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1220 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1221 ResVecTy, SDValue(Res, 0),
1222 CurDAG->getTargetConstant(RC->getID(), DL,
1226 ReplaceNode(Node, Res);
1235 bool MipsSEDAGToDAGISel::
1236 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1237 std::vector<SDValue> &OutOps) {
1238 SDValue Base, Offset;
1240 switch(ConstraintID) {
1242 llvm_unreachable("Unexpected asm memory constraint");
1243 // All memory constraints can at least accept raw pointers.
1244 case InlineAsm::Constraint_i:
1245 OutOps.push_back(Op);
1246 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1248 case InlineAsm::Constraint_m:
1249 if (selectAddrRegImm16(Op, Base, Offset)) {
1250 OutOps.push_back(Base);
1251 OutOps.push_back(Offset);
1254 OutOps.push_back(Op);
1255 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1257 case InlineAsm::Constraint_R:
1258 // The 'R' constraint is supposed to be much more complicated than this.
1259 // However, it's becoming less useful due to architectural changes and
1260 // ought to be replaced by other constraints such as 'ZC'.
1261 // For now, support 9-bit signed offsets which is supportable by all
1262 // subtargets for all instructions.
1263 if (selectAddrRegImm9(Op, Base, Offset)) {
1264 OutOps.push_back(Base);
1265 OutOps.push_back(Offset);
1268 OutOps.push_back(Op);
1269 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1271 case InlineAsm::Constraint_ZC:
1272 // ZC matches whatever the pref, ll, and sc instructions can handle for the
1274 if (Subtarget->inMicroMipsMode()) {
1275 // On microMIPS, they can handle 12-bit offsets.
1276 if (selectAddrRegImm12(Op, Base, Offset)) {
1277 OutOps.push_back(Base);
1278 OutOps.push_back(Offset);
1281 } else if (Subtarget->hasMips32r6()) {
1282 // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1283 if (selectAddrRegImm9(Op, Base, Offset)) {
1284 OutOps.push_back(Base);
1285 OutOps.push_back(Offset);
1288 } else if (selectAddrRegImm16(Op, Base, Offset)) {
1289 // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1290 OutOps.push_back(Base);
1291 OutOps.push_back(Offset);
1294 // In all cases, 0-bit offsets are acceptable.
1295 OutOps.push_back(Op);
1296 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1302 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
1303 CodeGenOpt::Level OptLevel) {
1304 return new MipsSEDAGToDAGISel(TM, OptLevel);