1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsMachineFunction.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetInstrInfo.h"
29 #define DEBUG_TYPE "mips-isel"
32 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
33 cl::desc("MIPS: permit tail calls."), cl::init(false));
35 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
36 cl::desc("Expand double precision loads and "
37 "stores to their single precision "
40 MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
41 const MipsSubtarget &STI)
42 : MipsTargetLowering(TM, STI) {
43 // Set up the register classes
44 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
46 if (Subtarget.isGP64bit())
47 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
49 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
50 // Expand all truncating stores and extending loads.
51 for (MVT VT0 : MVT::vector_valuetypes()) {
52 for (MVT VT1 : MVT::vector_valuetypes()) {
53 setTruncStoreAction(VT0, VT1, Expand);
54 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
55 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
56 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
61 if (Subtarget.hasDSP()) {
62 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
64 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
65 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
67 // Expand all builtin opcodes.
68 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
69 setOperationAction(Opc, VecTys[i], Expand);
71 setOperationAction(ISD::ADD, VecTys[i], Legal);
72 setOperationAction(ISD::SUB, VecTys[i], Legal);
73 setOperationAction(ISD::LOAD, VecTys[i], Legal);
74 setOperationAction(ISD::STORE, VecTys[i], Legal);
75 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
78 setTargetDAGCombine(ISD::SHL);
79 setTargetDAGCombine(ISD::SRA);
80 setTargetDAGCombine(ISD::SRL);
81 setTargetDAGCombine(ISD::SETCC);
82 setTargetDAGCombine(ISD::VSELECT);
85 if (Subtarget.hasDSPR2())
86 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
88 if (Subtarget.hasMSA()) {
89 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
90 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
91 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
92 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
93 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
94 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
95 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
97 // f16 is a storage-only type, always promote it to f32.
98 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
99 setOperationAction(ISD::SETCC, MVT::f16, Promote);
100 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
101 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
102 setOperationAction(ISD::SELECT, MVT::f16, Promote);
103 setOperationAction(ISD::FADD, MVT::f16, Promote);
104 setOperationAction(ISD::FSUB, MVT::f16, Promote);
105 setOperationAction(ISD::FMUL, MVT::f16, Promote);
106 setOperationAction(ISD::FDIV, MVT::f16, Promote);
107 setOperationAction(ISD::FREM, MVT::f16, Promote);
108 setOperationAction(ISD::FMA, MVT::f16, Promote);
109 setOperationAction(ISD::FNEG, MVT::f16, Promote);
110 setOperationAction(ISD::FABS, MVT::f16, Promote);
111 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
112 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
113 setOperationAction(ISD::FCOS, MVT::f16, Promote);
114 setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote);
115 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
116 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
117 setOperationAction(ISD::FPOW, MVT::f16, Promote);
118 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
119 setOperationAction(ISD::FRINT, MVT::f16, Promote);
120 setOperationAction(ISD::FSIN, MVT::f16, Promote);
121 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
122 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
123 setOperationAction(ISD::FEXP, MVT::f16, Promote);
124 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
125 setOperationAction(ISD::FLOG, MVT::f16, Promote);
126 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
127 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
128 setOperationAction(ISD::FROUND, MVT::f16, Promote);
129 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
130 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
131 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
132 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
133 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
135 setTargetDAGCombine(ISD::AND);
136 setTargetDAGCombine(ISD::OR);
137 setTargetDAGCombine(ISD::SRA);
138 setTargetDAGCombine(ISD::VSELECT);
139 setTargetDAGCombine(ISD::XOR);
142 if (!Subtarget.useSoftFloat()) {
143 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
145 // When dealing with single precision only, use libcalls
146 if (!Subtarget.isSingleFloat()) {
147 if (Subtarget.isFP64bit())
148 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
150 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
156 setOperationAction(ISD::MULHS, MVT::i32, Custom);
157 setOperationAction(ISD::MULHU, MVT::i32, Custom);
159 if (Subtarget.hasCnMips())
160 setOperationAction(ISD::MUL, MVT::i64, Legal);
161 else if (Subtarget.isGP64bit())
162 setOperationAction(ISD::MUL, MVT::i64, Custom);
164 if (Subtarget.isGP64bit()) {
165 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
166 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
167 setOperationAction(ISD::MULHS, MVT::i64, Custom);
168 setOperationAction(ISD::MULHU, MVT::i64, Custom);
169 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
170 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
174 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
176 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
177 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
178 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
179 setOperationAction(ISD::LOAD, MVT::i32, Custom);
180 setOperationAction(ISD::STORE, MVT::i32, Custom);
182 setTargetDAGCombine(ISD::ADDE);
183 setTargetDAGCombine(ISD::SUBE);
184 setTargetDAGCombine(ISD::MUL);
186 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
187 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
188 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
191 setOperationAction(ISD::LOAD, MVT::f64, Custom);
192 setOperationAction(ISD::STORE, MVT::f64, Custom);
195 if (Subtarget.hasMips32r6()) {
196 // MIPS32r6 replaces the accumulator-based multiplies with a three register
198 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
199 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
200 setOperationAction(ISD::MUL, MVT::i32, Legal);
201 setOperationAction(ISD::MULHS, MVT::i32, Legal);
202 setOperationAction(ISD::MULHU, MVT::i32, Legal);
204 // MIPS32r6 replaces the accumulator-based division/remainder with separate
205 // three register division and remainder instructions.
206 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
207 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
208 setOperationAction(ISD::SDIV, MVT::i32, Legal);
209 setOperationAction(ISD::UDIV, MVT::i32, Legal);
210 setOperationAction(ISD::SREM, MVT::i32, Legal);
211 setOperationAction(ISD::UREM, MVT::i32, Legal);
213 // MIPS32r6 replaces conditional moves with an equivalent that removes the
214 // need for three GPR read ports.
215 setOperationAction(ISD::SETCC, MVT::i32, Legal);
216 setOperationAction(ISD::SELECT, MVT::i32, Legal);
217 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
219 setOperationAction(ISD::SETCC, MVT::f32, Legal);
220 setOperationAction(ISD::SELECT, MVT::f32, Legal);
221 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
223 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
224 setOperationAction(ISD::SETCC, MVT::f64, Legal);
225 setOperationAction(ISD::SELECT, MVT::f64, Legal);
226 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
228 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
230 // Floating point > and >= are supported via < and <=
231 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
233 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
234 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
242 if (Subtarget.hasMips64r6()) {
243 // MIPS64r6 replaces the accumulator-based multiplies with a three register
245 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
246 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
247 setOperationAction(ISD::MUL, MVT::i64, Legal);
248 setOperationAction(ISD::MULHS, MVT::i64, Legal);
249 setOperationAction(ISD::MULHU, MVT::i64, Legal);
251 // MIPS32r6 replaces the accumulator-based division/remainder with separate
252 // three register division and remainder instructions.
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::SDIV, MVT::i64, Legal);
256 setOperationAction(ISD::UDIV, MVT::i64, Legal);
257 setOperationAction(ISD::SREM, MVT::i64, Legal);
258 setOperationAction(ISD::UREM, MVT::i64, Legal);
260 // MIPS64r6 replaces conditional moves with an equivalent that removes the
261 // need for three GPR read ports.
262 setOperationAction(ISD::SETCC, MVT::i64, Legal);
263 setOperationAction(ISD::SELECT, MVT::i64, Legal);
264 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
267 computeRegisterProperties(Subtarget.getRegisterInfo());
270 const MipsTargetLowering *
271 llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
272 const MipsSubtarget &STI) {
273 return new MipsSETargetLowering(TM, STI);
276 const TargetRegisterClass *
277 MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
278 if (VT == MVT::Untyped)
279 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
281 return TargetLowering::getRepRegClassFor(VT);
284 // Enable MSA support for the given integer type and Register class.
285 void MipsSETargetLowering::
286 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
287 addRegisterClass(Ty, RC);
289 // Expand all builtin opcodes.
290 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
291 setOperationAction(Opc, Ty, Expand);
293 setOperationAction(ISD::BITCAST, Ty, Legal);
294 setOperationAction(ISD::LOAD, Ty, Legal);
295 setOperationAction(ISD::STORE, Ty, Legal);
296 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
297 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
298 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
300 setOperationAction(ISD::ADD, Ty, Legal);
301 setOperationAction(ISD::AND, Ty, Legal);
302 setOperationAction(ISD::CTLZ, Ty, Legal);
303 setOperationAction(ISD::CTPOP, Ty, Legal);
304 setOperationAction(ISD::MUL, Ty, Legal);
305 setOperationAction(ISD::OR, Ty, Legal);
306 setOperationAction(ISD::SDIV, Ty, Legal);
307 setOperationAction(ISD::SREM, Ty, Legal);
308 setOperationAction(ISD::SHL, Ty, Legal);
309 setOperationAction(ISD::SRA, Ty, Legal);
310 setOperationAction(ISD::SRL, Ty, Legal);
311 setOperationAction(ISD::SUB, Ty, Legal);
312 setOperationAction(ISD::UDIV, Ty, Legal);
313 setOperationAction(ISD::UREM, Ty, Legal);
314 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
315 setOperationAction(ISD::VSELECT, Ty, Legal);
316 setOperationAction(ISD::XOR, Ty, Legal);
318 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
319 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
320 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
321 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
322 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
325 setOperationAction(ISD::SETCC, Ty, Legal);
326 setCondCodeAction(ISD::SETNE, Ty, Expand);
327 setCondCodeAction(ISD::SETGE, Ty, Expand);
328 setCondCodeAction(ISD::SETGT, Ty, Expand);
329 setCondCodeAction(ISD::SETUGE, Ty, Expand);
330 setCondCodeAction(ISD::SETUGT, Ty, Expand);
333 // Enable MSA support for the given floating-point type and Register class.
334 void MipsSETargetLowering::
335 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
336 addRegisterClass(Ty, RC);
338 // Expand all builtin opcodes.
339 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
340 setOperationAction(Opc, Ty, Expand);
342 setOperationAction(ISD::LOAD, Ty, Legal);
343 setOperationAction(ISD::STORE, Ty, Legal);
344 setOperationAction(ISD::BITCAST, Ty, Legal);
345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
346 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
347 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
349 if (Ty != MVT::v8f16) {
350 setOperationAction(ISD::FABS, Ty, Legal);
351 setOperationAction(ISD::FADD, Ty, Legal);
352 setOperationAction(ISD::FDIV, Ty, Legal);
353 setOperationAction(ISD::FEXP2, Ty, Legal);
354 setOperationAction(ISD::FLOG2, Ty, Legal);
355 setOperationAction(ISD::FMA, Ty, Legal);
356 setOperationAction(ISD::FMUL, Ty, Legal);
357 setOperationAction(ISD::FRINT, Ty, Legal);
358 setOperationAction(ISD::FSQRT, Ty, Legal);
359 setOperationAction(ISD::FSUB, Ty, Legal);
360 setOperationAction(ISD::VSELECT, Ty, Legal);
362 setOperationAction(ISD::SETCC, Ty, Legal);
363 setCondCodeAction(ISD::SETOGE, Ty, Expand);
364 setCondCodeAction(ISD::SETOGT, Ty, Expand);
365 setCondCodeAction(ISD::SETUGE, Ty, Expand);
366 setCondCodeAction(ISD::SETUGT, Ty, Expand);
367 setCondCodeAction(ISD::SETGE, Ty, Expand);
368 setCondCodeAction(ISD::SETGT, Ty, Expand);
373 MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
377 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
379 if (Subtarget.systemSupportsUnalignedAccess()) {
380 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
381 // implementation defined whether this is handled by hardware, software, or
382 // a hybrid of the two but it's expected that most implementations will
383 // handle the majority of cases in hardware.
400 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
401 SelectionDAG &DAG) const {
402 switch(Op.getOpcode()) {
403 case ISD::LOAD: return lowerLOAD(Op, DAG);
404 case ISD::STORE: return lowerSTORE(Op, DAG);
405 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
406 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
407 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
408 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
409 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
410 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
411 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
413 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
414 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
415 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
416 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
417 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
418 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
421 return MipsTargetLowering::LowerOperation(Op, DAG);
425 // Transforms a subgraph in CurDAG if the following pattern is found:
426 // (addc multLo, Lo0), (adde multHi, Hi0),
428 // multHi/Lo: product of multiplication
429 // Lo0: initial value of Lo register
430 // Hi0: initial value of Hi register
431 // Return true if pattern matching was successful.
432 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
433 // ADDENode's second operand must be a flag output of an ADDC node in order
434 // for the matching to be successful.
435 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
437 if (ADDCNode->getOpcode() != ISD::ADDC)
440 SDValue MultHi = ADDENode->getOperand(0);
441 SDValue MultLo = ADDCNode->getOperand(0);
442 SDNode *MultNode = MultHi.getNode();
443 unsigned MultOpc = MultHi.getOpcode();
445 // MultHi and MultLo must be generated by the same node,
446 if (MultLo.getNode() != MultNode)
449 // and it must be a multiplication.
450 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
453 // MultLo amd MultHi must be the first and second output of MultNode
455 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
458 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
459 // of the values of MultNode, in which case MultNode will be removed in later
461 // If there exist users other than ADDENode or ADDCNode, this function returns
462 // here, which will result in MultNode being mapped to a single MULT
463 // instruction node rather than a pair of MULT and MADD instructions being
465 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
470 // Initialize accumulator.
471 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
472 ADDCNode->getOperand(1),
473 ADDENode->getOperand(1));
475 // create MipsMAdd(u) node
476 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
478 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
479 MultNode->getOperand(0),// Factor 0
480 MultNode->getOperand(1),// Factor 1
483 // replace uses of adde and addc here
484 if (!SDValue(ADDCNode, 0).use_empty()) {
485 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
486 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
488 if (!SDValue(ADDENode, 0).use_empty()) {
489 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
490 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
497 // Transforms a subgraph in CurDAG if the following pattern is found:
498 // (addc Lo0, multLo), (sube Hi0, multHi),
500 // multHi/Lo: product of multiplication
501 // Lo0: initial value of Lo register
502 // Hi0: initial value of Hi register
503 // Return true if pattern matching was successful.
504 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
505 // SUBENode's second operand must be a flag output of an SUBC node in order
506 // for the matching to be successful.
507 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
509 if (SUBCNode->getOpcode() != ISD::SUBC)
512 SDValue MultHi = SUBENode->getOperand(1);
513 SDValue MultLo = SUBCNode->getOperand(1);
514 SDNode *MultNode = MultHi.getNode();
515 unsigned MultOpc = MultHi.getOpcode();
517 // MultHi and MultLo must be generated by the same node,
518 if (MultLo.getNode() != MultNode)
521 // and it must be a multiplication.
522 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
525 // MultLo amd MultHi must be the first and second output of MultNode
527 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
530 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
531 // of the values of MultNode, in which case MultNode will be removed in later
533 // If there exist users other than SUBENode or SUBCNode, this function returns
534 // here, which will result in MultNode being mapped to a single MULT
535 // instruction node rather than a pair of MULT and MSUB instructions being
537 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
542 // Initialize accumulator.
543 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
544 SUBCNode->getOperand(0),
545 SUBENode->getOperand(0));
547 // create MipsSub(u) node
548 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
550 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
551 MultNode->getOperand(0),// Factor 0
552 MultNode->getOperand(1),// Factor 1
555 // replace uses of sube and subc here
556 if (!SDValue(SUBCNode, 0).use_empty()) {
557 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
558 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
560 if (!SDValue(SUBENode, 0).use_empty()) {
561 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
562 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
568 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
569 TargetLowering::DAGCombinerInfo &DCI,
570 const MipsSubtarget &Subtarget) {
571 if (DCI.isBeforeLegalize())
574 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
575 N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
576 return SDValue(N, 0);
581 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
583 // Performs the following transformations:
584 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
585 // sign/zero-extension is completely overwritten by the new one performed by
587 // - Removes redundant zero extensions performed by an ISD::AND.
588 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
589 TargetLowering::DAGCombinerInfo &DCI,
590 const MipsSubtarget &Subtarget) {
591 if (!Subtarget.hasMSA())
594 SDValue Op0 = N->getOperand(0);
595 SDValue Op1 = N->getOperand(1);
596 unsigned Op0Opcode = Op0->getOpcode();
598 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
599 // where $d + 1 == 2^n and n == 32
600 // or $d + 1 == 2^n and n <= 32 and ZExt
601 // -> (MipsVExtractZExt $a, $b, $c)
602 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
603 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
604 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
609 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
611 if (Log2IfPositive <= 0)
612 return SDValue(); // Mask+1 is not a power of 2
614 SDValue Op0Op2 = Op0->getOperand(2);
615 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
616 unsigned ExtendTySize = ExtendTy.getSizeInBits();
617 unsigned Log2 = Log2IfPositive;
619 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
620 Log2 == ExtendTySize) {
621 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
622 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
624 makeArrayRef(Ops, Op0->getNumOperands()));
631 // Determine if the specified node is a constant vector splat.
633 // Returns true and sets Imm if:
634 // * N is a ISD::BUILD_VECTOR representing a constant splat
636 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
637 // differences are that it assumes the MSA has already been checked and the
638 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
639 // must not be in order for binsri.d to be selectable).
640 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
641 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
646 APInt SplatValue, SplatUndef;
647 unsigned SplatBitSize;
650 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
659 // Test whether the given node is an all-ones build_vector.
660 static bool isVectorAllOnes(SDValue N) {
661 // Look through bitcasts. Endianness doesn't matter because we are looking
662 // for an all-ones value.
663 if (N->getOpcode() == ISD::BITCAST)
664 N = N->getOperand(0);
666 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
671 APInt SplatValue, SplatUndef;
672 unsigned SplatBitSize;
675 // Endianness doesn't matter in this context because we are looking for
676 // an all-ones value.
677 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
678 return SplatValue.isAllOnesValue();
683 // Test whether N is the bitwise inverse of OfNode.
684 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
685 if (N->getOpcode() != ISD::XOR)
688 if (isVectorAllOnes(N->getOperand(0)))
689 return N->getOperand(1) == OfNode;
691 if (isVectorAllOnes(N->getOperand(1)))
692 return N->getOperand(0) == OfNode;
697 // Perform combines where ISD::OR is the root node.
699 // Performs the following transformations:
700 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
701 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
703 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
704 TargetLowering::DAGCombinerInfo &DCI,
705 const MipsSubtarget &Subtarget) {
706 if (!Subtarget.hasMSA())
709 EVT Ty = N->getValueType(0);
711 if (!Ty.is128BitVector())
714 SDValue Op0 = N->getOperand(0);
715 SDValue Op1 = N->getOperand(1);
717 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
718 SDValue Op0Op0 = Op0->getOperand(0);
719 SDValue Op0Op1 = Op0->getOperand(1);
720 SDValue Op1Op0 = Op1->getOperand(0);
721 SDValue Op1Op1 = Op1->getOperand(1);
722 bool IsLittleEndian = !Subtarget.isLittle();
724 SDValue IfSet, IfClr, Cond;
725 bool IsConstantMask = false;
728 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
729 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
731 // IfClr will be set if we find a valid match.
732 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
736 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
737 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
739 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
740 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
743 IsConstantMask = true;
746 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
747 // thing again using this mask.
748 // IfClr will be set if we find a valid match.
749 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
753 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
754 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
756 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
757 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
760 IsConstantMask = true;
763 // If IfClr is not yet set, try looking for a non-constant match.
764 // IfClr will be set if we find a valid match amongst the eight
766 if (!IfClr.getNode()) {
767 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
771 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
775 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
779 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
783 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
787 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
791 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
795 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
802 // At this point, IfClr will be set if we have a valid match.
803 if (!IfClr.getNode())
806 assert(Cond.getNode() && IfSet.getNode());
808 // Fold degenerate cases.
809 if (IsConstantMask) {
810 if (Mask.isAllOnesValue())
816 // Transform the DAG into an equivalent VSELECT.
817 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
823 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
824 TargetLowering::DAGCombinerInfo &DCI,
825 const MipsSubtarget &Subtarget) {
826 if (DCI.isBeforeLegalize())
829 if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 &&
831 return SDValue(N, 0);
836 static SDValue genConstMult(SDValue X, uint64_t C, const SDLoc &DL, EVT VT,
837 EVT ShiftTy, SelectionDAG &DAG) {
838 // Clear the upper (64 - VT.sizeInBits) bits.
839 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
843 return DAG.getConstant(0, DL, VT);
849 // If c is power of 2, return (shl x, log2(c)).
850 if (isPowerOf2_64(C))
851 return DAG.getNode(ISD::SHL, DL, VT, X,
852 DAG.getConstant(Log2_64(C), DL, ShiftTy));
854 unsigned Log2Ceil = Log2_64_Ceil(C);
855 uint64_t Floor = 1LL << Log2_64(C);
856 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
858 // If |c - floor_c| <= |c - ceil_c|,
859 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
860 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
861 if (C - Floor <= Ceil - C) {
862 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
863 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
864 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
867 // If |c - floor_c| > |c - ceil_c|,
868 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
869 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
870 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
871 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
874 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
875 const TargetLowering::DAGCombinerInfo &DCI,
876 const MipsSETargetLowering *TL) {
877 EVT VT = N->getValueType(0);
879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
881 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), VT,
882 TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
885 return SDValue(N, 0);
888 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
890 const MipsSubtarget &Subtarget) {
891 // See if this is a vector splat immediate node.
892 APInt SplatValue, SplatUndef;
893 unsigned SplatBitSize;
895 unsigned EltSize = Ty.getScalarSizeInBits();
896 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
898 if (!Subtarget.hasDSP())
902 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
903 EltSize, !Subtarget.isLittle()) ||
904 (SplatBitSize != EltSize) ||
905 (SplatValue.getZExtValue() >= EltSize))
909 return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
910 DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
913 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
914 TargetLowering::DAGCombinerInfo &DCI,
915 const MipsSubtarget &Subtarget) {
916 EVT Ty = N->getValueType(0);
918 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
921 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
924 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
925 // constant splats into MipsISD::SHRA_DSP for DSPr2.
927 // Performs the following transformations:
928 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
929 // sign/zero-extension is completely overwritten by the new one performed by
930 // the ISD::SRA and ISD::SHL nodes.
931 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
934 // See performDSPShiftCombine for more information about the transformation
936 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
937 TargetLowering::DAGCombinerInfo &DCI,
938 const MipsSubtarget &Subtarget) {
939 EVT Ty = N->getValueType(0);
941 if (Subtarget.hasMSA()) {
942 SDValue Op0 = N->getOperand(0);
943 SDValue Op1 = N->getOperand(1);
945 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
946 // where $d + sizeof($c) == 32
947 // or $d + sizeof($c) <= 32 and SExt
948 // -> (MipsVExtractSExt $a, $b, $c)
949 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
950 SDValue Op0Op0 = Op0->getOperand(0);
951 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
956 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
957 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
960 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
961 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
963 if (TotalBits == 32 ||
964 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
966 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
967 Op0Op0->getOperand(2) };
968 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
970 makeArrayRef(Ops, Op0Op0->getNumOperands()));
975 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
978 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
982 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
983 TargetLowering::DAGCombinerInfo &DCI,
984 const MipsSubtarget &Subtarget) {
985 EVT Ty = N->getValueType(0);
987 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
990 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
993 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
994 bool IsV216 = (Ty == MVT::v2i16);
998 case ISD::SETNE: return true;
1002 case ISD::SETGE: return IsV216;
1006 case ISD::SETUGE: return !IsV216;
1007 default: return false;
1011 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
1012 EVT Ty = N->getValueType(0);
1014 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
1017 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
1020 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
1021 N->getOperand(1), N->getOperand(2));
1024 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
1025 EVT Ty = N->getValueType(0);
1027 if (Ty.is128BitVector() && Ty.isInteger()) {
1028 // Try the following combines:
1029 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
1030 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
1031 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
1032 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
1033 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
1034 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
1035 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
1036 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
1037 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
1038 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
1040 SDValue Op0 = N->getOperand(0);
1042 if (Op0->getOpcode() != ISD::SETCC)
1045 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
1048 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
1050 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1055 SDValue Op1 = N->getOperand(1);
1056 SDValue Op2 = N->getOperand(2);
1057 SDValue Op0Op0 = Op0->getOperand(0);
1058 SDValue Op0Op1 = Op0->getOperand(1);
1060 if (Op1 == Op0Op0 && Op2 == Op0Op1)
1061 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
1063 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1064 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
1066 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
1067 SDValue SetCC = N->getOperand(0);
1069 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
1072 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
1073 SetCC.getOperand(0), SetCC.getOperand(1),
1074 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
1080 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
1081 const MipsSubtarget &Subtarget) {
1082 EVT Ty = N->getValueType(0);
1084 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
1085 // Try the following combines:
1086 // (xor (or $a, $b), (build_vector allones))
1087 // (xor (or $a, $b), (bitcast (build_vector allones)))
1088 SDValue Op0 = N->getOperand(0);
1089 SDValue Op1 = N->getOperand(1);
1092 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
1094 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1099 if (NotOp->getOpcode() == ISD::OR)
1100 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1101 NotOp->getOperand(1));
1108 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1109 SelectionDAG &DAG = DCI.DAG;
1112 switch (N->getOpcode()) {
1114 return performADDECombine(N, DAG, DCI, Subtarget);
1116 Val = performANDCombine(N, DAG, DCI, Subtarget);
1119 Val = performORCombine(N, DAG, DCI, Subtarget);
1122 return performSUBECombine(N, DAG, DCI, Subtarget);
1124 return performMULCombine(N, DAG, DCI, this);
1126 Val = performSHLCombine(N, DAG, DCI, Subtarget);
1129 return performSRACombine(N, DAG, DCI, Subtarget);
1131 return performSRLCombine(N, DAG, DCI, Subtarget);
1133 return performVSELECTCombine(N, DAG);
1135 Val = performXORCombine(N, DAG, Subtarget);
1138 Val = performSETCCCombine(N, DAG);
1142 if (Val.getNode()) {
1143 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1144 N->printrWithDepth(dbgs(), &DAG);
1145 dbgs() << "\n=> \n";
1146 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1151 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1155 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1156 MachineBasicBlock *BB) const {
1157 switch (MI.getOpcode()) {
1159 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1160 case Mips::BPOSGE32_PSEUDO:
1161 return emitBPOSGE32(MI, BB);
1162 case Mips::SNZ_B_PSEUDO:
1163 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1164 case Mips::SNZ_H_PSEUDO:
1165 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1166 case Mips::SNZ_W_PSEUDO:
1167 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1168 case Mips::SNZ_D_PSEUDO:
1169 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1170 case Mips::SNZ_V_PSEUDO:
1171 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1172 case Mips::SZ_B_PSEUDO:
1173 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1174 case Mips::SZ_H_PSEUDO:
1175 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1176 case Mips::SZ_W_PSEUDO:
1177 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1178 case Mips::SZ_D_PSEUDO:
1179 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1180 case Mips::SZ_V_PSEUDO:
1181 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1182 case Mips::COPY_FW_PSEUDO:
1183 return emitCOPY_FW(MI, BB);
1184 case Mips::COPY_FD_PSEUDO:
1185 return emitCOPY_FD(MI, BB);
1186 case Mips::INSERT_FW_PSEUDO:
1187 return emitINSERT_FW(MI, BB);
1188 case Mips::INSERT_FD_PSEUDO:
1189 return emitINSERT_FD(MI, BB);
1190 case Mips::INSERT_B_VIDX_PSEUDO:
1191 case Mips::INSERT_B_VIDX64_PSEUDO:
1192 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1193 case Mips::INSERT_H_VIDX_PSEUDO:
1194 case Mips::INSERT_H_VIDX64_PSEUDO:
1195 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1196 case Mips::INSERT_W_VIDX_PSEUDO:
1197 case Mips::INSERT_W_VIDX64_PSEUDO:
1198 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1199 case Mips::INSERT_D_VIDX_PSEUDO:
1200 case Mips::INSERT_D_VIDX64_PSEUDO:
1201 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1202 case Mips::INSERT_FW_VIDX_PSEUDO:
1203 case Mips::INSERT_FW_VIDX64_PSEUDO:
1204 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1205 case Mips::INSERT_FD_VIDX_PSEUDO:
1206 case Mips::INSERT_FD_VIDX64_PSEUDO:
1207 return emitINSERT_DF_VIDX(MI, BB, 8, true);
1208 case Mips::FILL_FW_PSEUDO:
1209 return emitFILL_FW(MI, BB);
1210 case Mips::FILL_FD_PSEUDO:
1211 return emitFILL_FD(MI, BB);
1212 case Mips::FEXP2_W_1_PSEUDO:
1213 return emitFEXP2_W_1(MI, BB);
1214 case Mips::FEXP2_D_1_PSEUDO:
1215 return emitFEXP2_D_1(MI, BB);
1217 return emitST_F16_PSEUDO(MI, BB);
1219 return emitLD_F16_PSEUDO(MI, BB);
1220 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1221 return emitFPEXTEND_PSEUDO(MI, BB, false);
1222 case Mips::MSA_FP_ROUND_W_PSEUDO:
1223 return emitFPROUND_PSEUDO(MI, BB, false);
1224 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1225 return emitFPEXTEND_PSEUDO(MI, BB, true);
1226 case Mips::MSA_FP_ROUND_D_PSEUDO:
1227 return emitFPROUND_PSEUDO(MI, BB, true);
1231 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1232 const CCState &CCInfo, unsigned NextStackOffset,
1233 const MipsFunctionInfo &FI) const {
1234 if (!UseMipsTailCalls)
1237 // Exception has to be cleared with eret.
1241 // Return false if either the callee or caller has a byval argument.
1242 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1245 // Return true if the callee's argument area is no larger than the
1247 return NextStackOffset <= FI.getIncomingArgSize();
1250 void MipsSETargetLowering::
1251 getOpndList(SmallVectorImpl<SDValue> &Ops,
1252 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1253 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1254 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1255 SDValue Chain) const {
1256 Ops.push_back(Callee);
1257 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1258 InternalLinkage, IsCallReloc, CLI, Callee,
1262 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1263 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1265 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1266 return MipsTargetLowering::lowerLOAD(Op, DAG);
1268 // Replace a double precision load with two i32 loads and a buildpair64.
1270 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1271 EVT PtrVT = Ptr.getValueType();
1273 // i32 load from lower address.
1274 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1275 Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1277 // i32 load from higher address.
1278 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1279 SDValue Hi = DAG.getLoad(
1280 MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1281 std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1283 if (!Subtarget.isLittle())
1286 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1287 SDValue Ops[2] = {BP, Hi.getValue(1)};
1288 return DAG.getMergeValues(Ops, DL);
1291 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1292 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1294 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1295 return MipsTargetLowering::lowerSTORE(Op, DAG);
1297 // Replace a double precision store with two extractelement64s and i32 stores.
1299 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1300 EVT PtrVT = Ptr.getValueType();
1301 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1302 Val, DAG.getConstant(0, DL, MVT::i32));
1303 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1304 Val, DAG.getConstant(1, DL, MVT::i32));
1306 if (!Subtarget.isLittle())
1309 // i32 store to lower address.
1311 DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1312 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1314 // i32 store to higher address.
1315 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1316 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1317 std::min(Nd.getAlignment(), 4U),
1318 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1321 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1322 bool HasLo, bool HasHi,
1323 SelectionDAG &DAG) const {
1324 // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1325 assert(!Subtarget.hasMips32r6());
1327 EVT Ty = Op.getOperand(0).getValueType();
1329 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1330 Op.getOperand(0), Op.getOperand(1));
1334 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1336 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1338 if (!HasLo || !HasHi)
1339 return HasLo ? Lo : Hi;
1341 SDValue Vals[] = { Lo, Hi };
1342 return DAG.getMergeValues(Vals, DL);
1345 static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) {
1346 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1347 DAG.getConstant(0, DL, MVT::i32));
1348 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1349 DAG.getConstant(1, DL, MVT::i32));
1350 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1353 static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
1354 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1355 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1356 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1359 // This function expands mips intrinsic nodes which have 64-bit input operands
1360 // or output values.
1362 // out64 = intrinsic-node in64
1364 // lo = copy (extract-element (in64, 0))
1365 // hi = copy (extract-element (in64, 1))
1366 // mips-specific-node
1369 // out64 = merge-values (v0, v1)
1371 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1373 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1374 SmallVector<SDValue, 3> Ops;
1377 // See if Op has a chain input.
1379 Ops.push_back(Op->getOperand(OpNo++));
1381 // The next operand is the intrinsic opcode.
1382 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1384 // See if the next operand has type i64.
1385 SDValue Opnd = Op->getOperand(++OpNo), In64;
1387 if (Opnd.getValueType() == MVT::i64)
1388 In64 = initAccumulator(Opnd, DL, DAG);
1390 Ops.push_back(Opnd);
1392 // Push the remaining operands.
1393 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1394 Ops.push_back(Op->getOperand(OpNo));
1396 // Add In64 to the end of the list.
1398 Ops.push_back(In64);
1401 SmallVector<EVT, 2> ResTys;
1403 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1405 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1408 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1409 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1414 assert(Val->getValueType(1) == MVT::Other);
1415 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1416 return DAG.getMergeValues(Vals, DL);
1419 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1420 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1422 SDValue Vec = Op->getOperand(1);
1423 SDValue Idx = Op->getOperand(2);
1424 EVT ResTy = Op->getValueType(0);
1425 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1427 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1428 DAG.getValueType(EltTy));
1433 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1434 EVT ResVecTy = Op->getValueType(0);
1435 EVT ViaVecTy = ResVecTy;
1438 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1439 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1442 SDValue LaneB = Op->getOperand(2);
1444 if (ResVecTy == MVT::v2i64) {
1445 LaneA = DAG.getConstant(0, DL, MVT::i32);
1446 ViaVecTy = MVT::v4i32;
1450 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1451 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1453 SDValue Result = DAG.getBuildVector(
1454 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1456 if (ViaVecTy != ResVecTy)
1457 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1462 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1463 bool IsSigned = false) {
1464 return DAG.getConstant(
1465 APInt(Op->getValueType(0).getScalarType().getSizeInBits(),
1466 Op->getConstantOperandVal(ImmOp), IsSigned),
1467 SDLoc(Op), Op->getValueType(0));
1470 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1471 bool BigEndian, SelectionDAG &DAG) {
1472 EVT ViaVecTy = VecTy;
1473 SDValue SplatValueA = SplatValue;
1474 SDValue SplatValueB = SplatValue;
1475 SDLoc DL(SplatValue);
1477 if (VecTy == MVT::v2i64) {
1478 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1479 ViaVecTy = MVT::v4i32;
1481 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1482 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1483 DAG.getConstant(32, DL, MVT::i32));
1484 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1487 // We currently hold the parts in little endian order. Swap them if
1490 std::swap(SplatValueA, SplatValueB);
1492 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1493 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1494 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1495 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1497 SDValue Result = DAG.getBuildVector(
1498 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1500 if (VecTy != ViaVecTy)
1501 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1506 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1507 unsigned Opc, SDValue Imm,
1509 EVT VecTy = Op->getValueType(0);
1513 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1515 if (VecTy == MVT::v2i64) {
1516 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1517 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1519 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1521 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1524 std::swap(BitImmLoOp, BitImmHiOp);
1526 Exp2Imm = DAG.getNode(
1527 ISD::BITCAST, DL, MVT::v2i64,
1528 DAG.getBuildVector(MVT::v4i32, DL,
1529 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1533 if (!Exp2Imm.getNode()) {
1534 // We couldnt constant fold, do a vector shift instead
1536 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1537 // only values 0-63 are valid.
1538 if (VecTy == MVT::v2i64)
1539 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1541 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1543 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1547 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1550 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1551 EVT ResTy = Op->getValueType(0);
1553 SDValue One = DAG.getConstant(1, DL, ResTy);
1554 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1556 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1557 DAG.getNOT(DL, Bit, ResTy));
1560 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1562 EVT ResTy = Op->getValueType(0);
1563 APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1564 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1565 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1567 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1570 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1571 SelectionDAG &DAG) const {
1573 unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1574 switch (Intrinsic) {
1577 case Intrinsic::mips_shilo:
1578 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1579 case Intrinsic::mips_dpau_h_qbl:
1580 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1581 case Intrinsic::mips_dpau_h_qbr:
1582 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1583 case Intrinsic::mips_dpsu_h_qbl:
1584 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1585 case Intrinsic::mips_dpsu_h_qbr:
1586 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1587 case Intrinsic::mips_dpa_w_ph:
1588 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1589 case Intrinsic::mips_dps_w_ph:
1590 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1591 case Intrinsic::mips_dpax_w_ph:
1592 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1593 case Intrinsic::mips_dpsx_w_ph:
1594 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1595 case Intrinsic::mips_mulsa_w_ph:
1596 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1597 case Intrinsic::mips_mult:
1598 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1599 case Intrinsic::mips_multu:
1600 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1601 case Intrinsic::mips_madd:
1602 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1603 case Intrinsic::mips_maddu:
1604 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1605 case Intrinsic::mips_msub:
1606 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1607 case Intrinsic::mips_msubu:
1608 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1609 case Intrinsic::mips_addv_b:
1610 case Intrinsic::mips_addv_h:
1611 case Intrinsic::mips_addv_w:
1612 case Intrinsic::mips_addv_d:
1613 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1615 case Intrinsic::mips_addvi_b:
1616 case Intrinsic::mips_addvi_h:
1617 case Intrinsic::mips_addvi_w:
1618 case Intrinsic::mips_addvi_d:
1619 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1620 lowerMSASplatImm(Op, 2, DAG));
1621 case Intrinsic::mips_and_v:
1622 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1624 case Intrinsic::mips_andi_b:
1625 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1626 lowerMSASplatImm(Op, 2, DAG));
1627 case Intrinsic::mips_bclr_b:
1628 case Intrinsic::mips_bclr_h:
1629 case Intrinsic::mips_bclr_w:
1630 case Intrinsic::mips_bclr_d:
1631 return lowerMSABitClear(Op, DAG);
1632 case Intrinsic::mips_bclri_b:
1633 case Intrinsic::mips_bclri_h:
1634 case Intrinsic::mips_bclri_w:
1635 case Intrinsic::mips_bclri_d:
1636 return lowerMSABitClearImm(Op, DAG);
1637 case Intrinsic::mips_binsli_b:
1638 case Intrinsic::mips_binsli_h:
1639 case Intrinsic::mips_binsli_w:
1640 case Intrinsic::mips_binsli_d: {
1641 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1642 EVT VecTy = Op->getValueType(0);
1643 EVT EltTy = VecTy.getVectorElementType();
1644 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1645 report_fatal_error("Immediate out of range");
1646 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1647 Op->getConstantOperandVal(3) + 1);
1648 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1649 DAG.getConstant(Mask, DL, VecTy, true),
1650 Op->getOperand(2), Op->getOperand(1));
1652 case Intrinsic::mips_binsri_b:
1653 case Intrinsic::mips_binsri_h:
1654 case Intrinsic::mips_binsri_w:
1655 case Intrinsic::mips_binsri_d: {
1656 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1657 EVT VecTy = Op->getValueType(0);
1658 EVT EltTy = VecTy.getVectorElementType();
1659 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1660 report_fatal_error("Immediate out of range");
1661 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1662 Op->getConstantOperandVal(3) + 1);
1663 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1664 DAG.getConstant(Mask, DL, VecTy, true),
1665 Op->getOperand(2), Op->getOperand(1));
1667 case Intrinsic::mips_bmnz_v:
1668 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1669 Op->getOperand(2), Op->getOperand(1));
1670 case Intrinsic::mips_bmnzi_b:
1671 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1672 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1674 case Intrinsic::mips_bmz_v:
1675 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1676 Op->getOperand(1), Op->getOperand(2));
1677 case Intrinsic::mips_bmzi_b:
1678 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1679 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1681 case Intrinsic::mips_bneg_b:
1682 case Intrinsic::mips_bneg_h:
1683 case Intrinsic::mips_bneg_w:
1684 case Intrinsic::mips_bneg_d: {
1685 EVT VecTy = Op->getValueType(0);
1686 SDValue One = DAG.getConstant(1, DL, VecTy);
1688 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1689 DAG.getNode(ISD::SHL, DL, VecTy, One,
1690 Op->getOperand(2)));
1692 case Intrinsic::mips_bnegi_b:
1693 case Intrinsic::mips_bnegi_h:
1694 case Intrinsic::mips_bnegi_w:
1695 case Intrinsic::mips_bnegi_d:
1696 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1697 !Subtarget.isLittle());
1698 case Intrinsic::mips_bnz_b:
1699 case Intrinsic::mips_bnz_h:
1700 case Intrinsic::mips_bnz_w:
1701 case Intrinsic::mips_bnz_d:
1702 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1704 case Intrinsic::mips_bnz_v:
1705 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1707 case Intrinsic::mips_bsel_v:
1708 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1709 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1710 Op->getOperand(1), Op->getOperand(3),
1712 case Intrinsic::mips_bseli_b:
1713 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1714 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1715 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1717 case Intrinsic::mips_bset_b:
1718 case Intrinsic::mips_bset_h:
1719 case Intrinsic::mips_bset_w:
1720 case Intrinsic::mips_bset_d: {
1721 EVT VecTy = Op->getValueType(0);
1722 SDValue One = DAG.getConstant(1, DL, VecTy);
1724 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1725 DAG.getNode(ISD::SHL, DL, VecTy, One,
1726 Op->getOperand(2)));
1728 case Intrinsic::mips_bseti_b:
1729 case Intrinsic::mips_bseti_h:
1730 case Intrinsic::mips_bseti_w:
1731 case Intrinsic::mips_bseti_d:
1732 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1733 !Subtarget.isLittle());
1734 case Intrinsic::mips_bz_b:
1735 case Intrinsic::mips_bz_h:
1736 case Intrinsic::mips_bz_w:
1737 case Intrinsic::mips_bz_d:
1738 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1740 case Intrinsic::mips_bz_v:
1741 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1743 case Intrinsic::mips_ceq_b:
1744 case Intrinsic::mips_ceq_h:
1745 case Intrinsic::mips_ceq_w:
1746 case Intrinsic::mips_ceq_d:
1747 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1748 Op->getOperand(2), ISD::SETEQ);
1749 case Intrinsic::mips_ceqi_b:
1750 case Intrinsic::mips_ceqi_h:
1751 case Intrinsic::mips_ceqi_w:
1752 case Intrinsic::mips_ceqi_d:
1753 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1754 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
1755 case Intrinsic::mips_cle_s_b:
1756 case Intrinsic::mips_cle_s_h:
1757 case Intrinsic::mips_cle_s_w:
1758 case Intrinsic::mips_cle_s_d:
1759 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1760 Op->getOperand(2), ISD::SETLE);
1761 case Intrinsic::mips_clei_s_b:
1762 case Intrinsic::mips_clei_s_h:
1763 case Intrinsic::mips_clei_s_w:
1764 case Intrinsic::mips_clei_s_d:
1765 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1766 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
1767 case Intrinsic::mips_cle_u_b:
1768 case Intrinsic::mips_cle_u_h:
1769 case Intrinsic::mips_cle_u_w:
1770 case Intrinsic::mips_cle_u_d:
1771 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1772 Op->getOperand(2), ISD::SETULE);
1773 case Intrinsic::mips_clei_u_b:
1774 case Intrinsic::mips_clei_u_h:
1775 case Intrinsic::mips_clei_u_w:
1776 case Intrinsic::mips_clei_u_d:
1777 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1778 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1779 case Intrinsic::mips_clt_s_b:
1780 case Intrinsic::mips_clt_s_h:
1781 case Intrinsic::mips_clt_s_w:
1782 case Intrinsic::mips_clt_s_d:
1783 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1784 Op->getOperand(2), ISD::SETLT);
1785 case Intrinsic::mips_clti_s_b:
1786 case Intrinsic::mips_clti_s_h:
1787 case Intrinsic::mips_clti_s_w:
1788 case Intrinsic::mips_clti_s_d:
1789 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1790 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
1791 case Intrinsic::mips_clt_u_b:
1792 case Intrinsic::mips_clt_u_h:
1793 case Intrinsic::mips_clt_u_w:
1794 case Intrinsic::mips_clt_u_d:
1795 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1796 Op->getOperand(2), ISD::SETULT);
1797 case Intrinsic::mips_clti_u_b:
1798 case Intrinsic::mips_clti_u_h:
1799 case Intrinsic::mips_clti_u_w:
1800 case Intrinsic::mips_clti_u_d:
1801 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1802 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1803 case Intrinsic::mips_copy_s_b:
1804 case Intrinsic::mips_copy_s_h:
1805 case Intrinsic::mips_copy_s_w:
1806 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1807 case Intrinsic::mips_copy_s_d:
1808 if (Subtarget.hasMips64())
1809 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1810 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1812 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1813 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1814 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1815 Op->getValueType(0), Op->getOperand(1),
1818 case Intrinsic::mips_copy_u_b:
1819 case Intrinsic::mips_copy_u_h:
1820 case Intrinsic::mips_copy_u_w:
1821 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1822 case Intrinsic::mips_copy_u_d:
1823 if (Subtarget.hasMips64())
1824 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1825 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1827 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1828 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1829 // Note: When i64 is illegal, this results in copy_s.w instructions
1830 // instead of copy_u.w instructions. This makes no difference to the
1831 // behaviour since i64 is only illegal when the register file is 32-bit.
1832 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1833 Op->getValueType(0), Op->getOperand(1),
1836 case Intrinsic::mips_div_s_b:
1837 case Intrinsic::mips_div_s_h:
1838 case Intrinsic::mips_div_s_w:
1839 case Intrinsic::mips_div_s_d:
1840 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1842 case Intrinsic::mips_div_u_b:
1843 case Intrinsic::mips_div_u_h:
1844 case Intrinsic::mips_div_u_w:
1845 case Intrinsic::mips_div_u_d:
1846 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1848 case Intrinsic::mips_fadd_w:
1849 case Intrinsic::mips_fadd_d: {
1850 // TODO: If intrinsics have fast-math-flags, propagate them.
1851 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1854 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1855 case Intrinsic::mips_fceq_w:
1856 case Intrinsic::mips_fceq_d:
1857 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1858 Op->getOperand(2), ISD::SETOEQ);
1859 case Intrinsic::mips_fcle_w:
1860 case Intrinsic::mips_fcle_d:
1861 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1862 Op->getOperand(2), ISD::SETOLE);
1863 case Intrinsic::mips_fclt_w:
1864 case Intrinsic::mips_fclt_d:
1865 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1866 Op->getOperand(2), ISD::SETOLT);
1867 case Intrinsic::mips_fcne_w:
1868 case Intrinsic::mips_fcne_d:
1869 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1870 Op->getOperand(2), ISD::SETONE);
1871 case Intrinsic::mips_fcor_w:
1872 case Intrinsic::mips_fcor_d:
1873 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1874 Op->getOperand(2), ISD::SETO);
1875 case Intrinsic::mips_fcueq_w:
1876 case Intrinsic::mips_fcueq_d:
1877 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1878 Op->getOperand(2), ISD::SETUEQ);
1879 case Intrinsic::mips_fcule_w:
1880 case Intrinsic::mips_fcule_d:
1881 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1882 Op->getOperand(2), ISD::SETULE);
1883 case Intrinsic::mips_fcult_w:
1884 case Intrinsic::mips_fcult_d:
1885 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1886 Op->getOperand(2), ISD::SETULT);
1887 case Intrinsic::mips_fcun_w:
1888 case Intrinsic::mips_fcun_d:
1889 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1890 Op->getOperand(2), ISD::SETUO);
1891 case Intrinsic::mips_fcune_w:
1892 case Intrinsic::mips_fcune_d:
1893 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1894 Op->getOperand(2), ISD::SETUNE);
1895 case Intrinsic::mips_fdiv_w:
1896 case Intrinsic::mips_fdiv_d: {
1897 // TODO: If intrinsics have fast-math-flags, propagate them.
1898 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1901 case Intrinsic::mips_ffint_u_w:
1902 case Intrinsic::mips_ffint_u_d:
1903 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1905 case Intrinsic::mips_ffint_s_w:
1906 case Intrinsic::mips_ffint_s_d:
1907 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1909 case Intrinsic::mips_fill_b:
1910 case Intrinsic::mips_fill_h:
1911 case Intrinsic::mips_fill_w:
1912 case Intrinsic::mips_fill_d: {
1913 EVT ResTy = Op->getValueType(0);
1914 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
1917 // If ResTy is v2i64 then the type legalizer will break this node down into
1918 // an equivalent v4i32.
1919 return DAG.getBuildVector(ResTy, DL, Ops);
1921 case Intrinsic::mips_fexp2_w:
1922 case Intrinsic::mips_fexp2_d: {
1923 // TODO: If intrinsics have fast-math-flags, propagate them.
1924 EVT ResTy = Op->getValueType(0);
1926 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1927 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1929 case Intrinsic::mips_flog2_w:
1930 case Intrinsic::mips_flog2_d:
1931 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1932 case Intrinsic::mips_fmadd_w:
1933 case Intrinsic::mips_fmadd_d:
1934 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1935 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1936 case Intrinsic::mips_fmul_w:
1937 case Intrinsic::mips_fmul_d: {
1938 // TODO: If intrinsics have fast-math-flags, propagate them.
1939 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1942 case Intrinsic::mips_fmsub_w:
1943 case Intrinsic::mips_fmsub_d: {
1944 // TODO: If intrinsics have fast-math-flags, propagate them.
1945 EVT ResTy = Op->getValueType(0);
1946 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1947 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1948 Op->getOperand(2), Op->getOperand(3)));
1950 case Intrinsic::mips_frint_w:
1951 case Intrinsic::mips_frint_d:
1952 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1953 case Intrinsic::mips_fsqrt_w:
1954 case Intrinsic::mips_fsqrt_d:
1955 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1956 case Intrinsic::mips_fsub_w:
1957 case Intrinsic::mips_fsub_d: {
1958 // TODO: If intrinsics have fast-math-flags, propagate them.
1959 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1962 case Intrinsic::mips_ftrunc_u_w:
1963 case Intrinsic::mips_ftrunc_u_d:
1964 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1966 case Intrinsic::mips_ftrunc_s_w:
1967 case Intrinsic::mips_ftrunc_s_d:
1968 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1970 case Intrinsic::mips_ilvev_b:
1971 case Intrinsic::mips_ilvev_h:
1972 case Intrinsic::mips_ilvev_w:
1973 case Intrinsic::mips_ilvev_d:
1974 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1975 Op->getOperand(1), Op->getOperand(2));
1976 case Intrinsic::mips_ilvl_b:
1977 case Intrinsic::mips_ilvl_h:
1978 case Intrinsic::mips_ilvl_w:
1979 case Intrinsic::mips_ilvl_d:
1980 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1981 Op->getOperand(1), Op->getOperand(2));
1982 case Intrinsic::mips_ilvod_b:
1983 case Intrinsic::mips_ilvod_h:
1984 case Intrinsic::mips_ilvod_w:
1985 case Intrinsic::mips_ilvod_d:
1986 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1987 Op->getOperand(1), Op->getOperand(2));
1988 case Intrinsic::mips_ilvr_b:
1989 case Intrinsic::mips_ilvr_h:
1990 case Intrinsic::mips_ilvr_w:
1991 case Intrinsic::mips_ilvr_d:
1992 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1993 Op->getOperand(1), Op->getOperand(2));
1994 case Intrinsic::mips_insert_b:
1995 case Intrinsic::mips_insert_h:
1996 case Intrinsic::mips_insert_w:
1997 case Intrinsic::mips_insert_d:
1998 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1999 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
2000 case Intrinsic::mips_insve_b:
2001 case Intrinsic::mips_insve_h:
2002 case Intrinsic::mips_insve_w:
2003 case Intrinsic::mips_insve_d: {
2004 // Report an error for out of range values.
2006 switch (Intrinsic) {
2007 case Intrinsic::mips_insve_b: Max = 15; break;
2008 case Intrinsic::mips_insve_h: Max = 7; break;
2009 case Intrinsic::mips_insve_w: Max = 3; break;
2010 case Intrinsic::mips_insve_d: Max = 1; break;
2011 default: llvm_unreachable("Unmatched intrinsic");
2013 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2014 if (Value < 0 || Value > Max)
2015 report_fatal_error("Immediate out of range");
2016 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
2017 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
2018 DAG.getConstant(0, DL, MVT::i32));
2020 case Intrinsic::mips_ldi_b:
2021 case Intrinsic::mips_ldi_h:
2022 case Intrinsic::mips_ldi_w:
2023 case Intrinsic::mips_ldi_d:
2024 return lowerMSASplatImm(Op, 1, DAG, true);
2025 case Intrinsic::mips_lsa:
2026 case Intrinsic::mips_dlsa: {
2027 EVT ResTy = Op->getValueType(0);
2028 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2029 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
2030 Op->getOperand(2), Op->getOperand(3)));
2032 case Intrinsic::mips_maddv_b:
2033 case Intrinsic::mips_maddv_h:
2034 case Intrinsic::mips_maddv_w:
2035 case Intrinsic::mips_maddv_d: {
2036 EVT ResTy = Op->getValueType(0);
2037 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2038 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2039 Op->getOperand(2), Op->getOperand(3)));
2041 case Intrinsic::mips_max_s_b:
2042 case Intrinsic::mips_max_s_h:
2043 case Intrinsic::mips_max_s_w:
2044 case Intrinsic::mips_max_s_d:
2045 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
2046 Op->getOperand(1), Op->getOperand(2));
2047 case Intrinsic::mips_max_u_b:
2048 case Intrinsic::mips_max_u_h:
2049 case Intrinsic::mips_max_u_w:
2050 case Intrinsic::mips_max_u_d:
2051 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
2052 Op->getOperand(1), Op->getOperand(2));
2053 case Intrinsic::mips_maxi_s_b:
2054 case Intrinsic::mips_maxi_s_h:
2055 case Intrinsic::mips_maxi_s_w:
2056 case Intrinsic::mips_maxi_s_d:
2057 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
2058 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2059 case Intrinsic::mips_maxi_u_b:
2060 case Intrinsic::mips_maxi_u_h:
2061 case Intrinsic::mips_maxi_u_w:
2062 case Intrinsic::mips_maxi_u_d:
2063 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
2064 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2065 case Intrinsic::mips_min_s_b:
2066 case Intrinsic::mips_min_s_h:
2067 case Intrinsic::mips_min_s_w:
2068 case Intrinsic::mips_min_s_d:
2069 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
2070 Op->getOperand(1), Op->getOperand(2));
2071 case Intrinsic::mips_min_u_b:
2072 case Intrinsic::mips_min_u_h:
2073 case Intrinsic::mips_min_u_w:
2074 case Intrinsic::mips_min_u_d:
2075 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
2076 Op->getOperand(1), Op->getOperand(2));
2077 case Intrinsic::mips_mini_s_b:
2078 case Intrinsic::mips_mini_s_h:
2079 case Intrinsic::mips_mini_s_w:
2080 case Intrinsic::mips_mini_s_d:
2081 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
2082 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
2083 case Intrinsic::mips_mini_u_b:
2084 case Intrinsic::mips_mini_u_h:
2085 case Intrinsic::mips_mini_u_w:
2086 case Intrinsic::mips_mini_u_d:
2087 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
2088 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2089 case Intrinsic::mips_mod_s_b:
2090 case Intrinsic::mips_mod_s_h:
2091 case Intrinsic::mips_mod_s_w:
2092 case Intrinsic::mips_mod_s_d:
2093 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2095 case Intrinsic::mips_mod_u_b:
2096 case Intrinsic::mips_mod_u_h:
2097 case Intrinsic::mips_mod_u_w:
2098 case Intrinsic::mips_mod_u_d:
2099 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2101 case Intrinsic::mips_mulv_b:
2102 case Intrinsic::mips_mulv_h:
2103 case Intrinsic::mips_mulv_w:
2104 case Intrinsic::mips_mulv_d:
2105 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2107 case Intrinsic::mips_msubv_b:
2108 case Intrinsic::mips_msubv_h:
2109 case Intrinsic::mips_msubv_w:
2110 case Intrinsic::mips_msubv_d: {
2111 EVT ResTy = Op->getValueType(0);
2112 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2113 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2114 Op->getOperand(2), Op->getOperand(3)));
2116 case Intrinsic::mips_nlzc_b:
2117 case Intrinsic::mips_nlzc_h:
2118 case Intrinsic::mips_nlzc_w:
2119 case Intrinsic::mips_nlzc_d:
2120 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2121 case Intrinsic::mips_nor_v: {
2122 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2123 Op->getOperand(1), Op->getOperand(2));
2124 return DAG.getNOT(DL, Res, Res->getValueType(0));
2126 case Intrinsic::mips_nori_b: {
2127 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2129 lowerMSASplatImm(Op, 2, DAG));
2130 return DAG.getNOT(DL, Res, Res->getValueType(0));
2132 case Intrinsic::mips_or_v:
2133 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2135 case Intrinsic::mips_ori_b:
2136 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2137 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2138 case Intrinsic::mips_pckev_b:
2139 case Intrinsic::mips_pckev_h:
2140 case Intrinsic::mips_pckev_w:
2141 case Intrinsic::mips_pckev_d:
2142 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2143 Op->getOperand(1), Op->getOperand(2));
2144 case Intrinsic::mips_pckod_b:
2145 case Intrinsic::mips_pckod_h:
2146 case Intrinsic::mips_pckod_w:
2147 case Intrinsic::mips_pckod_d:
2148 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2149 Op->getOperand(1), Op->getOperand(2));
2150 case Intrinsic::mips_pcnt_b:
2151 case Intrinsic::mips_pcnt_h:
2152 case Intrinsic::mips_pcnt_w:
2153 case Intrinsic::mips_pcnt_d:
2154 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2155 case Intrinsic::mips_sat_s_b:
2156 case Intrinsic::mips_sat_s_h:
2157 case Intrinsic::mips_sat_s_w:
2158 case Intrinsic::mips_sat_s_d:
2159 case Intrinsic::mips_sat_u_b:
2160 case Intrinsic::mips_sat_u_h:
2161 case Intrinsic::mips_sat_u_w:
2162 case Intrinsic::mips_sat_u_d: {
2163 // Report an error for out of range values.
2165 switch (Intrinsic) {
2166 case Intrinsic::mips_sat_s_b:
2167 case Intrinsic::mips_sat_u_b: Max = 7; break;
2168 case Intrinsic::mips_sat_s_h:
2169 case Intrinsic::mips_sat_u_h: Max = 15; break;
2170 case Intrinsic::mips_sat_s_w:
2171 case Intrinsic::mips_sat_u_w: Max = 31; break;
2172 case Intrinsic::mips_sat_s_d:
2173 case Intrinsic::mips_sat_u_d: Max = 63; break;
2174 default: llvm_unreachable("Unmatched intrinsic");
2176 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2177 if (Value < 0 || Value > Max)
2178 report_fatal_error("Immediate out of range");
2181 case Intrinsic::mips_shf_b:
2182 case Intrinsic::mips_shf_h:
2183 case Intrinsic::mips_shf_w: {
2184 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2185 if (Value < 0 || Value > 255)
2186 report_fatal_error("Immediate out of range");
2187 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2188 Op->getOperand(2), Op->getOperand(1));
2190 case Intrinsic::mips_sldi_b:
2191 case Intrinsic::mips_sldi_h:
2192 case Intrinsic::mips_sldi_w:
2193 case Intrinsic::mips_sldi_d: {
2194 // Report an error for out of range values.
2196 switch (Intrinsic) {
2197 case Intrinsic::mips_sldi_b: Max = 15; break;
2198 case Intrinsic::mips_sldi_h: Max = 7; break;
2199 case Intrinsic::mips_sldi_w: Max = 3; break;
2200 case Intrinsic::mips_sldi_d: Max = 1; break;
2201 default: llvm_unreachable("Unmatched intrinsic");
2203 int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2204 if (Value < 0 || Value > Max)
2205 report_fatal_error("Immediate out of range");
2208 case Intrinsic::mips_sll_b:
2209 case Intrinsic::mips_sll_h:
2210 case Intrinsic::mips_sll_w:
2211 case Intrinsic::mips_sll_d:
2212 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2214 case Intrinsic::mips_slli_b:
2215 case Intrinsic::mips_slli_h:
2216 case Intrinsic::mips_slli_w:
2217 case Intrinsic::mips_slli_d:
2218 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2219 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2220 case Intrinsic::mips_splat_b:
2221 case Intrinsic::mips_splat_h:
2222 case Intrinsic::mips_splat_w:
2223 case Intrinsic::mips_splat_d:
2224 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2225 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2226 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2227 // Instead we lower to MipsISD::VSHF and match from there.
2228 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2229 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2231 case Intrinsic::mips_splati_b:
2232 case Intrinsic::mips_splati_h:
2233 case Intrinsic::mips_splati_w:
2234 case Intrinsic::mips_splati_d:
2235 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2236 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2238 case Intrinsic::mips_sra_b:
2239 case Intrinsic::mips_sra_h:
2240 case Intrinsic::mips_sra_w:
2241 case Intrinsic::mips_sra_d:
2242 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2244 case Intrinsic::mips_srai_b:
2245 case Intrinsic::mips_srai_h:
2246 case Intrinsic::mips_srai_w:
2247 case Intrinsic::mips_srai_d:
2248 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2249 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2250 case Intrinsic::mips_srari_b:
2251 case Intrinsic::mips_srari_h:
2252 case Intrinsic::mips_srari_w:
2253 case Intrinsic::mips_srari_d: {
2254 // Report an error for out of range values.
2256 switch (Intrinsic) {
2257 case Intrinsic::mips_srari_b: Max = 7; break;
2258 case Intrinsic::mips_srari_h: Max = 15; break;
2259 case Intrinsic::mips_srari_w: Max = 31; break;
2260 case Intrinsic::mips_srari_d: Max = 63; break;
2261 default: llvm_unreachable("Unmatched intrinsic");
2263 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2264 if (Value < 0 || Value > Max)
2265 report_fatal_error("Immediate out of range");
2268 case Intrinsic::mips_srl_b:
2269 case Intrinsic::mips_srl_h:
2270 case Intrinsic::mips_srl_w:
2271 case Intrinsic::mips_srl_d:
2272 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2274 case Intrinsic::mips_srli_b:
2275 case Intrinsic::mips_srli_h:
2276 case Intrinsic::mips_srli_w:
2277 case Intrinsic::mips_srli_d:
2278 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2279 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2280 case Intrinsic::mips_srlri_b:
2281 case Intrinsic::mips_srlri_h:
2282 case Intrinsic::mips_srlri_w:
2283 case Intrinsic::mips_srlri_d: {
2284 // Report an error for out of range values.
2286 switch (Intrinsic) {
2287 case Intrinsic::mips_srlri_b: Max = 7; break;
2288 case Intrinsic::mips_srlri_h: Max = 15; break;
2289 case Intrinsic::mips_srlri_w: Max = 31; break;
2290 case Intrinsic::mips_srlri_d: Max = 63; break;
2291 default: llvm_unreachable("Unmatched intrinsic");
2293 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2294 if (Value < 0 || Value > Max)
2295 report_fatal_error("Immediate out of range");
2298 case Intrinsic::mips_subv_b:
2299 case Intrinsic::mips_subv_h:
2300 case Intrinsic::mips_subv_w:
2301 case Intrinsic::mips_subv_d:
2302 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2304 case Intrinsic::mips_subvi_b:
2305 case Intrinsic::mips_subvi_h:
2306 case Intrinsic::mips_subvi_w:
2307 case Intrinsic::mips_subvi_d:
2308 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2309 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2310 case Intrinsic::mips_vshf_b:
2311 case Intrinsic::mips_vshf_h:
2312 case Intrinsic::mips_vshf_w:
2313 case Intrinsic::mips_vshf_d:
2314 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2315 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2316 case Intrinsic::mips_xor_v:
2317 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2319 case Intrinsic::mips_xori_b:
2320 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2321 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2322 case Intrinsic::thread_pointer: {
2323 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2324 return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2329 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2330 const MipsSubtarget &Subtarget) {
2332 SDValue ChainIn = Op->getOperand(0);
2333 SDValue Address = Op->getOperand(2);
2334 SDValue Offset = Op->getOperand(3);
2335 EVT ResTy = Op->getValueType(0);
2336 EVT PtrTy = Address->getValueType(0);
2338 // For N64 addresses have the underlying type MVT::i64. This intrinsic
2339 // however takes an i32 signed constant offset. The actual type of the
2340 // intrinsic is a scaled signed i10.
2341 if (Subtarget.isABI_N64())
2342 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2344 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2345 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2346 /* Alignment = */ 16);
2349 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2350 SelectionDAG &DAG) const {
2351 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2355 case Intrinsic::mips_extp:
2356 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2357 case Intrinsic::mips_extpdp:
2358 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2359 case Intrinsic::mips_extr_w:
2360 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2361 case Intrinsic::mips_extr_r_w:
2362 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2363 case Intrinsic::mips_extr_rs_w:
2364 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2365 case Intrinsic::mips_extr_s_h:
2366 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2367 case Intrinsic::mips_mthlip:
2368 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2369 case Intrinsic::mips_mulsaq_s_w_ph:
2370 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2371 case Intrinsic::mips_maq_s_w_phl:
2372 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2373 case Intrinsic::mips_maq_s_w_phr:
2374 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2375 case Intrinsic::mips_maq_sa_w_phl:
2376 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2377 case Intrinsic::mips_maq_sa_w_phr:
2378 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2379 case Intrinsic::mips_dpaq_s_w_ph:
2380 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2381 case Intrinsic::mips_dpsq_s_w_ph:
2382 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2383 case Intrinsic::mips_dpaq_sa_l_w:
2384 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2385 case Intrinsic::mips_dpsq_sa_l_w:
2386 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2387 case Intrinsic::mips_dpaqx_s_w_ph:
2388 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2389 case Intrinsic::mips_dpaqx_sa_w_ph:
2390 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2391 case Intrinsic::mips_dpsqx_s_w_ph:
2392 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2393 case Intrinsic::mips_dpsqx_sa_w_ph:
2394 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2395 case Intrinsic::mips_ld_b:
2396 case Intrinsic::mips_ld_h:
2397 case Intrinsic::mips_ld_w:
2398 case Intrinsic::mips_ld_d:
2399 return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2403 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2404 const MipsSubtarget &Subtarget) {
2406 SDValue ChainIn = Op->getOperand(0);
2407 SDValue Value = Op->getOperand(2);
2408 SDValue Address = Op->getOperand(3);
2409 SDValue Offset = Op->getOperand(4);
2410 EVT PtrTy = Address->getValueType(0);
2412 // For N64 addresses have the underlying type MVT::i64. This intrinsic
2413 // however takes an i32 signed constant offset. The actual type of the
2414 // intrinsic is a scaled signed i10.
2415 if (Subtarget.isABI_N64())
2416 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2418 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2420 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2421 /* Alignment = */ 16);
2424 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2425 SelectionDAG &DAG) const {
2426 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2430 case Intrinsic::mips_st_b:
2431 case Intrinsic::mips_st_h:
2432 case Intrinsic::mips_st_w:
2433 case Intrinsic::mips_st_d:
2434 return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
2438 /// \brief Check if the given BuildVectorSDNode is a splat.
2439 /// This method currently relies on DAG nodes being reused when equivalent,
2440 /// so it's possible for this to return false even when isConstantSplat returns
2442 static bool isSplatVector(const BuildVectorSDNode *N) {
2443 unsigned int nOps = N->getNumOperands();
2444 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2446 SDValue Operand0 = N->getOperand(0);
2448 for (unsigned int i = 1; i < nOps; ++i) {
2449 if (N->getOperand(i) != Operand0)
2456 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2458 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2459 // choose to sign-extend but we could have equally chosen zero-extend. The
2460 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2461 // result into this node later (possibly changing it to a zero-extend in the
2463 SDValue MipsSETargetLowering::
2464 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2466 EVT ResTy = Op->getValueType(0);
2467 SDValue Op0 = Op->getOperand(0);
2468 EVT VecTy = Op0->getValueType(0);
2470 if (!VecTy.is128BitVector())
2473 if (ResTy.isInteger()) {
2474 SDValue Op1 = Op->getOperand(1);
2475 EVT EltTy = VecTy.getVectorElementType();
2476 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2477 DAG.getValueType(EltTy));
2483 static bool isConstantOrUndef(const SDValue Op) {
2486 if (isa<ConstantSDNode>(Op))
2488 if (isa<ConstantFPSDNode>(Op))
2493 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2494 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2495 if (isConstantOrUndef(Op->getOperand(i)))
2500 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2503 // Lowers according to the following rules:
2504 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2505 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2507 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2508 // is a power of 2 less than or equal to 64 and the value does not fit into a
2509 // signed 10-bit immediate
2510 // - Non-constant splats are legal as-is.
2511 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2512 // - All others are illegal and must be expanded.
2513 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2514 SelectionDAG &DAG) const {
2515 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2516 EVT ResTy = Op->getValueType(0);
2518 APInt SplatValue, SplatUndef;
2519 unsigned SplatBitSize;
2522 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2525 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2527 !Subtarget.isLittle()) && SplatBitSize <= 64) {
2528 // We can only cope with 8, 16, 32, or 64-bit elements
2529 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2533 // If the value isn't an integer type we will have to bitcast
2534 // from an integer type first. Also, if there are any undefs, we must
2535 // lower them to defined values first.
2536 if (ResTy.isInteger() && !HasAnyUndefs)
2541 switch (SplatBitSize) {
2545 ViaVecTy = MVT::v16i8;
2548 ViaVecTy = MVT::v8i16;
2551 ViaVecTy = MVT::v4i32;
2554 // There's no fill.d to fall back on for 64-bit values
2558 // SelectionDAG::getConstant will promote SplatValue appropriately.
2559 SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2561 // Bitcast to the type we originally wanted
2562 if (ViaVecTy != ResTy)
2563 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2566 } else if (isSplatVector(Node))
2568 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2569 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2570 // The resulting code is the same length as the expansion, but it doesn't
2571 // use memory operations
2572 EVT ResTy = Node->getValueType(0);
2574 assert(ResTy.isVector());
2576 unsigned NumElts = ResTy.getVectorNumElements();
2577 SDValue Vector = DAG.getUNDEF(ResTy);
2578 for (unsigned i = 0; i < NumElts; ++i) {
2579 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2580 Node->getOperand(i),
2581 DAG.getConstant(i, DL, MVT::i32));
2589 // Lower VECTOR_SHUFFLE into SHF (if possible).
2591 // SHF splits the vector into blocks of four elements, then shuffles these
2592 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2594 // It is therefore possible to lower into SHF when the mask takes the form:
2595 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2596 // When undef's appear they are treated as if they were whatever value is
2597 // necessary in order to fit the above forms.
2600 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2601 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2602 // i32 7, i32 6, i32 5, i32 4>
2604 // (SHF_H $w0, $w1, 27)
2605 // where the 27 comes from:
2606 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2607 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2608 SmallVector<int, 16> Indices,
2609 SelectionDAG &DAG) {
2610 int SHFIndices[4] = { -1, -1, -1, -1 };
2612 if (Indices.size() < 4)
2615 for (unsigned i = 0; i < 4; ++i) {
2616 for (unsigned j = i; j < Indices.size(); j += 4) {
2617 int Idx = Indices[j];
2619 // Convert from vector index to 4-element subvector index
2620 // If an index refers to an element outside of the subvector then give up
2623 if (Idx < 0 || Idx >= 4)
2627 // If the mask has an undef, replace it with the current index.
2628 // Note that it might still be undef if the current index is also undef
2629 if (SHFIndices[i] == -1)
2630 SHFIndices[i] = Idx;
2632 // Check that non-undef values are the same as in the mask. If they
2633 // aren't then give up
2634 if (!(Idx == -1 || Idx == SHFIndices[i]))
2639 // Calculate the immediate. Replace any remaining undefs with zero
2641 for (int i = 3; i >= 0; --i) {
2642 int Idx = SHFIndices[i];
2652 return DAG.getNode(MipsISD::SHF, DL, ResTy,
2653 DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
2656 /// Determine whether a range fits a regular pattern of values.
2657 /// This function accounts for the possibility of jumping over the End iterator.
2658 template <typename ValType>
2660 fitsRegularPattern(typename SmallVectorImpl<ValType>::const_iterator Begin,
2661 unsigned CheckStride,
2662 typename SmallVectorImpl<ValType>::const_iterator End,
2663 ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2667 if (*I != -1 && *I != ExpectedIndex)
2669 ExpectedIndex += ExpectedIndexStride;
2671 // Incrementing past End is undefined behaviour so we must increment one
2672 // step at a time and check for End at each step.
2673 for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2674 ; // Empty loop body.
2679 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2681 // It is a SPLATI when the mask is:
2683 // where x is any valid index.
2685 // When undef's appear in the mask they are treated as if they were whatever
2686 // value is necessary in order to fit the above form.
2687 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2688 SmallVector<int, 16> Indices,
2689 SelectionDAG &DAG) {
2690 assert((Indices.size() % 2) == 0);
2692 int SplatIndex = -1;
2693 for (const auto &V : Indices) {
2700 return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2704 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2706 // ILVEV interleaves the even elements from each vector.
2708 // It is possible to lower into ILVEV when the mask consists of two of the
2709 // following forms interleaved:
2711 // <n, n+2, n+4, ...>
2712 // where n is the number of elements in the vector.
2714 // <0, 0, 2, 2, 4, 4, ...>
2715 // <0, n, 2, n+2, 4, n+4, ...>
2717 // When undef's appear in the mask they are treated as if they were whatever
2718 // value is necessary in order to fit the above forms.
2719 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2720 SmallVector<int, 16> Indices,
2721 SelectionDAG &DAG) {
2722 assert((Indices.size() % 2) == 0);
2726 const auto &Begin = Indices.begin();
2727 const auto &End = Indices.end();
2729 // Check even elements are taken from the even elements of one half or the
2730 // other and pick an operand accordingly.
2731 if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2732 Wt = Op->getOperand(0);
2733 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2734 Wt = Op->getOperand(1);
2738 // Check odd elements are taken from the even elements of one half or the
2739 // other and pick an operand accordingly.
2740 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2741 Ws = Op->getOperand(0);
2742 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2743 Ws = Op->getOperand(1);
2747 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2750 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2752 // ILVOD interleaves the odd elements from each vector.
2754 // It is possible to lower into ILVOD when the mask consists of two of the
2755 // following forms interleaved:
2757 // <n+1, n+3, n+5, ...>
2758 // where n is the number of elements in the vector.
2760 // <1, 1, 3, 3, 5, 5, ...>
2761 // <1, n+1, 3, n+3, 5, n+5, ...>
2763 // When undef's appear in the mask they are treated as if they were whatever
2764 // value is necessary in order to fit the above forms.
2765 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2766 SmallVector<int, 16> Indices,
2767 SelectionDAG &DAG) {
2768 assert((Indices.size() % 2) == 0);
2772 const auto &Begin = Indices.begin();
2773 const auto &End = Indices.end();
2775 // Check even elements are taken from the odd elements of one half or the
2776 // other and pick an operand accordingly.
2777 if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2778 Wt = Op->getOperand(0);
2779 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2780 Wt = Op->getOperand(1);
2784 // Check odd elements are taken from the odd elements of one half or the
2785 // other and pick an operand accordingly.
2786 if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2787 Ws = Op->getOperand(0);
2788 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2789 Ws = Op->getOperand(1);
2793 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2796 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2798 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2801 // It is possible to lower into ILVR when the mask consists of two of the
2802 // following forms interleaved:
2804 // <n, n+1, n+2, ...>
2805 // where n is the number of elements in the vector.
2807 // <0, 0, 1, 1, 2, 2, ...>
2808 // <0, n, 1, n+1, 2, n+2, ...>
2810 // When undef's appear in the mask they are treated as if they were whatever
2811 // value is necessary in order to fit the above forms.
2812 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2813 SmallVector<int, 16> Indices,
2814 SelectionDAG &DAG) {
2815 assert((Indices.size() % 2) == 0);
2819 const auto &Begin = Indices.begin();
2820 const auto &End = Indices.end();
2822 // Check even elements are taken from the right (lowest-indexed) elements of
2823 // one half or the other and pick an operand accordingly.
2824 if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2825 Wt = Op->getOperand(0);
2826 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2827 Wt = Op->getOperand(1);
2831 // Check odd elements are taken from the right (lowest-indexed) elements of
2832 // one half or the other and pick an operand accordingly.
2833 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2834 Ws = Op->getOperand(0);
2835 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2836 Ws = Op->getOperand(1);
2840 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2843 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2845 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2848 // It is possible to lower into ILVL when the mask consists of two of the
2849 // following forms interleaved:
2850 // <x, x+1, x+2, ...>
2851 // <n+x, n+x+1, n+x+2, ...>
2852 // where n is the number of elements in the vector and x is half n.
2854 // <x, x, x+1, x+1, x+2, x+2, ...>
2855 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2857 // When undef's appear in the mask they are treated as if they were whatever
2858 // value is necessary in order to fit the above forms.
2859 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2860 SmallVector<int, 16> Indices,
2861 SelectionDAG &DAG) {
2862 assert((Indices.size() % 2) == 0);
2864 unsigned HalfSize = Indices.size() / 2;
2867 const auto &Begin = Indices.begin();
2868 const auto &End = Indices.end();
2870 // Check even elements are taken from the left (highest-indexed) elements of
2871 // one half or the other and pick an operand accordingly.
2872 if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2873 Wt = Op->getOperand(0);
2874 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2875 Wt = Op->getOperand(1);
2879 // Check odd elements are taken from the left (highest-indexed) elements of
2880 // one half or the other and pick an operand accordingly.
2881 if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2882 Ws = Op->getOperand(0);
2883 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2885 Ws = Op->getOperand(1);
2889 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2892 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2894 // PCKEV copies the even elements of each vector into the result vector.
2896 // It is possible to lower into PCKEV when the mask consists of two of the
2897 // following forms concatenated:
2899 // <n, n+2, n+4, ...>
2900 // where n is the number of elements in the vector.
2902 // <0, 2, 4, ..., 0, 2, 4, ...>
2903 // <0, 2, 4, ..., n, n+2, n+4, ...>
2905 // When undef's appear in the mask they are treated as if they were whatever
2906 // value is necessary in order to fit the above forms.
2907 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2908 SmallVector<int, 16> Indices,
2909 SelectionDAG &DAG) {
2910 assert((Indices.size() % 2) == 0);
2914 const auto &Begin = Indices.begin();
2915 const auto &Mid = Indices.begin() + Indices.size() / 2;
2916 const auto &End = Indices.end();
2918 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2919 Wt = Op->getOperand(0);
2920 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2921 Wt = Op->getOperand(1);
2925 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2926 Ws = Op->getOperand(0);
2927 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2928 Ws = Op->getOperand(1);
2932 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2935 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2937 // PCKOD copies the odd elements of each vector into the result vector.
2939 // It is possible to lower into PCKOD when the mask consists of two of the
2940 // following forms concatenated:
2942 // <n+1, n+3, n+5, ...>
2943 // where n is the number of elements in the vector.
2945 // <1, 3, 5, ..., 1, 3, 5, ...>
2946 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2948 // When undef's appear in the mask they are treated as if they were whatever
2949 // value is necessary in order to fit the above forms.
2950 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2951 SmallVector<int, 16> Indices,
2952 SelectionDAG &DAG) {
2953 assert((Indices.size() % 2) == 0);
2957 const auto &Begin = Indices.begin();
2958 const auto &Mid = Indices.begin() + Indices.size() / 2;
2959 const auto &End = Indices.end();
2961 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2962 Wt = Op->getOperand(0);
2963 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2964 Wt = Op->getOperand(1);
2968 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2969 Ws = Op->getOperand(0);
2970 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2971 Ws = Op->getOperand(1);
2975 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2978 // Lower VECTOR_SHUFFLE into VSHF.
2980 // This mostly consists of converting the shuffle indices in Indices into a
2981 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2982 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2983 // if the type is v8i16 and all the indices are less than 8 then the second
2984 // operand is unused and can be replaced with anything. We choose to replace it
2985 // with the used operand since this reduces the number of instructions overall.
2986 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2987 SmallVector<int, 16> Indices,
2988 SelectionDAG &DAG) {
2989 SmallVector<SDValue, 16> Ops;
2992 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2993 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2994 bool Using1stVec = false;
2995 bool Using2ndVec = false;
2997 int ResTyNumElts = ResTy.getVectorNumElements();
2999 for (int i = 0; i < ResTyNumElts; ++i) {
3000 // Idx == -1 means UNDEF
3001 int Idx = Indices[i];
3003 if (0 <= Idx && Idx < ResTyNumElts)
3005 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
3009 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
3011 Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
3013 SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
3015 if (Using1stVec && Using2ndVec) {
3016 Op0 = Op->getOperand(0);
3017 Op1 = Op->getOperand(1);
3018 } else if (Using1stVec)
3019 Op0 = Op1 = Op->getOperand(0);
3020 else if (Using2ndVec)
3021 Op0 = Op1 = Op->getOperand(1);
3023 llvm_unreachable("shuffle vector mask references neither vector operand?");
3025 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
3026 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
3027 // VSHF concatenates the vectors in a bitwise fashion:
3028 // <0b00, 0b01> + <0b10, 0b11> ->
3029 // 0b0100 + 0b1110 -> 0b01001110
3030 // <0b10, 0b11, 0b00, 0b01>
3031 // We must therefore swap the operands to get the correct result.
3032 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
3035 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
3036 // indices in the shuffle.
3037 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
3038 SelectionDAG &DAG) const {
3039 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
3040 EVT ResTy = Op->getValueType(0);
3042 if (!ResTy.is128BitVector())
3045 int ResTyNumElts = ResTy.getVectorNumElements();
3046 SmallVector<int, 16> Indices;
3048 for (int i = 0; i < ResTyNumElts; ++i)
3049 Indices.push_back(Node->getMaskElt(i));
3051 // splati.[bhwd] is preferable to the others but is matched from
3053 if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
3054 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
3056 if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
3058 if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
3060 if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
3062 if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
3064 if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
3066 if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
3068 if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
3070 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
3074 MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
3075 MachineBasicBlock *BB) const {
3077 // bposge32_pseudo $vr0
3087 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
3089 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3090 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3091 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3092 DebugLoc DL = MI.getDebugLoc();
3093 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3094 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
3095 MachineFunction *F = BB->getParent();
3096 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3097 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3098 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3101 F->insert(It, Sink);
3103 // Transfer the remainder of BB and its successor edges to Sink.
3104 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3106 Sink->transferSuccessorsAndUpdatePHIs(BB);
3109 BB->addSuccessor(FBB);
3110 BB->addSuccessor(TBB);
3111 FBB->addSuccessor(Sink);
3112 TBB->addSuccessor(Sink);
3114 // Insert the real bposge32 instruction to $BB.
3115 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3116 // Insert the real bposge32c instruction to $BB.
3117 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3120 unsigned VR2 = RegInfo.createVirtualRegister(RC);
3121 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3122 .addReg(Mips::ZERO).addImm(0);
3123 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3126 unsigned VR1 = RegInfo.createVirtualRegister(RC);
3127 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3128 .addReg(Mips::ZERO).addImm(1);
3130 // Insert phi function to $Sink.
3131 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3132 MI.getOperand(0).getReg())
3138 MI.eraseFromParent(); // The pseudo instruction is gone now.
3142 MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
3143 MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
3145 // vany_nonzero $rd, $ws
3156 // $rd = phi($rd1, $fbb, $rd2, $tbb)
3158 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3159 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3160 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3161 DebugLoc DL = MI.getDebugLoc();
3162 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3163 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
3164 MachineFunction *F = BB->getParent();
3165 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3166 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3167 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3170 F->insert(It, Sink);
3172 // Transfer the remainder of BB and its successor edges to Sink.
3173 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3175 Sink->transferSuccessorsAndUpdatePHIs(BB);
3178 BB->addSuccessor(FBB);
3179 BB->addSuccessor(TBB);
3180 FBB->addSuccessor(Sink);
3181 TBB->addSuccessor(Sink);
3183 // Insert the real bnz.b instruction to $BB.
3184 BuildMI(BB, DL, TII->get(BranchOp))
3185 .addReg(MI.getOperand(1).getReg())
3189 unsigned RD1 = RegInfo.createVirtualRegister(RC);
3190 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3191 .addReg(Mips::ZERO).addImm(0);
3192 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3195 unsigned RD2 = RegInfo.createVirtualRegister(RC);
3196 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3197 .addReg(Mips::ZERO).addImm(1);
3199 // Insert phi function to $Sink.
3200 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3201 MI.getOperand(0).getReg())
3207 MI.eraseFromParent(); // The pseudo instruction is gone now.
3211 // Emit the COPY_FW pseudo instruction.
3213 // copy_fw_pseudo $fd, $ws, n
3215 // copy_u_w $rt, $ws, $n
3218 // When n is zero, the equivalent operation can be performed with (potentially)
3219 // zero instructions due to register overlaps. This optimization is never valid
3220 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3222 MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3223 MachineBasicBlock *BB) const {
3224 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3225 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3226 DebugLoc DL = MI.getDebugLoc();
3227 unsigned Fd = MI.getOperand(0).getReg();
3228 unsigned Ws = MI.getOperand(1).getReg();
3229 unsigned Lane = MI.getOperand(2).getImm();
3233 if (!Subtarget.useOddSPReg()) {
3234 // We must copy to an even-numbered MSA register so that the
3235 // single-precision sub-register is also guaranteed to be even-numbered.
3236 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3238 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3241 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3243 unsigned Wt = RegInfo.createVirtualRegister(
3244 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3245 &Mips::MSA128WEvensRegClass);
3247 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3248 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3251 MI.eraseFromParent(); // The pseudo instruction is gone now.
3255 // Emit the COPY_FD pseudo instruction.
3257 // copy_fd_pseudo $fd, $ws, n
3259 // splati.d $wt, $ws, $n
3260 // copy $fd, $wt:sub_64
3262 // When n is zero, the equivalent operation can be performed with (potentially)
3263 // zero instructions due to register overlaps. This optimization is always
3264 // valid because FR=1 mode which is the only supported mode in MSA.
3266 MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3267 MachineBasicBlock *BB) const {
3268 assert(Subtarget.isFP64bit());
3270 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3271 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3272 unsigned Fd = MI.getOperand(0).getReg();
3273 unsigned Ws = MI.getOperand(1).getReg();
3274 unsigned Lane = MI.getOperand(2).getImm() * 2;
3275 DebugLoc DL = MI.getDebugLoc();
3278 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3280 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3282 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3283 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3286 MI.eraseFromParent(); // The pseudo instruction is gone now.
3290 // Emit the INSERT_FW pseudo instruction.
3292 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3294 // subreg_to_reg $wt:sub_lo, $fs
3295 // insve_w $wd[$n], $wd_in, $wt[0]
3297 MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
3298 MachineBasicBlock *BB) const {
3299 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3300 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3301 DebugLoc DL = MI.getDebugLoc();
3302 unsigned Wd = MI.getOperand(0).getReg();
3303 unsigned Wd_in = MI.getOperand(1).getReg();
3304 unsigned Lane = MI.getOperand(2).getImm();
3305 unsigned Fs = MI.getOperand(3).getReg();
3306 unsigned Wt = RegInfo.createVirtualRegister(
3307 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3308 &Mips::MSA128WEvensRegClass);
3310 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3313 .addImm(Mips::sub_lo);
3314 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3320 MI.eraseFromParent(); // The pseudo instruction is gone now.
3324 // Emit the INSERT_FD pseudo instruction.
3326 // insert_fd_pseudo $wd, $fs, n
3328 // subreg_to_reg $wt:sub_64, $fs
3329 // insve_d $wd[$n], $wd_in, $wt[0]
3331 MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
3332 MachineBasicBlock *BB) const {
3333 assert(Subtarget.isFP64bit());
3335 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3336 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3337 DebugLoc DL = MI.getDebugLoc();
3338 unsigned Wd = MI.getOperand(0).getReg();
3339 unsigned Wd_in = MI.getOperand(1).getReg();
3340 unsigned Lane = MI.getOperand(2).getImm();
3341 unsigned Fs = MI.getOperand(3).getReg();
3342 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3344 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3347 .addImm(Mips::sub_64);
3348 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3354 MI.eraseFromParent(); // The pseudo instruction is gone now.
3358 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3361 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3363 // (SLL $lanetmp1, $lane, <log2size)
3364 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3365 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3366 // (NEG $lanetmp2, $lanetmp1)
3367 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3369 // For floating point:
3370 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3372 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3373 // (SLL $lanetmp1, $lane, <log2size)
3374 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3375 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3376 // (NEG $lanetmp2, $lanetmp1)
3377 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3378 MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3379 MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3381 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3382 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3383 DebugLoc DL = MI.getDebugLoc();
3384 unsigned Wd = MI.getOperand(0).getReg();
3385 unsigned SrcVecReg = MI.getOperand(1).getReg();
3386 unsigned LaneReg = MI.getOperand(2).getReg();
3387 unsigned SrcValReg = MI.getOperand(3).getReg();
3389 const TargetRegisterClass *VecRC = nullptr;
3390 // FIXME: This should be true for N32 too.
3391 const TargetRegisterClass *GPRRC =
3392 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3393 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3394 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3395 unsigned EltLog2Size;
3396 unsigned InsertOp = 0;
3397 unsigned InsveOp = 0;
3398 switch (EltSizeInBytes) {
3400 llvm_unreachable("Unexpected size");
3403 InsertOp = Mips::INSERT_B;
3404 InsveOp = Mips::INSVE_B;
3405 VecRC = &Mips::MSA128BRegClass;
3409 InsertOp = Mips::INSERT_H;
3410 InsveOp = Mips::INSVE_H;
3411 VecRC = &Mips::MSA128HRegClass;
3415 InsertOp = Mips::INSERT_W;
3416 InsveOp = Mips::INSVE_W;
3417 VecRC = &Mips::MSA128WRegClass;
3421 InsertOp = Mips::INSERT_D;
3422 InsveOp = Mips::INSVE_D;
3423 VecRC = &Mips::MSA128DRegClass;
3428 unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3429 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3432 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3436 // Convert the lane index into a byte index
3437 if (EltSizeInBytes != 1) {
3438 unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3439 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3441 .addImm(EltLog2Size);
3445 // Rotate bytes around so that the desired lane is element zero
3446 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3447 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3450 .addReg(LaneReg, 0, SubRegIdx);
3452 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3454 // Use insve.df to insert to element zero
3455 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3461 // Use insert.df to insert to element zero
3462 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3468 // Rotate elements the rest of the way for a full rotation.
3469 // sld.df inteprets $rt modulo the number of columns so we only need to negate
3470 // the lane index to do this.
3471 unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3472 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3474 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3476 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3479 .addReg(LaneTmp2, 0, SubRegIdx);
3481 MI.eraseFromParent(); // The pseudo instruction is gone now.
3485 // Emit the FILL_FW pseudo instruction.
3487 // fill_fw_pseudo $wd, $fs
3489 // implicit_def $wt1
3490 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3491 // splati.w $wd, $wt2[0]
3493 MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
3494 MachineBasicBlock *BB) const {
3495 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3496 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3497 DebugLoc DL = MI.getDebugLoc();
3498 unsigned Wd = MI.getOperand(0).getReg();
3499 unsigned Fs = MI.getOperand(1).getReg();
3500 unsigned Wt1 = RegInfo.createVirtualRegister(
3501 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3502 : &Mips::MSA128WEvensRegClass);
3503 unsigned Wt2 = RegInfo.createVirtualRegister(
3504 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3505 : &Mips::MSA128WEvensRegClass);
3507 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3508 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3511 .addImm(Mips::sub_lo);
3512 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3514 MI.eraseFromParent(); // The pseudo instruction is gone now.
3518 // Emit the FILL_FD pseudo instruction.
3520 // fill_fd_pseudo $wd, $fs
3522 // implicit_def $wt1
3523 // insert_subreg $wt2:subreg_64, $wt1, $fs
3524 // splati.d $wd, $wt2[0]
3526 MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
3527 MachineBasicBlock *BB) const {
3528 assert(Subtarget.isFP64bit());
3530 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3531 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3532 DebugLoc DL = MI.getDebugLoc();
3533 unsigned Wd = MI.getOperand(0).getReg();
3534 unsigned Fs = MI.getOperand(1).getReg();
3535 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3536 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3538 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3539 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3542 .addImm(Mips::sub_64);
3543 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3545 MI.eraseFromParent(); // The pseudo instruction is gone now.
3549 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3552 // STF16 MSA128F16:$wd, mem_simm10:$addr
3554 // copy_u.h $rtemp,$wd[0]
3557 // Safety: We can't use st.h & co as they would over write the memory after
3558 // the destination. It would require half floats be allocated 16 bytes(!) of
3561 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3562 MachineBasicBlock *BB) const {
3564 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3565 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3566 DebugLoc DL = MI.getDebugLoc();
3567 unsigned Ws = MI.getOperand(0).getReg();
3568 unsigned Rt = MI.getOperand(1).getReg();
3569 const MachineMemOperand &MMO = **MI.memoperands_begin();
3570 unsigned Imm = MMO.getOffset();
3572 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3573 // spill and reload can expand as a GPR64 operand. Examine the
3574 // operand in detail and default to ABI.
3575 const TargetRegisterClass *RC =
3576 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3577 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3578 : &Mips::GPR64RegClass);
3579 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3580 unsigned Rs = RegInfo.createVirtualRegister(RC);
3582 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3583 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3587 .addMemOperand(BB->getParent()->getMachineMemOperand(
3588 &MMO, MMO.getOffset(), MMO.getSize()));
3590 MI.eraseFromParent();
3594 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3596 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3599 // fill.h $wd, $rtemp
3601 // Safety: We can't use ld.h & co as they over-read from the source.
3602 // Additionally, if the address is not modulo 16, 2 cases can occur:
3603 // a) Segmentation fault as the load instruction reads from a memory page
3604 // memory it's not supposed to.
3605 // b) The load crosses an implementation specific boundary, requiring OS
3609 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3610 MachineBasicBlock *BB) const {
3612 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3613 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3614 DebugLoc DL = MI.getDebugLoc();
3615 unsigned Wd = MI.getOperand(0).getReg();
3617 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3618 // spill and reload can expand as a GPR64 operand. Examine the
3619 // operand in detail and default to ABI.
3620 const TargetRegisterClass *RC =
3621 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3622 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3623 : &Mips::GPR64RegClass);
3625 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3626 unsigned Rt = RegInfo.createVirtualRegister(RC);
3628 MachineInstrBuilder MIB =
3629 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3630 for (unsigned i = 1; i < MI.getNumOperands(); i++)
3631 MIB.add(MI.getOperand(i));
3633 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3635 MI.eraseFromParent();
3639 // Emit the FPROUND_PSEUDO instruction.
3641 // Round an FGR64Opnd, FGR32Opnd to an f16.
3643 // Safety: Cycle the operand through the GPRs so the result always ends up
3644 // the correct MSA register.
3646 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3647 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3648 // (which they can be, as the MSA registers are defined to alias the
3649 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3650 // the correct register class. That requires operands be tie-able across
3651 // register classes which have a sub/super register class relationship.
3655 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3658 // fill.w $rtemp, $wtemp
3659 // fexdo.w $wd, $wtemp, $wtemp
3661 // For FPG64Opnd on mips32r2+:
3663 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3666 // fill.w $rtemp, $wtemp
3667 // mfhc1 $rtemp2, $fs
3668 // insert.w $wtemp[1], $rtemp2
3669 // insert.w $wtemp[3], $rtemp2
3670 // fexdo.w $wtemp2, $wtemp, $wtemp
3671 // fexdo.h $wd, $temp2, $temp2
3673 // For FGR64Opnd on mips64r2+:
3675 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3677 // dmfc1 $rtemp, $fs
3678 // fill.d $rtemp, $wtemp
3679 // fexdo.w $wtemp2, $wtemp, $wtemp
3680 // fexdo.h $wd, $wtemp2, $wtemp2
3682 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3683 // undef bits are "just right" and the exception enable bits are
3684 // set. By using fill.w to replicate $fs into all elements over
3685 // insert.w for one element, we avoid that potiential case. If
3686 // fexdo.[hw] causes an exception in, the exception is valid and it
3687 // occurs for all elements.
3690 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3691 MachineBasicBlock *BB,
3692 bool IsFGR64) const {
3694 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3695 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3697 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3699 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3701 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3702 DebugLoc DL = MI.getDebugLoc();
3703 unsigned Wd = MI.getOperand(0).getReg();
3704 unsigned Fs = MI.getOperand(1).getReg();
3706 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3707 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3708 const TargetRegisterClass *GPRRC =
3709 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3710 unsigned MFC1Opc = IsFGR64onMips64 ? Mips::DMFC1 : Mips::MFC1;
3711 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3713 // Perform the register class copy as mentioned above.
3714 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3715 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3716 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3717 unsigned WPHI = Wtemp;
3719 if (!Subtarget.hasMips64() && IsFGR64) {
3720 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3721 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3722 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3723 unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3724 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3728 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3736 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3737 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3743 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3745 MI.eraseFromParent();
3749 // Emit the FPEXTEND_PSEUDO instruction.
3751 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3753 // Safety: Cycle the result through the GPRs so the result always ends up
3754 // the correct floating point register.
3756 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3757 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3758 // (which they can be, as the MSA registers are defined to alias the
3759 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3760 // the correct register class. That requires operands be tie-able across
3761 // register classes which have a sub/super register class relationship. I
3766 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3768 // fexupr.w $wtemp, $ws
3769 // copy_s.w $rtemp, $ws[0]
3772 // For FGR64Opnd on Mips64:
3774 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3776 // fexupr.w $wtemp, $ws
3777 // fexupr.d $wtemp2, $wtemp
3778 // copy_s.d $rtemp, $wtemp2s[0]
3779 // dmtc1 $rtemp, $fd
3781 // For FGR64Opnd on Mips32:
3783 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3785 // fexupr.w $wtemp, $ws
3786 // fexupr.d $wtemp2, $wtemp
3787 // copy_s.w $rtemp, $wtemp2[0]
3788 // mtc1 $rtemp, $ftemp
3789 // copy_s.w $rtemp2, $wtemp2[1]
3790 // $fd = mthc1 $rtemp2, $ftemp
3793 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3794 MachineBasicBlock *BB,
3795 bool IsFGR64) const {
3797 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3798 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3800 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3802 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3803 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3805 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3806 DebugLoc DL = MI.getDebugLoc();
3807 unsigned Fd = MI.getOperand(0).getReg();
3808 unsigned Ws = MI.getOperand(1).getReg();
3810 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3811 const TargetRegisterClass *GPRRC =
3812 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3813 unsigned MTC1Opc = IsFGR64onMips64 ? Mips::DMTC1 : Mips::MTC1;
3814 unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3816 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3817 unsigned WPHI = Wtemp;
3819 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3821 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3822 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3825 // Perform the safety regclass copy mentioned above.
3826 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3827 unsigned FPRPHI = IsFGR64onMips32
3828 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3830 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3831 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3833 if (IsFGR64onMips32) {
3834 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3835 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3838 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3843 MI.eraseFromParent();
3847 // Emit the FEXP2_W_1 pseudo instructions.
3849 // fexp2_w_1_pseudo $wd, $wt
3852 // fexp2.w $wd, $ws, $wt
3854 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
3855 MachineBasicBlock *BB) const {
3856 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3857 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3858 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3859 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3860 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3861 DebugLoc DL = MI.getDebugLoc();
3863 // Splat 1.0 into a vector
3864 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3865 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3867 // Emit 1.0 * fexp2(Wt)
3868 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3870 .addReg(MI.getOperand(1).getReg());
3872 MI.eraseFromParent(); // The pseudo instruction is gone now.
3876 // Emit the FEXP2_D_1 pseudo instructions.
3878 // fexp2_d_1_pseudo $wd, $wt
3881 // fexp2.d $wd, $ws, $wt
3883 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
3884 MachineBasicBlock *BB) const {
3885 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3886 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3887 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3888 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3889 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3890 DebugLoc DL = MI.getDebugLoc();
3892 // Splat 1.0 into a vector
3893 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3894 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3896 // Emit 1.0 * fexp2(Wt)
3897 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3899 .addReg(MI.getOperand(1).getReg());
3901 MI.eraseFromParent(); // The pseudo instruction is gone now.