1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEISelLowering.h"
15 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/ISDOpcodes.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/MachineValueType.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 #include "llvm/CodeGen/TargetInstrInfo.h"
35 #include "llvm/CodeGen/TargetSubtargetInfo.h"
36 #include "llvm/CodeGen/ValueTypes.h"
37 #include "llvm/IR/DebugLoc.h"
38 #include "llvm/IR/Intrinsics.h"
39 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/raw_ostream.h"
53 #define DEBUG_TYPE "mips-isel"
56 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
57 cl::desc("MIPS: permit tail calls."), cl::init(false));
59 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
60 cl::desc("Expand double precision loads and "
61 "stores to their single precision "
64 MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
65 const MipsSubtarget &STI)
66 : MipsTargetLowering(TM, STI) {
67 // Set up the register classes
68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
70 if (Subtarget.isGP64bit())
71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
73 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
74 // Expand all truncating stores and extending loads.
75 for (MVT VT0 : MVT::vector_valuetypes()) {
76 for (MVT VT1 : MVT::vector_valuetypes()) {
77 setTruncStoreAction(VT0, VT1, Expand);
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
85 if (Subtarget.hasDSP()) {
86 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
88 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
89 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
91 // Expand all builtin opcodes.
92 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
93 setOperationAction(Opc, VecTys[i], Expand);
95 setOperationAction(ISD::ADD, VecTys[i], Legal);
96 setOperationAction(ISD::SUB, VecTys[i], Legal);
97 setOperationAction(ISD::LOAD, VecTys[i], Legal);
98 setOperationAction(ISD::STORE, VecTys[i], Legal);
99 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
102 setTargetDAGCombine(ISD::SHL);
103 setTargetDAGCombine(ISD::SRA);
104 setTargetDAGCombine(ISD::SRL);
105 setTargetDAGCombine(ISD::SETCC);
106 setTargetDAGCombine(ISD::VSELECT);
109 if (Subtarget.hasDSPR2())
110 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
112 if (Subtarget.hasMSA()) {
113 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
114 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
115 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
116 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
117 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
118 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
119 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
121 // f16 is a storage-only type, always promote it to f32.
122 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
123 setOperationAction(ISD::SETCC, MVT::f16, Promote);
124 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
125 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
126 setOperationAction(ISD::SELECT, MVT::f16, Promote);
127 setOperationAction(ISD::FADD, MVT::f16, Promote);
128 setOperationAction(ISD::FSUB, MVT::f16, Promote);
129 setOperationAction(ISD::FMUL, MVT::f16, Promote);
130 setOperationAction(ISD::FDIV, MVT::f16, Promote);
131 setOperationAction(ISD::FREM, MVT::f16, Promote);
132 setOperationAction(ISD::FMA, MVT::f16, Promote);
133 setOperationAction(ISD::FNEG, MVT::f16, Promote);
134 setOperationAction(ISD::FABS, MVT::f16, Promote);
135 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
136 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
137 setOperationAction(ISD::FCOS, MVT::f16, Promote);
138 setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote);
139 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
140 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
141 setOperationAction(ISD::FPOW, MVT::f16, Promote);
142 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
143 setOperationAction(ISD::FRINT, MVT::f16, Promote);
144 setOperationAction(ISD::FSIN, MVT::f16, Promote);
145 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
146 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
147 setOperationAction(ISD::FEXP, MVT::f16, Promote);
148 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
149 setOperationAction(ISD::FLOG, MVT::f16, Promote);
150 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
151 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
152 setOperationAction(ISD::FROUND, MVT::f16, Promote);
153 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
154 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
155 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
156 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
157 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
159 setTargetDAGCombine(ISD::AND);
160 setTargetDAGCombine(ISD::OR);
161 setTargetDAGCombine(ISD::SRA);
162 setTargetDAGCombine(ISD::VSELECT);
163 setTargetDAGCombine(ISD::XOR);
166 if (!Subtarget.useSoftFloat()) {
167 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
169 // When dealing with single precision only, use libcalls
170 if (!Subtarget.isSingleFloat()) {
171 if (Subtarget.isFP64bit())
172 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
174 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
178 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
179 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
180 setOperationAction(ISD::MULHS, MVT::i32, Custom);
181 setOperationAction(ISD::MULHU, MVT::i32, Custom);
183 if (Subtarget.hasCnMips())
184 setOperationAction(ISD::MUL, MVT::i64, Legal);
185 else if (Subtarget.isGP64bit())
186 setOperationAction(ISD::MUL, MVT::i64, Custom);
188 if (Subtarget.isGP64bit()) {
189 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
190 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
191 setOperationAction(ISD::MULHS, MVT::i64, Custom);
192 setOperationAction(ISD::MULHU, MVT::i64, Custom);
193 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
194 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
197 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
198 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
200 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
201 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
202 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
203 setOperationAction(ISD::LOAD, MVT::i32, Custom);
204 setOperationAction(ISD::STORE, MVT::i32, Custom);
206 setTargetDAGCombine(ISD::MUL);
208 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
209 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
210 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
213 setOperationAction(ISD::LOAD, MVT::f64, Custom);
214 setOperationAction(ISD::STORE, MVT::f64, Custom);
217 if (Subtarget.hasMips32r6()) {
218 // MIPS32r6 replaces the accumulator-based multiplies with a three register
220 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
221 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
222 setOperationAction(ISD::MUL, MVT::i32, Legal);
223 setOperationAction(ISD::MULHS, MVT::i32, Legal);
224 setOperationAction(ISD::MULHU, MVT::i32, Legal);
226 // MIPS32r6 replaces the accumulator-based division/remainder with separate
227 // three register division and remainder instructions.
228 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
229 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
230 setOperationAction(ISD::SDIV, MVT::i32, Legal);
231 setOperationAction(ISD::UDIV, MVT::i32, Legal);
232 setOperationAction(ISD::SREM, MVT::i32, Legal);
233 setOperationAction(ISD::UREM, MVT::i32, Legal);
235 // MIPS32r6 replaces conditional moves with an equivalent that removes the
236 // need for three GPR read ports.
237 setOperationAction(ISD::SETCC, MVT::i32, Legal);
238 setOperationAction(ISD::SELECT, MVT::i32, Legal);
239 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
241 setOperationAction(ISD::SETCC, MVT::f32, Legal);
242 setOperationAction(ISD::SELECT, MVT::f32, Legal);
243 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
245 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
246 setOperationAction(ISD::SETCC, MVT::f64, Legal);
247 setOperationAction(ISD::SELECT, MVT::f64, Custom);
248 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
250 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
252 // Floating point > and >= are supported via < and <=
253 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
254 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
255 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
256 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
258 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
259 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
260 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
261 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
264 if (Subtarget.hasMips64r6()) {
265 // MIPS64r6 replaces the accumulator-based multiplies with a three register
267 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
268 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Legal);
270 setOperationAction(ISD::MULHS, MVT::i64, Legal);
271 setOperationAction(ISD::MULHU, MVT::i64, Legal);
273 // MIPS32r6 replaces the accumulator-based division/remainder with separate
274 // three register division and remainder instructions.
275 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
276 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
277 setOperationAction(ISD::SDIV, MVT::i64, Legal);
278 setOperationAction(ISD::UDIV, MVT::i64, Legal);
279 setOperationAction(ISD::SREM, MVT::i64, Legal);
280 setOperationAction(ISD::UREM, MVT::i64, Legal);
282 // MIPS64r6 replaces conditional moves with an equivalent that removes the
283 // need for three GPR read ports.
284 setOperationAction(ISD::SETCC, MVT::i64, Legal);
285 setOperationAction(ISD::SELECT, MVT::i64, Legal);
286 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
289 computeRegisterProperties(Subtarget.getRegisterInfo());
292 const MipsTargetLowering *
293 llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
294 const MipsSubtarget &STI) {
295 return new MipsSETargetLowering(TM, STI);
298 const TargetRegisterClass *
299 MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
300 if (VT == MVT::Untyped)
301 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
303 return TargetLowering::getRepRegClassFor(VT);
306 // Enable MSA support for the given integer type and Register class.
307 void MipsSETargetLowering::
308 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
309 addRegisterClass(Ty, RC);
311 // Expand all builtin opcodes.
312 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
313 setOperationAction(Opc, Ty, Expand);
315 setOperationAction(ISD::BITCAST, Ty, Legal);
316 setOperationAction(ISD::LOAD, Ty, Legal);
317 setOperationAction(ISD::STORE, Ty, Legal);
318 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
319 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
320 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
322 setOperationAction(ISD::ADD, Ty, Legal);
323 setOperationAction(ISD::AND, Ty, Legal);
324 setOperationAction(ISD::CTLZ, Ty, Legal);
325 setOperationAction(ISD::CTPOP, Ty, Legal);
326 setOperationAction(ISD::MUL, Ty, Legal);
327 setOperationAction(ISD::OR, Ty, Legal);
328 setOperationAction(ISD::SDIV, Ty, Legal);
329 setOperationAction(ISD::SREM, Ty, Legal);
330 setOperationAction(ISD::SHL, Ty, Legal);
331 setOperationAction(ISD::SRA, Ty, Legal);
332 setOperationAction(ISD::SRL, Ty, Legal);
333 setOperationAction(ISD::SUB, Ty, Legal);
334 setOperationAction(ISD::UDIV, Ty, Legal);
335 setOperationAction(ISD::UREM, Ty, Legal);
336 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
337 setOperationAction(ISD::VSELECT, Ty, Legal);
338 setOperationAction(ISD::XOR, Ty, Legal);
340 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
341 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
342 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
343 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
344 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
347 setOperationAction(ISD::SETCC, Ty, Legal);
348 setCondCodeAction(ISD::SETNE, Ty, Expand);
349 setCondCodeAction(ISD::SETGE, Ty, Expand);
350 setCondCodeAction(ISD::SETGT, Ty, Expand);
351 setCondCodeAction(ISD::SETUGE, Ty, Expand);
352 setCondCodeAction(ISD::SETUGT, Ty, Expand);
355 // Enable MSA support for the given floating-point type and Register class.
356 void MipsSETargetLowering::
357 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
358 addRegisterClass(Ty, RC);
360 // Expand all builtin opcodes.
361 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
362 setOperationAction(Opc, Ty, Expand);
364 setOperationAction(ISD::LOAD, Ty, Legal);
365 setOperationAction(ISD::STORE, Ty, Legal);
366 setOperationAction(ISD::BITCAST, Ty, Legal);
367 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
368 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
369 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
371 if (Ty != MVT::v8f16) {
372 setOperationAction(ISD::FABS, Ty, Legal);
373 setOperationAction(ISD::FADD, Ty, Legal);
374 setOperationAction(ISD::FDIV, Ty, Legal);
375 setOperationAction(ISD::FEXP2, Ty, Legal);
376 setOperationAction(ISD::FLOG2, Ty, Legal);
377 setOperationAction(ISD::FMA, Ty, Legal);
378 setOperationAction(ISD::FMUL, Ty, Legal);
379 setOperationAction(ISD::FRINT, Ty, Legal);
380 setOperationAction(ISD::FSQRT, Ty, Legal);
381 setOperationAction(ISD::FSUB, Ty, Legal);
382 setOperationAction(ISD::VSELECT, Ty, Legal);
384 setOperationAction(ISD::SETCC, Ty, Legal);
385 setCondCodeAction(ISD::SETOGE, Ty, Expand);
386 setCondCodeAction(ISD::SETOGT, Ty, Expand);
387 setCondCodeAction(ISD::SETUGE, Ty, Expand);
388 setCondCodeAction(ISD::SETUGT, Ty, Expand);
389 setCondCodeAction(ISD::SETGE, Ty, Expand);
390 setCondCodeAction(ISD::SETGT, Ty, Expand);
394 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
395 if(!Subtarget.hasMips32r6())
396 return MipsTargetLowering::LowerOperation(Op, DAG);
398 EVT ResTy = Op->getValueType(0);
401 // Although MTC1_D64 takes an i32 and writes an f64, the upper 32 bits of the
402 // floating point register are undefined. Not really an issue as sel.d, which
403 // is produced from an FSELECT node, only looks at bit 0.
404 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
405 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
410 MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
414 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
416 if (Subtarget.systemSupportsUnalignedAccess()) {
417 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
418 // implementation defined whether this is handled by hardware, software, or
419 // a hybrid of the two but it's expected that most implementations will
420 // handle the majority of cases in hardware.
437 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
438 SelectionDAG &DAG) const {
439 switch(Op.getOpcode()) {
440 case ISD::LOAD: return lowerLOAD(Op, DAG);
441 case ISD::STORE: return lowerSTORE(Op, DAG);
442 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
443 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
444 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
445 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
446 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
447 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
448 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
450 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
451 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
452 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
453 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
454 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
455 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
456 case ISD::SELECT: return lowerSELECT(Op, DAG);
459 return MipsTargetLowering::LowerOperation(Op, DAG);
462 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
464 // Performs the following transformations:
465 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
466 // sign/zero-extension is completely overwritten by the new one performed by
468 // - Removes redundant zero extensions performed by an ISD::AND.
469 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
470 TargetLowering::DAGCombinerInfo &DCI,
471 const MipsSubtarget &Subtarget) {
472 if (!Subtarget.hasMSA())
475 SDValue Op0 = N->getOperand(0);
476 SDValue Op1 = N->getOperand(1);
477 unsigned Op0Opcode = Op0->getOpcode();
479 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
480 // where $d + 1 == 2^n and n == 32
481 // or $d + 1 == 2^n and n <= 32 and ZExt
482 // -> (MipsVExtractZExt $a, $b, $c)
483 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
484 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
485 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
490 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
492 if (Log2IfPositive <= 0)
493 return SDValue(); // Mask+1 is not a power of 2
495 SDValue Op0Op2 = Op0->getOperand(2);
496 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
497 unsigned ExtendTySize = ExtendTy.getSizeInBits();
498 unsigned Log2 = Log2IfPositive;
500 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
501 Log2 == ExtendTySize) {
502 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
503 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
505 makeArrayRef(Ops, Op0->getNumOperands()));
512 // Determine if the specified node is a constant vector splat.
514 // Returns true and sets Imm if:
515 // * N is a ISD::BUILD_VECTOR representing a constant splat
517 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
518 // differences are that it assumes the MSA has already been checked and the
519 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
520 // must not be in order for binsri.d to be selectable).
521 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
522 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
527 APInt SplatValue, SplatUndef;
528 unsigned SplatBitSize;
531 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
540 // Test whether the given node is an all-ones build_vector.
541 static bool isVectorAllOnes(SDValue N) {
542 // Look through bitcasts. Endianness doesn't matter because we are looking
543 // for an all-ones value.
544 if (N->getOpcode() == ISD::BITCAST)
545 N = N->getOperand(0);
547 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
552 APInt SplatValue, SplatUndef;
553 unsigned SplatBitSize;
556 // Endianness doesn't matter in this context because we are looking for
557 // an all-ones value.
558 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
559 return SplatValue.isAllOnesValue();
564 // Test whether N is the bitwise inverse of OfNode.
565 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
566 if (N->getOpcode() != ISD::XOR)
569 if (isVectorAllOnes(N->getOperand(0)))
570 return N->getOperand(1) == OfNode;
572 if (isVectorAllOnes(N->getOperand(1)))
573 return N->getOperand(0) == OfNode;
578 // Perform combines where ISD::OR is the root node.
580 // Performs the following transformations:
581 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
582 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
584 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
585 TargetLowering::DAGCombinerInfo &DCI,
586 const MipsSubtarget &Subtarget) {
587 if (!Subtarget.hasMSA())
590 EVT Ty = N->getValueType(0);
592 if (!Ty.is128BitVector())
595 SDValue Op0 = N->getOperand(0);
596 SDValue Op1 = N->getOperand(1);
598 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
599 SDValue Op0Op0 = Op0->getOperand(0);
600 SDValue Op0Op1 = Op0->getOperand(1);
601 SDValue Op1Op0 = Op1->getOperand(0);
602 SDValue Op1Op1 = Op1->getOperand(1);
603 bool IsLittleEndian = !Subtarget.isLittle();
605 SDValue IfSet, IfClr, Cond;
606 bool IsConstantMask = false;
609 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
610 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
612 // IfClr will be set if we find a valid match.
613 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
617 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
618 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
620 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
621 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
624 IsConstantMask = true;
627 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
628 // thing again using this mask.
629 // IfClr will be set if we find a valid match.
630 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
634 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
635 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
637 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
638 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
641 IsConstantMask = true;
644 // If IfClr is not yet set, try looking for a non-constant match.
645 // IfClr will be set if we find a valid match amongst the eight
647 if (!IfClr.getNode()) {
648 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
652 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
656 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
660 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
664 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
668 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
672 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
676 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
683 // At this point, IfClr will be set if we have a valid match.
684 if (!IfClr.getNode())
687 assert(Cond.getNode() && IfSet.getNode());
689 // Fold degenerate cases.
690 if (IsConstantMask) {
691 if (Mask.isAllOnesValue())
697 // Transform the DAG into an equivalent VSELECT.
698 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
704 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT,
705 EVT ShiftTy, SelectionDAG &DAG) {
708 return DAG.getConstant(0, DL, VT);
714 // If c is power of 2, return (shl x, log2(c)).
716 return DAG.getNode(ISD::SHL, DL, VT, X,
717 DAG.getConstant(C.logBase2(), DL, ShiftTy));
719 unsigned BitWidth = C.getBitWidth();
720 APInt Floor = APInt(BitWidth, 1) << C.logBase2();
721 APInt Ceil = C.isNegative() ? APInt(BitWidth, 0) :
722 APInt(BitWidth, 1) << C.ceilLogBase2();
724 // If |c - floor_c| <= |c - ceil_c|,
725 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
726 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
727 if ((C - Floor).ule(Ceil - C)) {
728 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
729 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
730 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
733 // If |c - floor_c| > |c - ceil_c|,
734 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
735 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
736 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
737 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
740 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
741 const TargetLowering::DAGCombinerInfo &DCI,
742 const MipsSETargetLowering *TL) {
743 EVT VT = N->getValueType(0);
745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
747 return genConstMult(N->getOperand(0), C->getAPIntValue(), SDLoc(N), VT,
748 TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
751 return SDValue(N, 0);
754 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
756 const MipsSubtarget &Subtarget) {
757 // See if this is a vector splat immediate node.
758 APInt SplatValue, SplatUndef;
759 unsigned SplatBitSize;
761 unsigned EltSize = Ty.getScalarSizeInBits();
762 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
764 if (!Subtarget.hasDSP())
768 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
769 EltSize, !Subtarget.isLittle()) ||
770 (SplatBitSize != EltSize) ||
771 (SplatValue.getZExtValue() >= EltSize))
775 return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
776 DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
779 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
780 TargetLowering::DAGCombinerInfo &DCI,
781 const MipsSubtarget &Subtarget) {
782 EVT Ty = N->getValueType(0);
784 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
787 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
790 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
791 // constant splats into MipsISD::SHRA_DSP for DSPr2.
793 // Performs the following transformations:
794 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
795 // sign/zero-extension is completely overwritten by the new one performed by
796 // the ISD::SRA and ISD::SHL nodes.
797 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
800 // See performDSPShiftCombine for more information about the transformation
802 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
803 TargetLowering::DAGCombinerInfo &DCI,
804 const MipsSubtarget &Subtarget) {
805 EVT Ty = N->getValueType(0);
807 if (Subtarget.hasMSA()) {
808 SDValue Op0 = N->getOperand(0);
809 SDValue Op1 = N->getOperand(1);
811 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
812 // where $d + sizeof($c) == 32
813 // or $d + sizeof($c) <= 32 and SExt
814 // -> (MipsVExtractSExt $a, $b, $c)
815 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
816 SDValue Op0Op0 = Op0->getOperand(0);
817 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
822 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
823 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
826 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
827 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
829 if (TotalBits == 32 ||
830 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
832 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
833 Op0Op0->getOperand(2) };
834 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
836 makeArrayRef(Ops, Op0Op0->getNumOperands()));
841 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
844 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
848 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
849 TargetLowering::DAGCombinerInfo &DCI,
850 const MipsSubtarget &Subtarget) {
851 EVT Ty = N->getValueType(0);
853 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
856 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
859 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
860 bool IsV216 = (Ty == MVT::v2i16);
864 case ISD::SETNE: return true;
868 case ISD::SETGE: return IsV216;
872 case ISD::SETUGE: return !IsV216;
873 default: return false;
877 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
878 EVT Ty = N->getValueType(0);
880 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
883 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
886 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
887 N->getOperand(1), N->getOperand(2));
890 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
891 EVT Ty = N->getValueType(0);
893 if (Ty.is128BitVector() && Ty.isInteger()) {
894 // Try the following combines:
895 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
896 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
897 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
898 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
899 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
900 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
901 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
902 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
903 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
904 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
906 SDValue Op0 = N->getOperand(0);
908 if (Op0->getOpcode() != ISD::SETCC)
911 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
914 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
916 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
921 SDValue Op1 = N->getOperand(1);
922 SDValue Op2 = N->getOperand(2);
923 SDValue Op0Op0 = Op0->getOperand(0);
924 SDValue Op0Op1 = Op0->getOperand(1);
926 if (Op1 == Op0Op0 && Op2 == Op0Op1)
927 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
929 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
930 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
932 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
933 SDValue SetCC = N->getOperand(0);
935 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
938 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
939 SetCC.getOperand(0), SetCC.getOperand(1),
940 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
946 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
947 const MipsSubtarget &Subtarget) {
948 EVT Ty = N->getValueType(0);
950 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
951 // Try the following combines:
952 // (xor (or $a, $b), (build_vector allones))
953 // (xor (or $a, $b), (bitcast (build_vector allones)))
954 SDValue Op0 = N->getOperand(0);
955 SDValue Op1 = N->getOperand(1);
958 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
960 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
965 if (NotOp->getOpcode() == ISD::OR)
966 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
967 NotOp->getOperand(1));
974 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
975 SelectionDAG &DAG = DCI.DAG;
978 switch (N->getOpcode()) {
980 Val = performANDCombine(N, DAG, DCI, Subtarget);
983 Val = performORCombine(N, DAG, DCI, Subtarget);
986 return performMULCombine(N, DAG, DCI, this);
988 Val = performSHLCombine(N, DAG, DCI, Subtarget);
991 return performSRACombine(N, DAG, DCI, Subtarget);
993 return performSRLCombine(N, DAG, DCI, Subtarget);
995 return performVSELECTCombine(N, DAG);
997 Val = performXORCombine(N, DAG, Subtarget);
1000 Val = performSETCCCombine(N, DAG);
1004 if (Val.getNode()) {
1005 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1006 N->printrWithDepth(dbgs(), &DAG);
1007 dbgs() << "\n=> \n";
1008 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1013 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1017 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1018 MachineBasicBlock *BB) const {
1019 switch (MI.getOpcode()) {
1021 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1022 case Mips::BPOSGE32_PSEUDO:
1023 return emitBPOSGE32(MI, BB);
1024 case Mips::SNZ_B_PSEUDO:
1025 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1026 case Mips::SNZ_H_PSEUDO:
1027 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1028 case Mips::SNZ_W_PSEUDO:
1029 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1030 case Mips::SNZ_D_PSEUDO:
1031 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1032 case Mips::SNZ_V_PSEUDO:
1033 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1034 case Mips::SZ_B_PSEUDO:
1035 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1036 case Mips::SZ_H_PSEUDO:
1037 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1038 case Mips::SZ_W_PSEUDO:
1039 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1040 case Mips::SZ_D_PSEUDO:
1041 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1042 case Mips::SZ_V_PSEUDO:
1043 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1044 case Mips::COPY_FW_PSEUDO:
1045 return emitCOPY_FW(MI, BB);
1046 case Mips::COPY_FD_PSEUDO:
1047 return emitCOPY_FD(MI, BB);
1048 case Mips::INSERT_FW_PSEUDO:
1049 return emitINSERT_FW(MI, BB);
1050 case Mips::INSERT_FD_PSEUDO:
1051 return emitINSERT_FD(MI, BB);
1052 case Mips::INSERT_B_VIDX_PSEUDO:
1053 case Mips::INSERT_B_VIDX64_PSEUDO:
1054 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1055 case Mips::INSERT_H_VIDX_PSEUDO:
1056 case Mips::INSERT_H_VIDX64_PSEUDO:
1057 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1058 case Mips::INSERT_W_VIDX_PSEUDO:
1059 case Mips::INSERT_W_VIDX64_PSEUDO:
1060 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1061 case Mips::INSERT_D_VIDX_PSEUDO:
1062 case Mips::INSERT_D_VIDX64_PSEUDO:
1063 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1064 case Mips::INSERT_FW_VIDX_PSEUDO:
1065 case Mips::INSERT_FW_VIDX64_PSEUDO:
1066 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1067 case Mips::INSERT_FD_VIDX_PSEUDO:
1068 case Mips::INSERT_FD_VIDX64_PSEUDO:
1069 return emitINSERT_DF_VIDX(MI, BB, 8, true);
1070 case Mips::FILL_FW_PSEUDO:
1071 return emitFILL_FW(MI, BB);
1072 case Mips::FILL_FD_PSEUDO:
1073 return emitFILL_FD(MI, BB);
1074 case Mips::FEXP2_W_1_PSEUDO:
1075 return emitFEXP2_W_1(MI, BB);
1076 case Mips::FEXP2_D_1_PSEUDO:
1077 return emitFEXP2_D_1(MI, BB);
1079 return emitST_F16_PSEUDO(MI, BB);
1081 return emitLD_F16_PSEUDO(MI, BB);
1082 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1083 return emitFPEXTEND_PSEUDO(MI, BB, false);
1084 case Mips::MSA_FP_ROUND_W_PSEUDO:
1085 return emitFPROUND_PSEUDO(MI, BB, false);
1086 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1087 return emitFPEXTEND_PSEUDO(MI, BB, true);
1088 case Mips::MSA_FP_ROUND_D_PSEUDO:
1089 return emitFPROUND_PSEUDO(MI, BB, true);
1093 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1094 const CCState &CCInfo, unsigned NextStackOffset,
1095 const MipsFunctionInfo &FI) const {
1096 if (!UseMipsTailCalls)
1099 // Exception has to be cleared with eret.
1103 // Return false if either the callee or caller has a byval argument.
1104 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1107 // Return true if the callee's argument area is no larger than the
1109 return NextStackOffset <= FI.getIncomingArgSize();
1112 void MipsSETargetLowering::
1113 getOpndList(SmallVectorImpl<SDValue> &Ops,
1114 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
1115 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1116 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1117 SDValue Chain) const {
1118 Ops.push_back(Callee);
1119 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1120 InternalLinkage, IsCallReloc, CLI, Callee,
1124 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1125 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1127 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1128 return MipsTargetLowering::lowerLOAD(Op, DAG);
1130 // Replace a double precision load with two i32 loads and a buildpair64.
1132 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1133 EVT PtrVT = Ptr.getValueType();
1135 // i32 load from lower address.
1136 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1137 Nd.getAlignment(), Nd.getMemOperand()->getFlags());
1139 // i32 load from higher address.
1140 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1141 SDValue Hi = DAG.getLoad(
1142 MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1143 std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
1145 if (!Subtarget.isLittle())
1148 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1149 SDValue Ops[2] = {BP, Hi.getValue(1)};
1150 return DAG.getMergeValues(Ops, DL);
1153 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1154 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1156 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1157 return MipsTargetLowering::lowerSTORE(Op, DAG);
1159 // Replace a double precision store with two extractelement64s and i32 stores.
1161 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1162 EVT PtrVT = Ptr.getValueType();
1163 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1164 Val, DAG.getConstant(0, DL, MVT::i32));
1165 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1166 Val, DAG.getConstant(1, DL, MVT::i32));
1168 if (!Subtarget.isLittle())
1171 // i32 store to lower address.
1173 DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1174 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1176 // i32 store to higher address.
1177 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1178 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1179 std::min(Nd.getAlignment(), 4U),
1180 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
1183 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1184 bool HasLo, bool HasHi,
1185 SelectionDAG &DAG) const {
1186 // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1187 assert(!Subtarget.hasMips32r6());
1189 EVT Ty = Op.getOperand(0).getValueType();
1191 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1192 Op.getOperand(0), Op.getOperand(1));
1196 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1198 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1200 if (!HasLo || !HasHi)
1201 return HasLo ? Lo : Hi;
1203 SDValue Vals[] = { Lo, Hi };
1204 return DAG.getMergeValues(Vals, DL);
1207 static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) {
1208 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1209 DAG.getConstant(0, DL, MVT::i32));
1210 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1211 DAG.getConstant(1, DL, MVT::i32));
1212 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1215 static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
1216 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1217 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1218 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1221 // This function expands mips intrinsic nodes which have 64-bit input operands
1222 // or output values.
1224 // out64 = intrinsic-node in64
1226 // lo = copy (extract-element (in64, 0))
1227 // hi = copy (extract-element (in64, 1))
1228 // mips-specific-node
1231 // out64 = merge-values (v0, v1)
1233 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1235 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1236 SmallVector<SDValue, 3> Ops;
1239 // See if Op has a chain input.
1241 Ops.push_back(Op->getOperand(OpNo++));
1243 // The next operand is the intrinsic opcode.
1244 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1246 // See if the next operand has type i64.
1247 SDValue Opnd = Op->getOperand(++OpNo), In64;
1249 if (Opnd.getValueType() == MVT::i64)
1250 In64 = initAccumulator(Opnd, DL, DAG);
1252 Ops.push_back(Opnd);
1254 // Push the remaining operands.
1255 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1256 Ops.push_back(Op->getOperand(OpNo));
1258 // Add In64 to the end of the list.
1260 Ops.push_back(In64);
1263 SmallVector<EVT, 2> ResTys;
1265 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1267 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1270 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1271 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1276 assert(Val->getValueType(1) == MVT::Other);
1277 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1278 return DAG.getMergeValues(Vals, DL);
1281 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1282 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1284 SDValue Vec = Op->getOperand(1);
1285 SDValue Idx = Op->getOperand(2);
1286 EVT ResTy = Op->getValueType(0);
1287 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1289 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1290 DAG.getValueType(EltTy));
1295 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1296 EVT ResVecTy = Op->getValueType(0);
1297 EVT ViaVecTy = ResVecTy;
1298 bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1301 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1302 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1304 SDValue LaneA = Op->getOperand(OpNr);
1307 if (ResVecTy == MVT::v2i64) {
1308 LaneB = DAG.getConstant(0, DL, MVT::i32);
1309 ViaVecTy = MVT::v4i32;
1311 std::swap(LaneA, LaneB);
1315 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1316 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1318 SDValue Result = DAG.getBuildVector(
1319 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1321 if (ViaVecTy != ResVecTy) {
1322 SDValue One = DAG.getConstant(1, DL, ViaVecTy);
1323 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy,
1324 DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One));
1330 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1331 bool IsSigned = false) {
1332 return DAG.getConstant(
1333 APInt(Op->getValueType(0).getScalarType().getSizeInBits(),
1334 Op->getConstantOperandVal(ImmOp), IsSigned),
1335 SDLoc(Op), Op->getValueType(0));
1338 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1339 bool BigEndian, SelectionDAG &DAG) {
1340 EVT ViaVecTy = VecTy;
1341 SDValue SplatValueA = SplatValue;
1342 SDValue SplatValueB = SplatValue;
1343 SDLoc DL(SplatValue);
1345 if (VecTy == MVT::v2i64) {
1346 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1347 ViaVecTy = MVT::v4i32;
1349 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1350 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1351 DAG.getConstant(32, DL, MVT::i32));
1352 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1355 // We currently hold the parts in little endian order. Swap them if
1358 std::swap(SplatValueA, SplatValueB);
1360 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1361 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1362 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1363 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1365 SDValue Result = DAG.getBuildVector(
1366 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1368 if (VecTy != ViaVecTy)
1369 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1374 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1375 unsigned Opc, SDValue Imm,
1377 EVT VecTy = Op->getValueType(0);
1381 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1383 if (VecTy == MVT::v2i64) {
1384 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1385 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1387 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1389 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
1392 std::swap(BitImmLoOp, BitImmHiOp);
1394 Exp2Imm = DAG.getNode(
1395 ISD::BITCAST, DL, MVT::v2i64,
1396 DAG.getBuildVector(MVT::v4i32, DL,
1397 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1401 if (!Exp2Imm.getNode()) {
1402 // We couldnt constant fold, do a vector shift instead
1404 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1405 // only values 0-63 are valid.
1406 if (VecTy == MVT::v2i64)
1407 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1409 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1411 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1415 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1418 static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG) {
1420 EVT ResTy = Op->getValueType(0);
1421 SDValue Vec = Op->getOperand(2);
1422 bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1423 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1424 SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
1426 SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1428 return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1431 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1432 EVT ResTy = Op->getValueType(0);
1434 SDValue One = DAG.getConstant(1, DL, ResTy);
1435 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1437 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1438 DAG.getNOT(DL, Bit, ResTy));
1441 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1443 EVT ResTy = Op->getValueType(0);
1444 APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1445 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1446 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1448 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1451 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1452 SelectionDAG &DAG) const {
1454 unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1455 switch (Intrinsic) {
1458 case Intrinsic::mips_shilo:
1459 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1460 case Intrinsic::mips_dpau_h_qbl:
1461 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1462 case Intrinsic::mips_dpau_h_qbr:
1463 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1464 case Intrinsic::mips_dpsu_h_qbl:
1465 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1466 case Intrinsic::mips_dpsu_h_qbr:
1467 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1468 case Intrinsic::mips_dpa_w_ph:
1469 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1470 case Intrinsic::mips_dps_w_ph:
1471 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1472 case Intrinsic::mips_dpax_w_ph:
1473 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1474 case Intrinsic::mips_dpsx_w_ph:
1475 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1476 case Intrinsic::mips_mulsa_w_ph:
1477 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1478 case Intrinsic::mips_mult:
1479 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1480 case Intrinsic::mips_multu:
1481 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1482 case Intrinsic::mips_madd:
1483 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1484 case Intrinsic::mips_maddu:
1485 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1486 case Intrinsic::mips_msub:
1487 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1488 case Intrinsic::mips_msubu:
1489 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1490 case Intrinsic::mips_addv_b:
1491 case Intrinsic::mips_addv_h:
1492 case Intrinsic::mips_addv_w:
1493 case Intrinsic::mips_addv_d:
1494 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1496 case Intrinsic::mips_addvi_b:
1497 case Intrinsic::mips_addvi_h:
1498 case Intrinsic::mips_addvi_w:
1499 case Intrinsic::mips_addvi_d:
1500 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1501 lowerMSASplatImm(Op, 2, DAG));
1502 case Intrinsic::mips_and_v:
1503 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1505 case Intrinsic::mips_andi_b:
1506 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1507 lowerMSASplatImm(Op, 2, DAG));
1508 case Intrinsic::mips_bclr_b:
1509 case Intrinsic::mips_bclr_h:
1510 case Intrinsic::mips_bclr_w:
1511 case Intrinsic::mips_bclr_d:
1512 return lowerMSABitClear(Op, DAG);
1513 case Intrinsic::mips_bclri_b:
1514 case Intrinsic::mips_bclri_h:
1515 case Intrinsic::mips_bclri_w:
1516 case Intrinsic::mips_bclri_d:
1517 return lowerMSABitClearImm(Op, DAG);
1518 case Intrinsic::mips_binsli_b:
1519 case Intrinsic::mips_binsli_h:
1520 case Intrinsic::mips_binsli_w:
1521 case Intrinsic::mips_binsli_d: {
1522 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1523 EVT VecTy = Op->getValueType(0);
1524 EVT EltTy = VecTy.getVectorElementType();
1525 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1526 report_fatal_error("Immediate out of range");
1527 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1528 Op->getConstantOperandVal(3) + 1);
1529 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1530 DAG.getConstant(Mask, DL, VecTy, true),
1531 Op->getOperand(2), Op->getOperand(1));
1533 case Intrinsic::mips_binsri_b:
1534 case Intrinsic::mips_binsri_h:
1535 case Intrinsic::mips_binsri_w:
1536 case Intrinsic::mips_binsri_d: {
1537 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1538 EVT VecTy = Op->getValueType(0);
1539 EVT EltTy = VecTy.getVectorElementType();
1540 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1541 report_fatal_error("Immediate out of range");
1542 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1543 Op->getConstantOperandVal(3) + 1);
1544 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1545 DAG.getConstant(Mask, DL, VecTy, true),
1546 Op->getOperand(2), Op->getOperand(1));
1548 case Intrinsic::mips_bmnz_v:
1549 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1550 Op->getOperand(2), Op->getOperand(1));
1551 case Intrinsic::mips_bmnzi_b:
1552 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1553 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1555 case Intrinsic::mips_bmz_v:
1556 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1557 Op->getOperand(1), Op->getOperand(2));
1558 case Intrinsic::mips_bmzi_b:
1559 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1560 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1562 case Intrinsic::mips_bneg_b:
1563 case Intrinsic::mips_bneg_h:
1564 case Intrinsic::mips_bneg_w:
1565 case Intrinsic::mips_bneg_d: {
1566 EVT VecTy = Op->getValueType(0);
1567 SDValue One = DAG.getConstant(1, DL, VecTy);
1569 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1570 DAG.getNode(ISD::SHL, DL, VecTy, One,
1571 truncateVecElts(Op, DAG)));
1573 case Intrinsic::mips_bnegi_b:
1574 case Intrinsic::mips_bnegi_h:
1575 case Intrinsic::mips_bnegi_w:
1576 case Intrinsic::mips_bnegi_d:
1577 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1578 !Subtarget.isLittle());
1579 case Intrinsic::mips_bnz_b:
1580 case Intrinsic::mips_bnz_h:
1581 case Intrinsic::mips_bnz_w:
1582 case Intrinsic::mips_bnz_d:
1583 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1585 case Intrinsic::mips_bnz_v:
1586 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1588 case Intrinsic::mips_bsel_v:
1589 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1590 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1591 Op->getOperand(1), Op->getOperand(3),
1593 case Intrinsic::mips_bseli_b:
1594 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1595 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1596 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1598 case Intrinsic::mips_bset_b:
1599 case Intrinsic::mips_bset_h:
1600 case Intrinsic::mips_bset_w:
1601 case Intrinsic::mips_bset_d: {
1602 EVT VecTy = Op->getValueType(0);
1603 SDValue One = DAG.getConstant(1, DL, VecTy);
1605 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1606 DAG.getNode(ISD::SHL, DL, VecTy, One,
1607 truncateVecElts(Op, DAG)));
1609 case Intrinsic::mips_bseti_b:
1610 case Intrinsic::mips_bseti_h:
1611 case Intrinsic::mips_bseti_w:
1612 case Intrinsic::mips_bseti_d:
1613 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1614 !Subtarget.isLittle());
1615 case Intrinsic::mips_bz_b:
1616 case Intrinsic::mips_bz_h:
1617 case Intrinsic::mips_bz_w:
1618 case Intrinsic::mips_bz_d:
1619 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1621 case Intrinsic::mips_bz_v:
1622 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1624 case Intrinsic::mips_ceq_b:
1625 case Intrinsic::mips_ceq_h:
1626 case Intrinsic::mips_ceq_w:
1627 case Intrinsic::mips_ceq_d:
1628 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1629 Op->getOperand(2), ISD::SETEQ);
1630 case Intrinsic::mips_ceqi_b:
1631 case Intrinsic::mips_ceqi_h:
1632 case Intrinsic::mips_ceqi_w:
1633 case Intrinsic::mips_ceqi_d:
1634 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1635 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
1636 case Intrinsic::mips_cle_s_b:
1637 case Intrinsic::mips_cle_s_h:
1638 case Intrinsic::mips_cle_s_w:
1639 case Intrinsic::mips_cle_s_d:
1640 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1641 Op->getOperand(2), ISD::SETLE);
1642 case Intrinsic::mips_clei_s_b:
1643 case Intrinsic::mips_clei_s_h:
1644 case Intrinsic::mips_clei_s_w:
1645 case Intrinsic::mips_clei_s_d:
1646 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1647 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
1648 case Intrinsic::mips_cle_u_b:
1649 case Intrinsic::mips_cle_u_h:
1650 case Intrinsic::mips_cle_u_w:
1651 case Intrinsic::mips_cle_u_d:
1652 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1653 Op->getOperand(2), ISD::SETULE);
1654 case Intrinsic::mips_clei_u_b:
1655 case Intrinsic::mips_clei_u_h:
1656 case Intrinsic::mips_clei_u_w:
1657 case Intrinsic::mips_clei_u_d:
1658 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1659 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1660 case Intrinsic::mips_clt_s_b:
1661 case Intrinsic::mips_clt_s_h:
1662 case Intrinsic::mips_clt_s_w:
1663 case Intrinsic::mips_clt_s_d:
1664 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1665 Op->getOperand(2), ISD::SETLT);
1666 case Intrinsic::mips_clti_s_b:
1667 case Intrinsic::mips_clti_s_h:
1668 case Intrinsic::mips_clti_s_w:
1669 case Intrinsic::mips_clti_s_d:
1670 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1671 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
1672 case Intrinsic::mips_clt_u_b:
1673 case Intrinsic::mips_clt_u_h:
1674 case Intrinsic::mips_clt_u_w:
1675 case Intrinsic::mips_clt_u_d:
1676 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1677 Op->getOperand(2), ISD::SETULT);
1678 case Intrinsic::mips_clti_u_b:
1679 case Intrinsic::mips_clti_u_h:
1680 case Intrinsic::mips_clti_u_w:
1681 case Intrinsic::mips_clti_u_d:
1682 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1683 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1684 case Intrinsic::mips_copy_s_b:
1685 case Intrinsic::mips_copy_s_h:
1686 case Intrinsic::mips_copy_s_w:
1687 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1688 case Intrinsic::mips_copy_s_d:
1689 if (Subtarget.hasMips64())
1690 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1691 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1693 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1694 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1695 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1696 Op->getValueType(0), Op->getOperand(1),
1699 case Intrinsic::mips_copy_u_b:
1700 case Intrinsic::mips_copy_u_h:
1701 case Intrinsic::mips_copy_u_w:
1702 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1703 case Intrinsic::mips_copy_u_d:
1704 if (Subtarget.hasMips64())
1705 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1706 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1708 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1709 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1710 // Note: When i64 is illegal, this results in copy_s.w instructions
1711 // instead of copy_u.w instructions. This makes no difference to the
1712 // behaviour since i64 is only illegal when the register file is 32-bit.
1713 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1714 Op->getValueType(0), Op->getOperand(1),
1717 case Intrinsic::mips_div_s_b:
1718 case Intrinsic::mips_div_s_h:
1719 case Intrinsic::mips_div_s_w:
1720 case Intrinsic::mips_div_s_d:
1721 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1723 case Intrinsic::mips_div_u_b:
1724 case Intrinsic::mips_div_u_h:
1725 case Intrinsic::mips_div_u_w:
1726 case Intrinsic::mips_div_u_d:
1727 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1729 case Intrinsic::mips_fadd_w:
1730 case Intrinsic::mips_fadd_d:
1731 // TODO: If intrinsics have fast-math-flags, propagate them.
1732 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1734 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1735 case Intrinsic::mips_fceq_w:
1736 case Intrinsic::mips_fceq_d:
1737 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1738 Op->getOperand(2), ISD::SETOEQ);
1739 case Intrinsic::mips_fcle_w:
1740 case Intrinsic::mips_fcle_d:
1741 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1742 Op->getOperand(2), ISD::SETOLE);
1743 case Intrinsic::mips_fclt_w:
1744 case Intrinsic::mips_fclt_d:
1745 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1746 Op->getOperand(2), ISD::SETOLT);
1747 case Intrinsic::mips_fcne_w:
1748 case Intrinsic::mips_fcne_d:
1749 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1750 Op->getOperand(2), ISD::SETONE);
1751 case Intrinsic::mips_fcor_w:
1752 case Intrinsic::mips_fcor_d:
1753 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1754 Op->getOperand(2), ISD::SETO);
1755 case Intrinsic::mips_fcueq_w:
1756 case Intrinsic::mips_fcueq_d:
1757 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1758 Op->getOperand(2), ISD::SETUEQ);
1759 case Intrinsic::mips_fcule_w:
1760 case Intrinsic::mips_fcule_d:
1761 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1762 Op->getOperand(2), ISD::SETULE);
1763 case Intrinsic::mips_fcult_w:
1764 case Intrinsic::mips_fcult_d:
1765 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1766 Op->getOperand(2), ISD::SETULT);
1767 case Intrinsic::mips_fcun_w:
1768 case Intrinsic::mips_fcun_d:
1769 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1770 Op->getOperand(2), ISD::SETUO);
1771 case Intrinsic::mips_fcune_w:
1772 case Intrinsic::mips_fcune_d:
1773 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1774 Op->getOperand(2), ISD::SETUNE);
1775 case Intrinsic::mips_fdiv_w:
1776 case Intrinsic::mips_fdiv_d:
1777 // TODO: If intrinsics have fast-math-flags, propagate them.
1778 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1780 case Intrinsic::mips_ffint_u_w:
1781 case Intrinsic::mips_ffint_u_d:
1782 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1784 case Intrinsic::mips_ffint_s_w:
1785 case Intrinsic::mips_ffint_s_d:
1786 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1788 case Intrinsic::mips_fill_b:
1789 case Intrinsic::mips_fill_h:
1790 case Intrinsic::mips_fill_w:
1791 case Intrinsic::mips_fill_d: {
1792 EVT ResTy = Op->getValueType(0);
1793 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
1796 // If ResTy is v2i64 then the type legalizer will break this node down into
1797 // an equivalent v4i32.
1798 return DAG.getBuildVector(ResTy, DL, Ops);
1800 case Intrinsic::mips_fexp2_w:
1801 case Intrinsic::mips_fexp2_d: {
1802 // TODO: If intrinsics have fast-math-flags, propagate them.
1803 EVT ResTy = Op->getValueType(0);
1805 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1806 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1808 case Intrinsic::mips_flog2_w:
1809 case Intrinsic::mips_flog2_d:
1810 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1811 case Intrinsic::mips_fmadd_w:
1812 case Intrinsic::mips_fmadd_d:
1813 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1814 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1815 case Intrinsic::mips_fmul_w:
1816 case Intrinsic::mips_fmul_d:
1817 // TODO: If intrinsics have fast-math-flags, propagate them.
1818 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1820 case Intrinsic::mips_fmsub_w:
1821 case Intrinsic::mips_fmsub_d: {
1822 // TODO: If intrinsics have fast-math-flags, propagate them.
1823 EVT ResTy = Op->getValueType(0);
1824 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1825 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1826 Op->getOperand(2), Op->getOperand(3)));
1828 case Intrinsic::mips_frint_w:
1829 case Intrinsic::mips_frint_d:
1830 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1831 case Intrinsic::mips_fsqrt_w:
1832 case Intrinsic::mips_fsqrt_d:
1833 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1834 case Intrinsic::mips_fsub_w:
1835 case Intrinsic::mips_fsub_d:
1836 // TODO: If intrinsics have fast-math-flags, propagate them.
1837 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1839 case Intrinsic::mips_ftrunc_u_w:
1840 case Intrinsic::mips_ftrunc_u_d:
1841 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1843 case Intrinsic::mips_ftrunc_s_w:
1844 case Intrinsic::mips_ftrunc_s_d:
1845 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1847 case Intrinsic::mips_ilvev_b:
1848 case Intrinsic::mips_ilvev_h:
1849 case Intrinsic::mips_ilvev_w:
1850 case Intrinsic::mips_ilvev_d:
1851 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1852 Op->getOperand(1), Op->getOperand(2));
1853 case Intrinsic::mips_ilvl_b:
1854 case Intrinsic::mips_ilvl_h:
1855 case Intrinsic::mips_ilvl_w:
1856 case Intrinsic::mips_ilvl_d:
1857 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1858 Op->getOperand(1), Op->getOperand(2));
1859 case Intrinsic::mips_ilvod_b:
1860 case Intrinsic::mips_ilvod_h:
1861 case Intrinsic::mips_ilvod_w:
1862 case Intrinsic::mips_ilvod_d:
1863 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1864 Op->getOperand(1), Op->getOperand(2));
1865 case Intrinsic::mips_ilvr_b:
1866 case Intrinsic::mips_ilvr_h:
1867 case Intrinsic::mips_ilvr_w:
1868 case Intrinsic::mips_ilvr_d:
1869 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1870 Op->getOperand(1), Op->getOperand(2));
1871 case Intrinsic::mips_insert_b:
1872 case Intrinsic::mips_insert_h:
1873 case Intrinsic::mips_insert_w:
1874 case Intrinsic::mips_insert_d:
1875 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1876 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1877 case Intrinsic::mips_insve_b:
1878 case Intrinsic::mips_insve_h:
1879 case Intrinsic::mips_insve_w:
1880 case Intrinsic::mips_insve_d: {
1881 // Report an error for out of range values.
1883 switch (Intrinsic) {
1884 case Intrinsic::mips_insve_b: Max = 15; break;
1885 case Intrinsic::mips_insve_h: Max = 7; break;
1886 case Intrinsic::mips_insve_w: Max = 3; break;
1887 case Intrinsic::mips_insve_d: Max = 1; break;
1888 default: llvm_unreachable("Unmatched intrinsic");
1890 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1891 if (Value < 0 || Value > Max)
1892 report_fatal_error("Immediate out of range");
1893 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1894 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1895 DAG.getConstant(0, DL, MVT::i32));
1897 case Intrinsic::mips_ldi_b:
1898 case Intrinsic::mips_ldi_h:
1899 case Intrinsic::mips_ldi_w:
1900 case Intrinsic::mips_ldi_d:
1901 return lowerMSASplatImm(Op, 1, DAG, true);
1902 case Intrinsic::mips_lsa:
1903 case Intrinsic::mips_dlsa: {
1904 EVT ResTy = Op->getValueType(0);
1905 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1906 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1907 Op->getOperand(2), Op->getOperand(3)));
1909 case Intrinsic::mips_maddv_b:
1910 case Intrinsic::mips_maddv_h:
1911 case Intrinsic::mips_maddv_w:
1912 case Intrinsic::mips_maddv_d: {
1913 EVT ResTy = Op->getValueType(0);
1914 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1915 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1916 Op->getOperand(2), Op->getOperand(3)));
1918 case Intrinsic::mips_max_s_b:
1919 case Intrinsic::mips_max_s_h:
1920 case Intrinsic::mips_max_s_w:
1921 case Intrinsic::mips_max_s_d:
1922 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1923 Op->getOperand(1), Op->getOperand(2));
1924 case Intrinsic::mips_max_u_b:
1925 case Intrinsic::mips_max_u_h:
1926 case Intrinsic::mips_max_u_w:
1927 case Intrinsic::mips_max_u_d:
1928 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1929 Op->getOperand(1), Op->getOperand(2));
1930 case Intrinsic::mips_maxi_s_b:
1931 case Intrinsic::mips_maxi_s_h:
1932 case Intrinsic::mips_maxi_s_w:
1933 case Intrinsic::mips_maxi_s_d:
1934 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1935 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
1936 case Intrinsic::mips_maxi_u_b:
1937 case Intrinsic::mips_maxi_u_h:
1938 case Intrinsic::mips_maxi_u_w:
1939 case Intrinsic::mips_maxi_u_d:
1940 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1941 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1942 case Intrinsic::mips_min_s_b:
1943 case Intrinsic::mips_min_s_h:
1944 case Intrinsic::mips_min_s_w:
1945 case Intrinsic::mips_min_s_d:
1946 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1947 Op->getOperand(1), Op->getOperand(2));
1948 case Intrinsic::mips_min_u_b:
1949 case Intrinsic::mips_min_u_h:
1950 case Intrinsic::mips_min_u_w:
1951 case Intrinsic::mips_min_u_d:
1952 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1953 Op->getOperand(1), Op->getOperand(2));
1954 case Intrinsic::mips_mini_s_b:
1955 case Intrinsic::mips_mini_s_h:
1956 case Intrinsic::mips_mini_s_w:
1957 case Intrinsic::mips_mini_s_d:
1958 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1959 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
1960 case Intrinsic::mips_mini_u_b:
1961 case Intrinsic::mips_mini_u_h:
1962 case Intrinsic::mips_mini_u_w:
1963 case Intrinsic::mips_mini_u_d:
1964 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1965 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1966 case Intrinsic::mips_mod_s_b:
1967 case Intrinsic::mips_mod_s_h:
1968 case Intrinsic::mips_mod_s_w:
1969 case Intrinsic::mips_mod_s_d:
1970 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1972 case Intrinsic::mips_mod_u_b:
1973 case Intrinsic::mips_mod_u_h:
1974 case Intrinsic::mips_mod_u_w:
1975 case Intrinsic::mips_mod_u_d:
1976 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1978 case Intrinsic::mips_mulv_b:
1979 case Intrinsic::mips_mulv_h:
1980 case Intrinsic::mips_mulv_w:
1981 case Intrinsic::mips_mulv_d:
1982 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1984 case Intrinsic::mips_msubv_b:
1985 case Intrinsic::mips_msubv_h:
1986 case Intrinsic::mips_msubv_w:
1987 case Intrinsic::mips_msubv_d: {
1988 EVT ResTy = Op->getValueType(0);
1989 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1990 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1991 Op->getOperand(2), Op->getOperand(3)));
1993 case Intrinsic::mips_nlzc_b:
1994 case Intrinsic::mips_nlzc_h:
1995 case Intrinsic::mips_nlzc_w:
1996 case Intrinsic::mips_nlzc_d:
1997 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1998 case Intrinsic::mips_nor_v: {
1999 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2000 Op->getOperand(1), Op->getOperand(2));
2001 return DAG.getNOT(DL, Res, Res->getValueType(0));
2003 case Intrinsic::mips_nori_b: {
2004 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2006 lowerMSASplatImm(Op, 2, DAG));
2007 return DAG.getNOT(DL, Res, Res->getValueType(0));
2009 case Intrinsic::mips_or_v:
2010 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2012 case Intrinsic::mips_ori_b:
2013 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2014 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2015 case Intrinsic::mips_pckev_b:
2016 case Intrinsic::mips_pckev_h:
2017 case Intrinsic::mips_pckev_w:
2018 case Intrinsic::mips_pckev_d:
2019 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2020 Op->getOperand(1), Op->getOperand(2));
2021 case Intrinsic::mips_pckod_b:
2022 case Intrinsic::mips_pckod_h:
2023 case Intrinsic::mips_pckod_w:
2024 case Intrinsic::mips_pckod_d:
2025 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2026 Op->getOperand(1), Op->getOperand(2));
2027 case Intrinsic::mips_pcnt_b:
2028 case Intrinsic::mips_pcnt_h:
2029 case Intrinsic::mips_pcnt_w:
2030 case Intrinsic::mips_pcnt_d:
2031 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2032 case Intrinsic::mips_sat_s_b:
2033 case Intrinsic::mips_sat_s_h:
2034 case Intrinsic::mips_sat_s_w:
2035 case Intrinsic::mips_sat_s_d:
2036 case Intrinsic::mips_sat_u_b:
2037 case Intrinsic::mips_sat_u_h:
2038 case Intrinsic::mips_sat_u_w:
2039 case Intrinsic::mips_sat_u_d: {
2040 // Report an error for out of range values.
2042 switch (Intrinsic) {
2043 case Intrinsic::mips_sat_s_b:
2044 case Intrinsic::mips_sat_u_b: Max = 7; break;
2045 case Intrinsic::mips_sat_s_h:
2046 case Intrinsic::mips_sat_u_h: Max = 15; break;
2047 case Intrinsic::mips_sat_s_w:
2048 case Intrinsic::mips_sat_u_w: Max = 31; break;
2049 case Intrinsic::mips_sat_s_d:
2050 case Intrinsic::mips_sat_u_d: Max = 63; break;
2051 default: llvm_unreachable("Unmatched intrinsic");
2053 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2054 if (Value < 0 || Value > Max)
2055 report_fatal_error("Immediate out of range");
2058 case Intrinsic::mips_shf_b:
2059 case Intrinsic::mips_shf_h:
2060 case Intrinsic::mips_shf_w: {
2061 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2062 if (Value < 0 || Value > 255)
2063 report_fatal_error("Immediate out of range");
2064 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2065 Op->getOperand(2), Op->getOperand(1));
2067 case Intrinsic::mips_sldi_b:
2068 case Intrinsic::mips_sldi_h:
2069 case Intrinsic::mips_sldi_w:
2070 case Intrinsic::mips_sldi_d: {
2071 // Report an error for out of range values.
2073 switch (Intrinsic) {
2074 case Intrinsic::mips_sldi_b: Max = 15; break;
2075 case Intrinsic::mips_sldi_h: Max = 7; break;
2076 case Intrinsic::mips_sldi_w: Max = 3; break;
2077 case Intrinsic::mips_sldi_d: Max = 1; break;
2078 default: llvm_unreachable("Unmatched intrinsic");
2080 int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2081 if (Value < 0 || Value > Max)
2082 report_fatal_error("Immediate out of range");
2085 case Intrinsic::mips_sll_b:
2086 case Intrinsic::mips_sll_h:
2087 case Intrinsic::mips_sll_w:
2088 case Intrinsic::mips_sll_d:
2089 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2090 truncateVecElts(Op, DAG));
2091 case Intrinsic::mips_slli_b:
2092 case Intrinsic::mips_slli_h:
2093 case Intrinsic::mips_slli_w:
2094 case Intrinsic::mips_slli_d:
2095 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2096 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2097 case Intrinsic::mips_splat_b:
2098 case Intrinsic::mips_splat_h:
2099 case Intrinsic::mips_splat_w:
2100 case Intrinsic::mips_splat_d:
2101 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2102 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2103 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2104 // Instead we lower to MipsISD::VSHF and match from there.
2105 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2106 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2108 case Intrinsic::mips_splati_b:
2109 case Intrinsic::mips_splati_h:
2110 case Intrinsic::mips_splati_w:
2111 case Intrinsic::mips_splati_d:
2112 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2113 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2115 case Intrinsic::mips_sra_b:
2116 case Intrinsic::mips_sra_h:
2117 case Intrinsic::mips_sra_w:
2118 case Intrinsic::mips_sra_d:
2119 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2120 truncateVecElts(Op, DAG));
2121 case Intrinsic::mips_srai_b:
2122 case Intrinsic::mips_srai_h:
2123 case Intrinsic::mips_srai_w:
2124 case Intrinsic::mips_srai_d:
2125 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2126 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2127 case Intrinsic::mips_srari_b:
2128 case Intrinsic::mips_srari_h:
2129 case Intrinsic::mips_srari_w:
2130 case Intrinsic::mips_srari_d: {
2131 // Report an error for out of range values.
2133 switch (Intrinsic) {
2134 case Intrinsic::mips_srari_b: Max = 7; break;
2135 case Intrinsic::mips_srari_h: Max = 15; break;
2136 case Intrinsic::mips_srari_w: Max = 31; break;
2137 case Intrinsic::mips_srari_d: Max = 63; break;
2138 default: llvm_unreachable("Unmatched intrinsic");
2140 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2141 if (Value < 0 || Value > Max)
2142 report_fatal_error("Immediate out of range");
2145 case Intrinsic::mips_srl_b:
2146 case Intrinsic::mips_srl_h:
2147 case Intrinsic::mips_srl_w:
2148 case Intrinsic::mips_srl_d:
2149 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2150 truncateVecElts(Op, DAG));
2151 case Intrinsic::mips_srli_b:
2152 case Intrinsic::mips_srli_h:
2153 case Intrinsic::mips_srli_w:
2154 case Intrinsic::mips_srli_d:
2155 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2156 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2157 case Intrinsic::mips_srlri_b:
2158 case Intrinsic::mips_srlri_h:
2159 case Intrinsic::mips_srlri_w:
2160 case Intrinsic::mips_srlri_d: {
2161 // Report an error for out of range values.
2163 switch (Intrinsic) {
2164 case Intrinsic::mips_srlri_b: Max = 7; break;
2165 case Intrinsic::mips_srlri_h: Max = 15; break;
2166 case Intrinsic::mips_srlri_w: Max = 31; break;
2167 case Intrinsic::mips_srlri_d: Max = 63; break;
2168 default: llvm_unreachable("Unmatched intrinsic");
2170 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2171 if (Value < 0 || Value > Max)
2172 report_fatal_error("Immediate out of range");
2175 case Intrinsic::mips_subv_b:
2176 case Intrinsic::mips_subv_h:
2177 case Intrinsic::mips_subv_w:
2178 case Intrinsic::mips_subv_d:
2179 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2181 case Intrinsic::mips_subvi_b:
2182 case Intrinsic::mips_subvi_h:
2183 case Intrinsic::mips_subvi_w:
2184 case Intrinsic::mips_subvi_d:
2185 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2186 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2187 case Intrinsic::mips_vshf_b:
2188 case Intrinsic::mips_vshf_h:
2189 case Intrinsic::mips_vshf_w:
2190 case Intrinsic::mips_vshf_d:
2191 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2192 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2193 case Intrinsic::mips_xor_v:
2194 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2196 case Intrinsic::mips_xori_b:
2197 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2198 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2199 case Intrinsic::thread_pointer: {
2200 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2201 return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2206 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2207 const MipsSubtarget &Subtarget) {
2209 SDValue ChainIn = Op->getOperand(0);
2210 SDValue Address = Op->getOperand(2);
2211 SDValue Offset = Op->getOperand(3);
2212 EVT ResTy = Op->getValueType(0);
2213 EVT PtrTy = Address->getValueType(0);
2215 // For N64 addresses have the underlying type MVT::i64. This intrinsic
2216 // however takes an i32 signed constant offset. The actual type of the
2217 // intrinsic is a scaled signed i10.
2218 if (Subtarget.isABI_N64())
2219 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2221 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2222 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2223 /* Alignment = */ 16);
2226 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2227 SelectionDAG &DAG) const {
2228 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2232 case Intrinsic::mips_extp:
2233 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2234 case Intrinsic::mips_extpdp:
2235 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2236 case Intrinsic::mips_extr_w:
2237 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2238 case Intrinsic::mips_extr_r_w:
2239 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2240 case Intrinsic::mips_extr_rs_w:
2241 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2242 case Intrinsic::mips_extr_s_h:
2243 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2244 case Intrinsic::mips_mthlip:
2245 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2246 case Intrinsic::mips_mulsaq_s_w_ph:
2247 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2248 case Intrinsic::mips_maq_s_w_phl:
2249 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2250 case Intrinsic::mips_maq_s_w_phr:
2251 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2252 case Intrinsic::mips_maq_sa_w_phl:
2253 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2254 case Intrinsic::mips_maq_sa_w_phr:
2255 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2256 case Intrinsic::mips_dpaq_s_w_ph:
2257 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2258 case Intrinsic::mips_dpsq_s_w_ph:
2259 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2260 case Intrinsic::mips_dpaq_sa_l_w:
2261 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2262 case Intrinsic::mips_dpsq_sa_l_w:
2263 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2264 case Intrinsic::mips_dpaqx_s_w_ph:
2265 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2266 case Intrinsic::mips_dpaqx_sa_w_ph:
2267 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2268 case Intrinsic::mips_dpsqx_s_w_ph:
2269 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2270 case Intrinsic::mips_dpsqx_sa_w_ph:
2271 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2272 case Intrinsic::mips_ld_b:
2273 case Intrinsic::mips_ld_h:
2274 case Intrinsic::mips_ld_w:
2275 case Intrinsic::mips_ld_d:
2276 return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
2280 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2281 const MipsSubtarget &Subtarget) {
2283 SDValue ChainIn = Op->getOperand(0);
2284 SDValue Value = Op->getOperand(2);
2285 SDValue Address = Op->getOperand(3);
2286 SDValue Offset = Op->getOperand(4);
2287 EVT PtrTy = Address->getValueType(0);
2289 // For N64 addresses have the underlying type MVT::i64. This intrinsic
2290 // however takes an i32 signed constant offset. The actual type of the
2291 // intrinsic is a scaled signed i10.
2292 if (Subtarget.isABI_N64())
2293 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2295 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2297 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2298 /* Alignment = */ 16);
2301 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2302 SelectionDAG &DAG) const {
2303 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2307 case Intrinsic::mips_st_b:
2308 case Intrinsic::mips_st_h:
2309 case Intrinsic::mips_st_w:
2310 case Intrinsic::mips_st_d:
2311 return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
2315 /// \brief Check if the given BuildVectorSDNode is a splat.
2316 /// This method currently relies on DAG nodes being reused when equivalent,
2317 /// so it's possible for this to return false even when isConstantSplat returns
2319 static bool isSplatVector(const BuildVectorSDNode *N) {
2320 unsigned int nOps = N->getNumOperands();
2321 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2323 SDValue Operand0 = N->getOperand(0);
2325 for (unsigned int i = 1; i < nOps; ++i) {
2326 if (N->getOperand(i) != Operand0)
2333 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2335 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2336 // choose to sign-extend but we could have equally chosen zero-extend. The
2337 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2338 // result into this node later (possibly changing it to a zero-extend in the
2340 SDValue MipsSETargetLowering::
2341 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2343 EVT ResTy = Op->getValueType(0);
2344 SDValue Op0 = Op->getOperand(0);
2345 EVT VecTy = Op0->getValueType(0);
2347 if (!VecTy.is128BitVector())
2350 if (ResTy.isInteger()) {
2351 SDValue Op1 = Op->getOperand(1);
2352 EVT EltTy = VecTy.getVectorElementType();
2353 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2354 DAG.getValueType(EltTy));
2360 static bool isConstantOrUndef(const SDValue Op) {
2363 if (isa<ConstantSDNode>(Op))
2365 if (isa<ConstantFPSDNode>(Op))
2370 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2371 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2372 if (isConstantOrUndef(Op->getOperand(i)))
2377 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2380 // Lowers according to the following rules:
2381 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2382 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2384 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2385 // is a power of 2 less than or equal to 64 and the value does not fit into a
2386 // signed 10-bit immediate
2387 // - Non-constant splats are legal as-is.
2388 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2389 // - All others are illegal and must be expanded.
2390 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2391 SelectionDAG &DAG) const {
2392 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2393 EVT ResTy = Op->getValueType(0);
2395 APInt SplatValue, SplatUndef;
2396 unsigned SplatBitSize;
2399 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2402 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2404 !Subtarget.isLittle()) && SplatBitSize <= 64) {
2405 // We can only cope with 8, 16, 32, or 64-bit elements
2406 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2410 // If the value isn't an integer type we will have to bitcast
2411 // from an integer type first. Also, if there are any undefs, we must
2412 // lower them to defined values first.
2413 if (ResTy.isInteger() && !HasAnyUndefs)
2418 switch (SplatBitSize) {
2422 ViaVecTy = MVT::v16i8;
2425 ViaVecTy = MVT::v8i16;
2428 ViaVecTy = MVT::v4i32;
2431 // There's no fill.d to fall back on for 64-bit values
2435 // SelectionDAG::getConstant will promote SplatValue appropriately.
2436 SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
2438 // Bitcast to the type we originally wanted
2439 if (ViaVecTy != ResTy)
2440 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2443 } else if (isSplatVector(Node))
2445 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2446 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2447 // The resulting code is the same length as the expansion, but it doesn't
2448 // use memory operations
2449 EVT ResTy = Node->getValueType(0);
2451 assert(ResTy.isVector());
2453 unsigned NumElts = ResTy.getVectorNumElements();
2454 SDValue Vector = DAG.getUNDEF(ResTy);
2455 for (unsigned i = 0; i < NumElts; ++i) {
2456 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2457 Node->getOperand(i),
2458 DAG.getConstant(i, DL, MVT::i32));
2466 // Lower VECTOR_SHUFFLE into SHF (if possible).
2468 // SHF splits the vector into blocks of four elements, then shuffles these
2469 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2471 // It is therefore possible to lower into SHF when the mask takes the form:
2472 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2473 // When undef's appear they are treated as if they were whatever value is
2474 // necessary in order to fit the above forms.
2477 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2478 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2479 // i32 7, i32 6, i32 5, i32 4>
2481 // (SHF_H $w0, $w1, 27)
2482 // where the 27 comes from:
2483 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2484 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2485 SmallVector<int, 16> Indices,
2486 SelectionDAG &DAG) {
2487 int SHFIndices[4] = { -1, -1, -1, -1 };
2489 if (Indices.size() < 4)
2492 for (unsigned i = 0; i < 4; ++i) {
2493 for (unsigned j = i; j < Indices.size(); j += 4) {
2494 int Idx = Indices[j];
2496 // Convert from vector index to 4-element subvector index
2497 // If an index refers to an element outside of the subvector then give up
2500 if (Idx < 0 || Idx >= 4)
2504 // If the mask has an undef, replace it with the current index.
2505 // Note that it might still be undef if the current index is also undef
2506 if (SHFIndices[i] == -1)
2507 SHFIndices[i] = Idx;
2509 // Check that non-undef values are the same as in the mask. If they
2510 // aren't then give up
2511 if (!(Idx == -1 || Idx == SHFIndices[i]))
2516 // Calculate the immediate. Replace any remaining undefs with zero
2518 for (int i = 3; i >= 0; --i) {
2519 int Idx = SHFIndices[i];
2529 return DAG.getNode(MipsISD::SHF, DL, ResTy,
2530 DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
2533 /// Determine whether a range fits a regular pattern of values.
2534 /// This function accounts for the possibility of jumping over the End iterator.
2535 template <typename ValType>
2537 fitsRegularPattern(typename SmallVectorImpl<ValType>::const_iterator Begin,
2538 unsigned CheckStride,
2539 typename SmallVectorImpl<ValType>::const_iterator End,
2540 ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2544 if (*I != -1 && *I != ExpectedIndex)
2546 ExpectedIndex += ExpectedIndexStride;
2548 // Incrementing past End is undefined behaviour so we must increment one
2549 // step at a time and check for End at each step.
2550 for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2551 ; // Empty loop body.
2556 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2558 // It is a SPLATI when the mask is:
2560 // where x is any valid index.
2562 // When undef's appear in the mask they are treated as if they were whatever
2563 // value is necessary in order to fit the above form.
2564 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2565 SmallVector<int, 16> Indices,
2566 SelectionDAG &DAG) {
2567 assert((Indices.size() % 2) == 0);
2569 int SplatIndex = -1;
2570 for (const auto &V : Indices) {
2577 return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2581 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2583 // ILVEV interleaves the even elements from each vector.
2585 // It is possible to lower into ILVEV when the mask consists of two of the
2586 // following forms interleaved:
2588 // <n, n+2, n+4, ...>
2589 // where n is the number of elements in the vector.
2591 // <0, 0, 2, 2, 4, 4, ...>
2592 // <0, n, 2, n+2, 4, n+4, ...>
2594 // When undef's appear in the mask they are treated as if they were whatever
2595 // value is necessary in order to fit the above forms.
2596 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2597 SmallVector<int, 16> Indices,
2598 SelectionDAG &DAG) {
2599 assert((Indices.size() % 2) == 0);
2603 const auto &Begin = Indices.begin();
2604 const auto &End = Indices.end();
2606 // Check even elements are taken from the even elements of one half or the
2607 // other and pick an operand accordingly.
2608 if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2609 Wt = Op->getOperand(0);
2610 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2611 Wt = Op->getOperand(1);
2615 // Check odd elements are taken from the even elements of one half or the
2616 // other and pick an operand accordingly.
2617 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2618 Ws = Op->getOperand(0);
2619 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2620 Ws = Op->getOperand(1);
2624 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2627 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2629 // ILVOD interleaves the odd elements from each vector.
2631 // It is possible to lower into ILVOD when the mask consists of two of the
2632 // following forms interleaved:
2634 // <n+1, n+3, n+5, ...>
2635 // where n is the number of elements in the vector.
2637 // <1, 1, 3, 3, 5, 5, ...>
2638 // <1, n+1, 3, n+3, 5, n+5, ...>
2640 // When undef's appear in the mask they are treated as if they were whatever
2641 // value is necessary in order to fit the above forms.
2642 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2643 SmallVector<int, 16> Indices,
2644 SelectionDAG &DAG) {
2645 assert((Indices.size() % 2) == 0);
2649 const auto &Begin = Indices.begin();
2650 const auto &End = Indices.end();
2652 // Check even elements are taken from the odd elements of one half or the
2653 // other and pick an operand accordingly.
2654 if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2655 Wt = Op->getOperand(0);
2656 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2657 Wt = Op->getOperand(1);
2661 // Check odd elements are taken from the odd elements of one half or the
2662 // other and pick an operand accordingly.
2663 if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2664 Ws = Op->getOperand(0);
2665 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2666 Ws = Op->getOperand(1);
2670 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2673 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2675 // ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2678 // It is possible to lower into ILVR when the mask consists of two of the
2679 // following forms interleaved:
2681 // <n, n+1, n+2, ...>
2682 // where n is the number of elements in the vector.
2684 // <0, 0, 1, 1, 2, 2, ...>
2685 // <0, n, 1, n+1, 2, n+2, ...>
2687 // When undef's appear in the mask they are treated as if they were whatever
2688 // value is necessary in order to fit the above forms.
2689 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2690 SmallVector<int, 16> Indices,
2691 SelectionDAG &DAG) {
2692 assert((Indices.size() % 2) == 0);
2696 const auto &Begin = Indices.begin();
2697 const auto &End = Indices.end();
2699 // Check even elements are taken from the right (lowest-indexed) elements of
2700 // one half or the other and pick an operand accordingly.
2701 if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2702 Wt = Op->getOperand(0);
2703 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2704 Wt = Op->getOperand(1);
2708 // Check odd elements are taken from the right (lowest-indexed) elements of
2709 // one half or the other and pick an operand accordingly.
2710 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2711 Ws = Op->getOperand(0);
2712 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2713 Ws = Op->getOperand(1);
2717 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2720 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2722 // ILVL interleaves consecutive elements from the left (highest-indexed) half
2725 // It is possible to lower into ILVL when the mask consists of two of the
2726 // following forms interleaved:
2727 // <x, x+1, x+2, ...>
2728 // <n+x, n+x+1, n+x+2, ...>
2729 // where n is the number of elements in the vector and x is half n.
2731 // <x, x, x+1, x+1, x+2, x+2, ...>
2732 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2734 // When undef's appear in the mask they are treated as if they were whatever
2735 // value is necessary in order to fit the above forms.
2736 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2737 SmallVector<int, 16> Indices,
2738 SelectionDAG &DAG) {
2739 assert((Indices.size() % 2) == 0);
2741 unsigned HalfSize = Indices.size() / 2;
2744 const auto &Begin = Indices.begin();
2745 const auto &End = Indices.end();
2747 // Check even elements are taken from the left (highest-indexed) elements of
2748 // one half or the other and pick an operand accordingly.
2749 if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2750 Wt = Op->getOperand(0);
2751 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2752 Wt = Op->getOperand(1);
2756 // Check odd elements are taken from the left (highest-indexed) elements of
2757 // one half or the other and pick an operand accordingly.
2758 if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2759 Ws = Op->getOperand(0);
2760 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2762 Ws = Op->getOperand(1);
2766 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2769 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2771 // PCKEV copies the even elements of each vector into the result vector.
2773 // It is possible to lower into PCKEV when the mask consists of two of the
2774 // following forms concatenated:
2776 // <n, n+2, n+4, ...>
2777 // where n is the number of elements in the vector.
2779 // <0, 2, 4, ..., 0, 2, 4, ...>
2780 // <0, 2, 4, ..., n, n+2, n+4, ...>
2782 // When undef's appear in the mask they are treated as if they were whatever
2783 // value is necessary in order to fit the above forms.
2784 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2785 SmallVector<int, 16> Indices,
2786 SelectionDAG &DAG) {
2787 assert((Indices.size() % 2) == 0);
2791 const auto &Begin = Indices.begin();
2792 const auto &Mid = Indices.begin() + Indices.size() / 2;
2793 const auto &End = Indices.end();
2795 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2796 Wt = Op->getOperand(0);
2797 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2798 Wt = Op->getOperand(1);
2802 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2803 Ws = Op->getOperand(0);
2804 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2805 Ws = Op->getOperand(1);
2809 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2812 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2814 // PCKOD copies the odd elements of each vector into the result vector.
2816 // It is possible to lower into PCKOD when the mask consists of two of the
2817 // following forms concatenated:
2819 // <n+1, n+3, n+5, ...>
2820 // where n is the number of elements in the vector.
2822 // <1, 3, 5, ..., 1, 3, 5, ...>
2823 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2825 // When undef's appear in the mask they are treated as if they were whatever
2826 // value is necessary in order to fit the above forms.
2827 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2828 SmallVector<int, 16> Indices,
2829 SelectionDAG &DAG) {
2830 assert((Indices.size() % 2) == 0);
2834 const auto &Begin = Indices.begin();
2835 const auto &Mid = Indices.begin() + Indices.size() / 2;
2836 const auto &End = Indices.end();
2838 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2839 Wt = Op->getOperand(0);
2840 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2841 Wt = Op->getOperand(1);
2845 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2846 Ws = Op->getOperand(0);
2847 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2848 Ws = Op->getOperand(1);
2852 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2855 // Lower VECTOR_SHUFFLE into VSHF.
2857 // This mostly consists of converting the shuffle indices in Indices into a
2858 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2859 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2860 // if the type is v8i16 and all the indices are less than 8 then the second
2861 // operand is unused and can be replaced with anything. We choose to replace it
2862 // with the used operand since this reduces the number of instructions overall.
2863 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2864 SmallVector<int, 16> Indices,
2865 SelectionDAG &DAG) {
2866 SmallVector<SDValue, 16> Ops;
2869 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2870 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2871 bool Using1stVec = false;
2872 bool Using2ndVec = false;
2874 int ResTyNumElts = ResTy.getVectorNumElements();
2876 for (int i = 0; i < ResTyNumElts; ++i) {
2877 // Idx == -1 means UNDEF
2878 int Idx = Indices[i];
2880 if (0 <= Idx && Idx < ResTyNumElts)
2882 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2886 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2888 Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
2890 SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
2892 if (Using1stVec && Using2ndVec) {
2893 Op0 = Op->getOperand(0);
2894 Op1 = Op->getOperand(1);
2895 } else if (Using1stVec)
2896 Op0 = Op1 = Op->getOperand(0);
2897 else if (Using2ndVec)
2898 Op0 = Op1 = Op->getOperand(1);
2900 llvm_unreachable("shuffle vector mask references neither vector operand?");
2902 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2903 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2904 // VSHF concatenates the vectors in a bitwise fashion:
2905 // <0b00, 0b01> + <0b10, 0b11> ->
2906 // 0b0100 + 0b1110 -> 0b01001110
2907 // <0b10, 0b11, 0b00, 0b01>
2908 // We must therefore swap the operands to get the correct result.
2909 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2912 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2913 // indices in the shuffle.
2914 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2915 SelectionDAG &DAG) const {
2916 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2917 EVT ResTy = Op->getValueType(0);
2919 if (!ResTy.is128BitVector())
2922 int ResTyNumElts = ResTy.getVectorNumElements();
2923 SmallVector<int, 16> Indices;
2925 for (int i = 0; i < ResTyNumElts; ++i)
2926 Indices.push_back(Node->getMaskElt(i));
2928 // splati.[bhwd] is preferable to the others but is matched from
2930 if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2931 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2933 if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
2935 if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
2937 if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
2939 if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
2941 if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
2943 if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
2945 if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
2947 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2951 MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
2952 MachineBasicBlock *BB) const {
2954 // bposge32_pseudo $vr0
2964 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2966 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2967 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
2968 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2969 DebugLoc DL = MI.getDebugLoc();
2970 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2971 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2972 MachineFunction *F = BB->getParent();
2973 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2974 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2975 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2978 F->insert(It, Sink);
2980 // Transfer the remainder of BB and its successor edges to Sink.
2981 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2983 Sink->transferSuccessorsAndUpdatePHIs(BB);
2986 BB->addSuccessor(FBB);
2987 BB->addSuccessor(TBB);
2988 FBB->addSuccessor(Sink);
2989 TBB->addSuccessor(Sink);
2991 // Insert the real bposge32 instruction to $BB.
2992 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2993 // Insert the real bposge32c instruction to $BB.
2994 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
2997 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2998 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2999 .addReg(Mips::ZERO).addImm(0);
3000 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3003 unsigned VR1 = RegInfo.createVirtualRegister(RC);
3004 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3005 .addReg(Mips::ZERO).addImm(1);
3007 // Insert phi function to $Sink.
3008 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3009 MI.getOperand(0).getReg())
3015 MI.eraseFromParent(); // The pseudo instruction is gone now.
3019 MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
3020 MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
3022 // vany_nonzero $rd, $ws
3033 // $rd = phi($rd1, $fbb, $rd2, $tbb)
3035 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3036 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3037 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3038 DebugLoc DL = MI.getDebugLoc();
3039 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3040 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
3041 MachineFunction *F = BB->getParent();
3042 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3043 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3044 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3047 F->insert(It, Sink);
3049 // Transfer the remainder of BB and its successor edges to Sink.
3050 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
3052 Sink->transferSuccessorsAndUpdatePHIs(BB);
3055 BB->addSuccessor(FBB);
3056 BB->addSuccessor(TBB);
3057 FBB->addSuccessor(Sink);
3058 TBB->addSuccessor(Sink);
3060 // Insert the real bnz.b instruction to $BB.
3061 BuildMI(BB, DL, TII->get(BranchOp))
3062 .addReg(MI.getOperand(1).getReg())
3066 unsigned RD1 = RegInfo.createVirtualRegister(RC);
3067 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3068 .addReg(Mips::ZERO).addImm(0);
3069 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3072 unsigned RD2 = RegInfo.createVirtualRegister(RC);
3073 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3074 .addReg(Mips::ZERO).addImm(1);
3076 // Insert phi function to $Sink.
3077 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3078 MI.getOperand(0).getReg())
3084 MI.eraseFromParent(); // The pseudo instruction is gone now.
3088 // Emit the COPY_FW pseudo instruction.
3090 // copy_fw_pseudo $fd, $ws, n
3092 // copy_u_w $rt, $ws, $n
3095 // When n is zero, the equivalent operation can be performed with (potentially)
3096 // zero instructions due to register overlaps. This optimization is never valid
3097 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3099 MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3100 MachineBasicBlock *BB) const {
3101 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3102 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3103 DebugLoc DL = MI.getDebugLoc();
3104 unsigned Fd = MI.getOperand(0).getReg();
3105 unsigned Ws = MI.getOperand(1).getReg();
3106 unsigned Lane = MI.getOperand(2).getImm();
3110 if (!Subtarget.useOddSPReg()) {
3111 // We must copy to an even-numbered MSA register so that the
3112 // single-precision sub-register is also guaranteed to be even-numbered.
3113 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3115 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3118 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3120 unsigned Wt = RegInfo.createVirtualRegister(
3121 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3122 &Mips::MSA128WEvensRegClass);
3124 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3125 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3128 MI.eraseFromParent(); // The pseudo instruction is gone now.
3132 // Emit the COPY_FD pseudo instruction.
3134 // copy_fd_pseudo $fd, $ws, n
3136 // splati.d $wt, $ws, $n
3137 // copy $fd, $wt:sub_64
3139 // When n is zero, the equivalent operation can be performed with (potentially)
3140 // zero instructions due to register overlaps. This optimization is always
3141 // valid because FR=1 mode which is the only supported mode in MSA.
3143 MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3144 MachineBasicBlock *BB) const {
3145 assert(Subtarget.isFP64bit());
3147 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3148 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3149 unsigned Fd = MI.getOperand(0).getReg();
3150 unsigned Ws = MI.getOperand(1).getReg();
3151 unsigned Lane = MI.getOperand(2).getImm() * 2;
3152 DebugLoc DL = MI.getDebugLoc();
3155 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3157 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3159 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3160 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3163 MI.eraseFromParent(); // The pseudo instruction is gone now.
3167 // Emit the INSERT_FW pseudo instruction.
3169 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3171 // subreg_to_reg $wt:sub_lo, $fs
3172 // insve_w $wd[$n], $wd_in, $wt[0]
3174 MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
3175 MachineBasicBlock *BB) const {
3176 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3177 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3178 DebugLoc DL = MI.getDebugLoc();
3179 unsigned Wd = MI.getOperand(0).getReg();
3180 unsigned Wd_in = MI.getOperand(1).getReg();
3181 unsigned Lane = MI.getOperand(2).getImm();
3182 unsigned Fs = MI.getOperand(3).getReg();
3183 unsigned Wt = RegInfo.createVirtualRegister(
3184 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3185 &Mips::MSA128WEvensRegClass);
3187 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3190 .addImm(Mips::sub_lo);
3191 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3197 MI.eraseFromParent(); // The pseudo instruction is gone now.
3201 // Emit the INSERT_FD pseudo instruction.
3203 // insert_fd_pseudo $wd, $fs, n
3205 // subreg_to_reg $wt:sub_64, $fs
3206 // insve_d $wd[$n], $wd_in, $wt[0]
3208 MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
3209 MachineBasicBlock *BB) const {
3210 assert(Subtarget.isFP64bit());
3212 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3213 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3214 DebugLoc DL = MI.getDebugLoc();
3215 unsigned Wd = MI.getOperand(0).getReg();
3216 unsigned Wd_in = MI.getOperand(1).getReg();
3217 unsigned Lane = MI.getOperand(2).getImm();
3218 unsigned Fs = MI.getOperand(3).getReg();
3219 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3221 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3224 .addImm(Mips::sub_64);
3225 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3231 MI.eraseFromParent(); // The pseudo instruction is gone now.
3235 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3238 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3240 // (SLL $lanetmp1, $lane, <log2size)
3241 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3242 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3243 // (NEG $lanetmp2, $lanetmp1)
3244 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3246 // For floating point:
3247 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3249 // (SUBREG_TO_REG $wt, $fs, <subreg>)
3250 // (SLL $lanetmp1, $lane, <log2size)
3251 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3252 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3253 // (NEG $lanetmp2, $lanetmp1)
3254 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3255 MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3256 MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3258 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3259 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3260 DebugLoc DL = MI.getDebugLoc();
3261 unsigned Wd = MI.getOperand(0).getReg();
3262 unsigned SrcVecReg = MI.getOperand(1).getReg();
3263 unsigned LaneReg = MI.getOperand(2).getReg();
3264 unsigned SrcValReg = MI.getOperand(3).getReg();
3266 const TargetRegisterClass *VecRC = nullptr;
3267 // FIXME: This should be true for N32 too.
3268 const TargetRegisterClass *GPRRC =
3269 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3270 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3271 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3272 unsigned EltLog2Size;
3273 unsigned InsertOp = 0;
3274 unsigned InsveOp = 0;
3275 switch (EltSizeInBytes) {
3277 llvm_unreachable("Unexpected size");
3280 InsertOp = Mips::INSERT_B;
3281 InsveOp = Mips::INSVE_B;
3282 VecRC = &Mips::MSA128BRegClass;
3286 InsertOp = Mips::INSERT_H;
3287 InsveOp = Mips::INSVE_H;
3288 VecRC = &Mips::MSA128HRegClass;
3292 InsertOp = Mips::INSERT_W;
3293 InsveOp = Mips::INSVE_W;
3294 VecRC = &Mips::MSA128WRegClass;
3298 InsertOp = Mips::INSERT_D;
3299 InsveOp = Mips::INSVE_D;
3300 VecRC = &Mips::MSA128DRegClass;
3305 unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3306 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3309 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3313 // Convert the lane index into a byte index
3314 if (EltSizeInBytes != 1) {
3315 unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3316 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3318 .addImm(EltLog2Size);
3322 // Rotate bytes around so that the desired lane is element zero
3323 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3324 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3327 .addReg(LaneReg, 0, SubRegIdx);
3329 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3331 // Use insve.df to insert to element zero
3332 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3338 // Use insert.df to insert to element zero
3339 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3345 // Rotate elements the rest of the way for a full rotation.
3346 // sld.df inteprets $rt modulo the number of columns so we only need to negate
3347 // the lane index to do this.
3348 unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3349 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3351 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3353 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3356 .addReg(LaneTmp2, 0, SubRegIdx);
3358 MI.eraseFromParent(); // The pseudo instruction is gone now.
3362 // Emit the FILL_FW pseudo instruction.
3364 // fill_fw_pseudo $wd, $fs
3366 // implicit_def $wt1
3367 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3368 // splati.w $wd, $wt2[0]
3370 MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
3371 MachineBasicBlock *BB) const {
3372 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3373 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3374 DebugLoc DL = MI.getDebugLoc();
3375 unsigned Wd = MI.getOperand(0).getReg();
3376 unsigned Fs = MI.getOperand(1).getReg();
3377 unsigned Wt1 = RegInfo.createVirtualRegister(
3378 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3379 : &Mips::MSA128WEvensRegClass);
3380 unsigned Wt2 = RegInfo.createVirtualRegister(
3381 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3382 : &Mips::MSA128WEvensRegClass);
3384 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3385 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3388 .addImm(Mips::sub_lo);
3389 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3391 MI.eraseFromParent(); // The pseudo instruction is gone now.
3395 // Emit the FILL_FD pseudo instruction.
3397 // fill_fd_pseudo $wd, $fs
3399 // implicit_def $wt1
3400 // insert_subreg $wt2:subreg_64, $wt1, $fs
3401 // splati.d $wd, $wt2[0]
3403 MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
3404 MachineBasicBlock *BB) const {
3405 assert(Subtarget.isFP64bit());
3407 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3408 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3409 DebugLoc DL = MI.getDebugLoc();
3410 unsigned Wd = MI.getOperand(0).getReg();
3411 unsigned Fs = MI.getOperand(1).getReg();
3412 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3413 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3415 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3416 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3419 .addImm(Mips::sub_64);
3420 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3422 MI.eraseFromParent(); // The pseudo instruction is gone now.
3426 // Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3429 // STF16 MSA128F16:$wd, mem_simm10:$addr
3431 // copy_u.h $rtemp,$wd[0]
3434 // Safety: We can't use st.h & co as they would over write the memory after
3435 // the destination. It would require half floats be allocated 16 bytes(!) of
3438 MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3439 MachineBasicBlock *BB) const {
3441 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3442 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3443 DebugLoc DL = MI.getDebugLoc();
3444 unsigned Ws = MI.getOperand(0).getReg();
3445 unsigned Rt = MI.getOperand(1).getReg();
3446 const MachineMemOperand &MMO = **MI.memoperands_begin();
3447 unsigned Imm = MMO.getOffset();
3449 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3450 // spill and reload can expand as a GPR64 operand. Examine the
3451 // operand in detail and default to ABI.
3452 const TargetRegisterClass *RC =
3453 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3454 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3455 : &Mips::GPR64RegClass);
3456 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3457 unsigned Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3459 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3461 unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3462 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3465 .addImm(Mips::sub_32);
3468 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3472 .addMemOperand(BB->getParent()->getMachineMemOperand(
3473 &MMO, MMO.getOffset(), MMO.getSize()));
3475 MI.eraseFromParent();
3479 // Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3481 // LD_F16 MSA128F16:$wd, mem_simm10:$addr
3484 // fill.h $wd, $rtemp
3486 // Safety: We can't use ld.h & co as they over-read from the source.
3487 // Additionally, if the address is not modulo 16, 2 cases can occur:
3488 // a) Segmentation fault as the load instruction reads from a memory page
3489 // memory it's not supposed to.
3490 // b) The load crosses an implementation specific boundary, requiring OS
3493 MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3494 MachineBasicBlock *BB) const {
3496 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3497 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3498 DebugLoc DL = MI.getDebugLoc();
3499 unsigned Wd = MI.getOperand(0).getReg();
3501 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3502 // spill and reload can expand as a GPR64 operand. Examine the
3503 // operand in detail and default to ABI.
3504 const TargetRegisterClass *RC =
3505 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3506 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3507 : &Mips::GPR64RegClass);
3509 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3510 unsigned Rt = RegInfo.createVirtualRegister(RC);
3512 MachineInstrBuilder MIB =
3513 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3514 for (unsigned i = 1; i < MI.getNumOperands(); i++)
3515 MIB.add(MI.getOperand(i));
3518 unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3519 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3523 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3525 MI.eraseFromParent();
3529 // Emit the FPROUND_PSEUDO instruction.
3531 // Round an FGR64Opnd, FGR32Opnd to an f16.
3533 // Safety: Cycle the operand through the GPRs so the result always ends up
3534 // the correct MSA register.
3536 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3537 // / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3538 // (which they can be, as the MSA registers are defined to alias the
3539 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3540 // the correct register class. That requires operands be tie-able across
3541 // register classes which have a sub/super register class relationship.
3545 // FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3548 // fill.w $rtemp, $wtemp
3549 // fexdo.w $wd, $wtemp, $wtemp
3551 // For FPG64Opnd on mips32r2+:
3553 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3556 // fill.w $rtemp, $wtemp
3557 // mfhc1 $rtemp2, $fs
3558 // insert.w $wtemp[1], $rtemp2
3559 // insert.w $wtemp[3], $rtemp2
3560 // fexdo.w $wtemp2, $wtemp, $wtemp
3561 // fexdo.h $wd, $temp2, $temp2
3563 // For FGR64Opnd on mips64r2+:
3565 // FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3567 // dmfc1 $rtemp, $fs
3568 // fill.d $rtemp, $wtemp
3569 // fexdo.w $wtemp2, $wtemp, $wtemp
3570 // fexdo.h $wd, $wtemp2, $wtemp2
3572 // Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3573 // undef bits are "just right" and the exception enable bits are
3574 // set. By using fill.w to replicate $fs into all elements over
3575 // insert.w for one element, we avoid that potiential case. If
3576 // fexdo.[hw] causes an exception in, the exception is valid and it
3577 // occurs for all elements.
3579 MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3580 MachineBasicBlock *BB,
3581 bool IsFGR64) const {
3583 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3584 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3586 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3588 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3589 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3591 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3592 DebugLoc DL = MI.getDebugLoc();
3593 unsigned Wd = MI.getOperand(0).getReg();
3594 unsigned Fs = MI.getOperand(1).getReg();
3596 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3597 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3598 const TargetRegisterClass *GPRRC =
3599 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3600 unsigned MFC1Opc = IsFGR64onMips64
3602 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3603 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3605 // Perform the register class copy as mentioned above.
3606 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3607 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3608 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3609 unsigned WPHI = Wtemp;
3611 if (IsFGR64onMips32) {
3612 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3613 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3614 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3615 unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3616 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3620 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3628 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3629 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3635 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3637 MI.eraseFromParent();
3641 // Emit the FPEXTEND_PSEUDO instruction.
3643 // Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3645 // Safety: Cycle the result through the GPRs so the result always ends up
3646 // the correct floating point register.
3648 // FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3649 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3650 // (which they can be, as the MSA registers are defined to alias the
3651 // FPU's 64 bit and 32 bit registers) the result can be accessed using
3652 // the correct register class. That requires operands be tie-able across
3653 // register classes which have a sub/super register class relationship. I
3658 // FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3660 // fexupr.w $wtemp, $ws
3661 // copy_s.w $rtemp, $ws[0]
3664 // For FGR64Opnd on Mips64:
3666 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3668 // fexupr.w $wtemp, $ws
3669 // fexupr.d $wtemp2, $wtemp
3670 // copy_s.d $rtemp, $wtemp2s[0]
3671 // dmtc1 $rtemp, $fd
3673 // For FGR64Opnd on Mips32:
3675 // FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3677 // fexupr.w $wtemp, $ws
3678 // fexupr.d $wtemp2, $wtemp
3679 // copy_s.w $rtemp, $wtemp2[0]
3680 // mtc1 $rtemp, $ftemp
3681 // copy_s.w $rtemp2, $wtemp2[1]
3682 // $fd = mthc1 $rtemp2, $ftemp
3684 MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3685 MachineBasicBlock *BB,
3686 bool IsFGR64) const {
3688 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3689 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3691 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3693 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3694 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3696 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3697 DebugLoc DL = MI.getDebugLoc();
3698 unsigned Fd = MI.getOperand(0).getReg();
3699 unsigned Ws = MI.getOperand(1).getReg();
3701 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3702 const TargetRegisterClass *GPRRC =
3703 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3704 unsigned MTC1Opc = IsFGR64onMips64
3706 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3707 unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3709 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3710 unsigned WPHI = Wtemp;
3712 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3714 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3715 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3718 // Perform the safety regclass copy mentioned above.
3719 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3720 unsigned FPRPHI = IsFGR64onMips32
3721 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3723 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3724 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3726 if (IsFGR64onMips32) {
3727 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3728 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3731 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3736 MI.eraseFromParent();
3740 // Emit the FEXP2_W_1 pseudo instructions.
3742 // fexp2_w_1_pseudo $wd, $wt
3745 // fexp2.w $wd, $ws, $wt
3747 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
3748 MachineBasicBlock *BB) const {
3749 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3750 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3751 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3752 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3753 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3754 DebugLoc DL = MI.getDebugLoc();
3756 // Splat 1.0 into a vector
3757 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3758 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3760 // Emit 1.0 * fexp2(Wt)
3761 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3763 .addReg(MI.getOperand(1).getReg());
3765 MI.eraseFromParent(); // The pseudo instruction is gone now.
3769 // Emit the FEXP2_D_1 pseudo instructions.
3771 // fexp2_d_1_pseudo $wd, $wt
3774 // fexp2.d $wd, $ws, $wt
3776 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
3777 MachineBasicBlock *BB) const {
3778 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3779 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3780 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3781 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3782 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3783 DebugLoc DL = MI.getDebugLoc();
3785 // Splat 1.0 into a vector
3786 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3787 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3789 // Emit 1.0 * fexp2(Wt)
3790 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3792 .addReg(MI.getOperand(1).getReg());
3794 MI.eraseFromParent(); // The pseudo instruction is gone now.