contrib/llvm/lib/Target/Mips/MipsSEISelLowering.h

   1 //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Subclass of MipsTargetLowering specialized for mips32/64.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
  15 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
  16
  17 #include "MipsISelLowering.h"
  18 #include "llvm/CodeGen/MachineValueType.h"
  19 #include "llvm/CodeGen/SelectionDAGNodes.h"
  20
  21 namespace llvm {
  22
  23 class MachineBasicBlock;
  24 class MachineInstr;
  25 class MipsSubtarget;
  26 class MipsTargetMachine;
  27 class SelectionDAG;
  28 class TargetRegisterClass;
  29
  30   class MipsSETargetLowering : public MipsTargetLowering  {
  31   public:
  32     explicit MipsSETargetLowering(const MipsTargetMachine &TM,
  33                                   const MipsSubtarget &STI);
  34
  35     /// \brief Enable MSA support for the given integer type and Register
  36     /// class.
  37     void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
  38
  39     /// \brief Enable MSA support for the given floating-point type and
  40     /// Register class.
  41     void addMSAFloatType(MVT::SimpleValueType Ty,
  42                          const TargetRegisterClass *RC);
  43
  44     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0,
  45                                         unsigned Align = 1,
  46                                         bool *Fast = nullptr) const override;
  47
  48     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  49
  50     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
  51
  52     MachineBasicBlock *
  53     EmitInstrWithCustomInserter(MachineInstr &MI,
  54                                 MachineBasicBlock *MBB) const override;
  55
  56     bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
  57       return false;
  58     }
  59
  60     const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
  61
  62   private:
  63     bool isEligibleForTailCallOptimization(
  64         const CCState &CCInfo, unsigned NextStackOffset,
  65         const MipsFunctionInfo &FI) const override;
  66
  67     void
  68     getOpndList(SmallVectorImpl<SDValue> &Ops,
  69                 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
  70                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
  71                 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
  72                 SDValue Chain) const override;
  73
  74     SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
  75     SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
  76
  77     SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
  78                         SelectionDAG &DAG) const;
  79
  80     SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  81     SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  82     SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
  83     SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
  84     SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
  85     /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
  86     /// depending on the indices in the shuffle.
  87     SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
  88     SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
  89
  90     MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
  91                                     MachineBasicBlock *BB) const;
  92     MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
  93                                             MachineBasicBlock *BB,
  94                                             unsigned BranchOp) const;
  95     /// \brief Emit the COPY_FW pseudo instruction
  96     MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
  97                                    MachineBasicBlock *BB) const;
  98     /// \brief Emit the COPY_FD pseudo instruction
  99     MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
 100                                    MachineBasicBlock *BB) const;
 101     /// \brief Emit the INSERT_FW pseudo instruction
 102     MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
 103                                      MachineBasicBlock *BB) const;
 104     /// \brief Emit the INSERT_FD pseudo instruction
 105     MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
 106                                      MachineBasicBlock *BB) const;
 107     /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
 108     MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
 109                                           MachineBasicBlock *BB,
 110                                           unsigned EltSizeInBytes,
 111                                           bool IsFP) const;
 112     /// \brief Emit the FILL_FW pseudo instruction
 113     MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
 114                                    MachineBasicBlock *BB) const;
 115     /// \brief Emit the FILL_FD pseudo instruction
 116     MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
 117                                    MachineBasicBlock *BB) const;
 118     /// \brief Emit the FEXP2_W_1 pseudo instructions.
 119     MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
 120                                      MachineBasicBlock *BB) const;
 121     /// \brief Emit the FEXP2_D_1 pseudo instructions.
 122     MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
 123                                      MachineBasicBlock *BB) const;
 124     /// \brief Emit the FILL_FW pseudo instruction
 125     MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
 126                                    MachineBasicBlock *BB) const;
 127     /// \brief Emit the FILL_FD pseudo instruction
 128     MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
 129                                    MachineBasicBlock *BB) const;
 130     /// \brief Emit the FEXP2_W_1 pseudo instructions.
 131     MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
 132                                            MachineBasicBlock *BB,
 133                                            bool IsFGR64) const;
 134     /// \brief Emit the FEXP2_D_1 pseudo instructions.
 135     MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
 136                                           MachineBasicBlock *BBi,
 137                                           bool IsFGR64) const;
 138   };
 139
 140 } // end namespace llvm
 141
 142 #endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H