1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/TargetRegistry.h"
28 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
41 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
42 int &FrameIndex) const {
43 unsigned Opc = MI.getOpcode();
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
47 if ((MI.getOperand(1).isFI()) && // is a stack slot
48 (MI.getOperand(2).isImm()) && // the imm is zero
49 (isZeroImm(MI.getOperand(2)))) {
50 FrameIndex = MI.getOperand(1).getIndex();
51 return MI.getOperand(0).getReg();
58 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 /// store to a stack slot, return the virtual or physical register number of
60 /// the source reg along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than storing to the stack slot.
63 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
64 int &FrameIndex) const {
65 unsigned Opc = MI.getOpcode();
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
69 if ((MI.getOperand(1).isFI()) && // is a stack slot
70 (MI.getOperand(2).isImm()) && // the imm is zero
71 (isZeroImm(MI.getOperand(2)))) {
72 FrameIndex = MI.getOperand(1).getIndex();
73 return MI.getOperand(0).getReg();
79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator I,
81 const DebugLoc &DL, unsigned DestReg,
82 unsigned SrcReg, bool KillSrc) const {
83 unsigned Opc = 0, ZeroReg = 0;
84 bool isMicroMips = Subtarget.inMicroMipsMode();
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
87 if (Mips::GPR32RegClass.contains(SrcReg)) {
89 Opc = Mips::MOVE16_MM;
91 Opc = Mips::OR, ZeroReg = Mips::ZERO;
92 } else if (Mips::CCRRegClass.contains(SrcReg))
94 else if (Mips::FGR32RegClass.contains(SrcReg))
96 else if (Mips::HI32RegClass.contains(SrcReg)) {
97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
99 } else if (Mips::LO32RegClass.contains(SrcReg)) {
100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
102 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
103 Opc = Mips::MFHI_DSP;
104 else if (Mips::LO32DSPRegClass.contains(SrcReg))
105 Opc = Mips::MFLO_DSP;
106 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
111 else if (Mips::MSACtrlRegClass.contains(SrcReg))
114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
115 if (Mips::CCRRegClass.contains(DestReg))
117 else if (Mips::FGR32RegClass.contains(DestReg))
119 else if (Mips::HI32RegClass.contains(DestReg))
120 Opc = Mips::MTHI, DestReg = 0;
121 else if (Mips::LO32RegClass.contains(DestReg))
122 Opc = Mips::MTLO, DestReg = 0;
123 else if (Mips::HI32DSPRegClass.contains(DestReg))
124 Opc = Mips::MTHI_DSP;
125 else if (Mips::LO32DSPRegClass.contains(DestReg))
126 Opc = Mips::MTLO_DSP;
127 else if (Mips::DSPCCRegClass.contains(DestReg)) {
128 BuildMI(MBB, I, DL, get(Mips::WRDSP))
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
130 .addReg(DestReg, RegState::ImplicitDefine);
132 } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
133 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
135 .addReg(SrcReg, getKillRegState(KillSrc));
139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142 Opc = Mips::FMOV_D32;
143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144 Opc = Mips::FMOV_D64;
145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146 if (Mips::GPR64RegClass.contains(SrcReg))
147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
148 else if (Mips::HI64RegClass.contains(SrcReg))
149 Opc = Mips::MFHI64, SrcReg = 0;
150 else if (Mips::LO64RegClass.contains(SrcReg))
151 Opc = Mips::MFLO64, SrcReg = 0;
152 else if (Mips::FGR64RegClass.contains(SrcReg))
155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156 if (Mips::HI64RegClass.contains(DestReg))
157 Opc = Mips::MTHI64, DestReg = 0;
158 else if (Mips::LO64RegClass.contains(DestReg))
159 Opc = Mips::MTLO64, DestReg = 0;
160 else if (Mips::FGR64RegClass.contains(DestReg))
163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
164 if (Mips::MSA128BRegClass.contains(SrcReg))
168 assert(Opc && "Cannot copy registers");
170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
173 MIB.addReg(DestReg, RegState::Define);
176 MIB.addReg(SrcReg, getKillRegState(KillSrc));
182 void MipsSEInstrInfo::
183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184 unsigned SrcReg, bool isKill, int FI,
185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
186 int64_t Offset) const {
188 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
192 if (Mips::GPR32RegClass.hasSubClassEq(RC))
194 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
196 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
197 Opc = Mips::STORE_ACC64;
198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
199 Opc = Mips::STORE_ACC64DSP;
200 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
201 Opc = Mips::STORE_ACC128;
202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
203 Opc = Mips::STORE_CCOND_DSP;
204 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
208 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
210 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
212 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
213 TRI->isTypeLegalForClass(*RC, MVT::v8f16))
215 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
216 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
218 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
219 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
221 else if (Mips::LO32RegClass.hasSubClassEq(RC))
223 else if (Mips::LO64RegClass.hasSubClassEq(RC))
225 else if (Mips::HI32RegClass.hasSubClassEq(RC))
227 else if (Mips::HI64RegClass.hasSubClassEq(RC))
230 // Hi, Lo are normally caller save but they are callee save
231 // for interrupt handling.
232 const Function *Func = MBB.getParent()->getFunction();
233 if (Func->hasFnAttribute("interrupt")) {
234 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
235 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
237 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
238 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
239 SrcReg = Mips::K0_64;
240 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
241 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
243 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
244 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
245 SrcReg = Mips::K0_64;
249 assert(Opc && "Register class not handled!");
250 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
251 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
254 void MipsSEInstrInfo::
255 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
256 unsigned DestReg, int FI, const TargetRegisterClass *RC,
257 const TargetRegisterInfo *TRI, int64_t Offset) const {
259 if (I != MBB.end()) DL = I->getDebugLoc();
260 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
263 const Function *Func = MBB.getParent()->getFunction();
264 bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") &&
265 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
266 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
268 if (Mips::GPR32RegClass.hasSubClassEq(RC))
270 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
272 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
273 Opc = Mips::LOAD_ACC64;
274 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
275 Opc = Mips::LOAD_ACC64DSP;
276 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
277 Opc = Mips::LOAD_ACC128;
278 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
279 Opc = Mips::LOAD_CCOND_DSP;
280 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
282 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
284 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
286 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
288 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
289 TRI->isTypeLegalForClass(*RC, MVT::v8f16))
291 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
292 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
294 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
295 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
297 else if (Mips::HI32RegClass.hasSubClassEq(RC))
299 else if (Mips::HI64RegClass.hasSubClassEq(RC))
301 else if (Mips::LO32RegClass.hasSubClassEq(RC))
303 else if (Mips::LO64RegClass.hasSubClassEq(RC))
306 assert(Opc && "Register class not handled!");
308 if (!ReqIndirectLoad)
309 BuildMI(MBB, I, DL, get(Opc), DestReg)
314 // Load HI/LO through K0. Notably the DestReg is encoded into the
315 // instruction itself.
316 unsigned Reg = Mips::K0;
317 unsigned LdOp = Mips::MTLO;
318 if (DestReg == Mips::HI0)
321 if (Subtarget.getABI().ArePtrs64bit()) {
323 if (DestReg == Mips::HI0_64)
329 BuildMI(MBB, I, DL, get(Opc), Reg)
333 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
337 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
338 MachineBasicBlock &MBB = *MI.getParent();
339 bool isMicroMips = Subtarget.inMicroMipsMode();
342 switch (MI.getDesc().getOpcode()) {
346 expandRetRA(MBB, MI);
351 case Mips::PseudoMFHI:
352 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
353 expandPseudoMFHiLo(MBB, MI, Opc);
355 case Mips::PseudoMFLO:
356 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
357 expandPseudoMFHiLo(MBB, MI, Opc);
359 case Mips::PseudoMFHI64:
360 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
362 case Mips::PseudoMFLO64:
363 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
365 case Mips::PseudoMTLOHI:
366 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
368 case Mips::PseudoMTLOHI64:
369 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
371 case Mips::PseudoMTLOHI_DSP:
372 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
374 case Mips::PseudoCVT_S_W:
375 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
377 case Mips::PseudoCVT_D32_W:
378 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
380 case Mips::PseudoCVT_S_L:
381 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
383 case Mips::PseudoCVT_D64_W:
384 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
386 case Mips::PseudoCVT_D64_L:
387 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
389 case Mips::BuildPairF64:
390 expandBuildPairF64(MBB, MI, false);
392 case Mips::BuildPairF64_64:
393 expandBuildPairF64(MBB, MI, true);
395 case Mips::ExtractElementF64:
396 expandExtractElementF64(MBB, MI, false);
398 case Mips::ExtractElementF64_64:
399 expandExtractElementF64(MBB, MI, true);
401 case Mips::MIPSeh_return32:
402 case Mips::MIPSeh_return64:
403 expandEhReturn(MBB, MI);
411 /// getOppositeBranchOpc - Return the inverse of the specified
412 /// opcode, e.g. turning BEQ to BNE.
413 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
415 default: llvm_unreachable("Illegal opcode!");
416 case Mips::BEQ: return Mips::BNE;
417 case Mips::BEQ_MM: return Mips::BNE_MM;
418 case Mips::BNE: return Mips::BEQ;
419 case Mips::BNE_MM: return Mips::BEQ_MM;
420 case Mips::BGTZ: return Mips::BLEZ;
421 case Mips::BGEZ: return Mips::BLTZ;
422 case Mips::BLTZ: return Mips::BGEZ;
423 case Mips::BLEZ: return Mips::BGTZ;
424 case Mips::BEQ64: return Mips::BNE64;
425 case Mips::BNE64: return Mips::BEQ64;
426 case Mips::BGTZ64: return Mips::BLEZ64;
427 case Mips::BGEZ64: return Mips::BLTZ64;
428 case Mips::BLTZ64: return Mips::BGEZ64;
429 case Mips::BLEZ64: return Mips::BGTZ64;
430 case Mips::BC1T: return Mips::BC1F;
431 case Mips::BC1F: return Mips::BC1T;
432 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
433 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
434 case Mips::BEQZC: return Mips::BNEZC;
435 case Mips::BNEZC: return Mips::BEQZC;
436 case Mips::BEQC: return Mips::BNEC;
437 case Mips::BNEC: return Mips::BEQC;
438 case Mips::BGTZC: return Mips::BLEZC;
439 case Mips::BGEZC: return Mips::BLTZC;
440 case Mips::BLTZC: return Mips::BGEZC;
441 case Mips::BLEZC: return Mips::BGTZC;
442 case Mips::BEQZC64: return Mips::BNEZC64;
443 case Mips::BNEZC64: return Mips::BEQZC64;
444 case Mips::BEQC64: return Mips::BNEC64;
445 case Mips::BNEC64: return Mips::BEQC64;
446 case Mips::BGEC64: return Mips::BLTC64;
447 case Mips::BGEUC64: return Mips::BLTUC64;
448 case Mips::BLTC64: return Mips::BGEC64;
449 case Mips::BLTUC64: return Mips::BGEUC64;
450 case Mips::BGTZC64: return Mips::BLEZC64;
451 case Mips::BGEZC64: return Mips::BLTZC64;
452 case Mips::BLTZC64: return Mips::BGEZC64;
453 case Mips::BLEZC64: return Mips::BGTZC64;
457 /// Adjust SP by Amount bytes.
458 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
459 MachineBasicBlock &MBB,
460 MachineBasicBlock::iterator I) const {
461 MipsABIInfo ABI = Subtarget.getABI();
463 unsigned ADDiu = ABI.GetPtrAddiuOp();
468 if (isInt<16>(Amount)) {
469 // addi sp, sp, amount
470 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
472 // For numbers which are not 16bit integers we synthesize Amount inline
473 // then add or subtract it from sp.
474 unsigned Opc = ABI.GetPtrAdduOp();
476 Opc = ABI.GetPtrSubuOp();
479 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
480 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
484 /// This function generates the sequence of instructions needed to get the
485 /// result of adding register REG and immediate IMM.
486 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
487 MachineBasicBlock::iterator II,
489 unsigned *NewImm) const {
490 MipsAnalyzeImmediate AnalyzeImm;
491 const MipsSubtarget &STI = Subtarget;
492 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
493 unsigned Size = STI.isABI_N64() ? 64 : 32;
494 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
495 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
496 const TargetRegisterClass *RC = STI.isABI_N64() ?
497 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
498 bool LastInstrIsADDiu = NewImm;
500 const MipsAnalyzeImmediate::InstSeq &Seq =
501 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
502 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
504 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
506 // The first instruction can be a LUi, which is different from other
507 // instructions (ADDiu, ORI and SLL) in that it does not have a register
509 unsigned Reg = RegInfo.createVirtualRegister(RC);
511 if (Inst->Opc == LUi)
512 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
514 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
515 .addImm(SignExtend64<16>(Inst->ImmOpnd));
517 // Build the remaining instructions in Seq.
518 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
519 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
520 .addImm(SignExtend64<16>(Inst->ImmOpnd));
522 if (LastInstrIsADDiu)
523 *NewImm = Inst->ImmOpnd;
528 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
529 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
530 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
531 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
532 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
533 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
534 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
535 Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
536 Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
537 Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
538 Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
539 Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 ||
540 Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
541 Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
542 Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
543 Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
544 Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
547 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
548 MachineBasicBlock::iterator I) const {
550 MachineInstrBuilder MIB;
551 if (Subtarget.isGP64bit())
552 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
553 .addReg(Mips::RA_64, RegState::Undef);
555 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
556 .addReg(Mips::RA, RegState::Undef);
558 // Retain any imp-use flags.
559 for (auto & MO : I->operands()) {
565 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
566 MachineBasicBlock::iterator I) const {
567 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
570 std::pair<bool, bool>
571 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
572 const MachineFunction &MF) const {
573 const MCInstrDesc &Desc = get(Opc);
574 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
575 const MipsRegisterInfo *RI = &getRegisterInfo();
576 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
577 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
579 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
582 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
583 MachineBasicBlock::iterator I,
584 unsigned NewOpc) const {
585 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
588 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
589 MachineBasicBlock::iterator I,
592 bool HasExplicitDef) const {
594 // lo_hi pseudomtlohi $gpr0, $gpr1
595 // to these two instructions:
599 DebugLoc DL = I->getDebugLoc();
600 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
601 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
602 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
604 // Add lo/hi registers if the mtlo/hi instructions created have explicit
606 if (HasExplicitDef) {
607 unsigned DstReg = I->getOperand(0).getReg();
608 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
609 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
610 LoInst.addReg(DstLo, RegState::Define);
611 HiInst.addReg(DstHi, RegState::Define);
614 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
615 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
618 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
619 MachineBasicBlock::iterator I,
620 unsigned CvtOpc, unsigned MovOpc,
622 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
623 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
624 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
625 unsigned KillSrc = getKillRegState(Src.isKill());
626 DebugLoc DL = I->getDebugLoc();
627 bool DstIsLarger, SrcIsLarger;
629 std::tie(DstIsLarger, SrcIsLarger) =
630 compareOpndSize(CvtOpc, *MBB.getParent());
633 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
636 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
638 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
639 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
642 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
643 MachineBasicBlock::iterator I,
645 unsigned DstReg = I->getOperand(0).getReg();
646 unsigned SrcReg = I->getOperand(1).getReg();
647 unsigned N = I->getOperand(2).getImm();
648 DebugLoc dl = I->getDebugLoc();
650 assert(N < 2 && "Invalid immediate");
651 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
652 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
654 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
655 // in MipsSEFrameLowering.cpp.
656 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
658 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
659 // in MipsSEFrameLowering.cpp.
660 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
662 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
663 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
664 // claim to read the whole 64-bits as part of a white lie used to
665 // temporarily work around a widespread bug in the -mfp64 support.
666 // The problem is that none of the 32-bit fpu ops mention the fact
667 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
668 // requires a major overhaul of the FPU implementation which can't
669 // be done right now due to time constraints.
670 // MFHC1 is one of two instructions that are affected since they are
671 // the only instructions that don't read the lower 32-bits.
672 // We therefore pretend that it reads the bottom 32-bits to
673 // artificially create a dependency and prevent the scheduler
674 // changing the behaviour of the code.
675 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
678 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
681 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
682 MachineBasicBlock::iterator I,
684 unsigned DstReg = I->getOperand(0).getReg();
685 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
686 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
687 DebugLoc dl = I->getDebugLoc();
688 const TargetRegisterInfo &TRI = getRegisterInfo();
690 // When mthc1 is available, use:
694 // Otherwise, for O32 FPXX ABI:
695 // spill + reload via ldc1
696 // This case is handled by the frame lowering code.
698 // Otherwise, for FP32:
702 // The case where dmtc1 is available doesn't need to be handled here
703 // because it never creates a BuildPairF64 node.
705 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
706 // in MipsSEFrameLowering.cpp.
707 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
709 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
710 // in MipsSEFrameLowering.cpp.
711 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
713 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
716 if (Subtarget.hasMTHC1()) {
717 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
718 // around a widespread bug in the -mfp64 support.
719 // The problem is that none of the 32-bit fpu ops mention the fact
720 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
721 // requires a major overhaul of the FPU implementation which can't
722 // be done right now due to time constraints.
723 // MTHC1 is one of two instructions that are affected since they are
724 // the only instructions that don't read the lower 32-bits.
725 // We therefore pretend that it reads the bottom 32-bits to
726 // artificially create a dependency and prevent the scheduler
727 // changing the behaviour of the code.
728 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
731 } else if (Subtarget.isABI_FPXX())
732 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
734 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
738 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
739 MachineBasicBlock::iterator I) const {
740 // This pseudo instruction is generated as part of the lowering of
741 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
742 // indirect jump to TargetReg
743 MipsABIInfo ABI = Subtarget.getABI();
744 unsigned ADDU = ABI.GetPtrAdduOp();
745 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
746 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
747 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
748 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
749 unsigned OffsetReg = I->getOperand(0).getReg();
750 unsigned TargetReg = I->getOperand(1).getReg();
752 // addu $ra, $v0, $zero
753 // addu $sp, $sp, $v1
754 // jr $ra (via RetRA)
755 const TargetMachine &TM = MBB.getParent()->getTarget();
756 if (TM.isPositionIndependent())
757 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
760 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
763 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
767 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
768 return new MipsSEInstrInfo(STI);