1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "MipsSERegisterInfo.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "mips-reg-info"
42 MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
44 bool MipsSERegisterInfo::
45 requiresRegisterScavenging(const MachineFunction &MF) const {
49 bool MipsSERegisterInfo::
50 requiresFrameIndexScavenging(const MachineFunction &MF) const {
54 const TargetRegisterClass *
55 MipsSERegisterInfo::intRegClass(unsigned Size) const {
57 return &Mips::GPR32RegClass;
60 return &Mips::GPR64RegClass;
63 /// Get the size of the offset supported by the given load/store/inline asm.
64 /// The result includes the effects of any scale factors applied to the
65 /// instruction immediate.
66 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode,
74 return 10 + 1 /* scale factor */;
77 return 10 + 2 /* scale factor */;
80 return 10 + 3 /* scale factor */;
104 case Mips::INLINEASM: {
105 unsigned ConstraintID = InlineAsm::getMemoryConstraintID(MO.getImm());
106 switch (ConstraintID) {
107 case InlineAsm::Constraint_ZC: {
108 const MipsSubtarget &Subtarget = MO.getParent()
111 ->getSubtarget<MipsSubtarget>();
112 if (Subtarget.inMicroMipsMode())
115 if (Subtarget.hasMips32r6())
129 /// Get the scale factor applied to the immediate in the given load/store.
130 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
146 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
147 unsigned OpNo, int FrameIndex,
149 int64_t SPOffset) const {
150 MachineInstr &MI = *II;
151 MachineFunction &MF = *MI.getParent()->getParent();
152 MachineFrameInfo &MFI = MF.getFrameInfo();
153 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
156 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
157 const MipsRegisterInfo *RegInfo =
158 static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
160 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
165 MinCSFI = CSI[0].getFrameIdx();
166 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
169 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
170 bool IsISRRegFI = MipsFI->isISRRegFI(FrameIndex);
171 // The following stack frame objects are always referenced relative to $sp:
172 // 1. Outgoing arguments.
173 // 2. Pointer to dynamically allocated stack space.
174 // 3. Locations for callee-saved registers.
175 // 4. Locations for eh data registers.
176 // 5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
177 // Everything else is referenced relative to whatever register
178 // getFrameRegister() returns.
181 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
183 FrameReg = ABI.GetStackPtr();
184 else if (RegInfo->needsStackRealignment(MF)) {
185 if (MFI.hasVarSizedObjects() && !MFI.isFixedObjectIndex(FrameIndex))
186 FrameReg = ABI.GetBasePtr();
187 else if (MFI.isFixedObjectIndex(FrameIndex))
188 FrameReg = getFrameRegister(MF);
190 FrameReg = ABI.GetStackPtr();
192 FrameReg = getFrameRegister(MF);
194 // Calculate final offset.
195 // - There is no need to change the offset if the frame object is one of the
196 // following: an outgoing argument, pointer to a dynamically allocated
197 // stack space or a $gp restore location,
198 // - If the frame object is any of the following, its offset must be adjusted
199 // by adding the size of the stack:
200 // incoming argument, callee-saved register location or local variable.
204 Offset = SPOffset + (int64_t)StackSize;
205 Offset += MI.getOperand(OpNo + 1).getImm();
207 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
209 if (!MI.isDebugValue()) {
210 // Make sure Offset fits within the field available.
211 // For MSA instructions, this is a 10-bit signed immediate (scaled by
212 // element size), otherwise it is a 16-bit signed immediate.
213 unsigned OffsetBitSize =
214 getLoadStoreOffsetSizeInBits(MI.getOpcode(), MI.getOperand(OpNo - 1));
215 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
217 if (OffsetBitSize < 16 && isInt<16>(Offset) &&
218 (!isIntN(OffsetBitSize, Offset) ||
219 OffsetToAlignment(Offset, OffsetAlign) != 0)) {
220 // If we have an offset that needs to fit into a signed n-bit immediate
221 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
222 MachineBasicBlock &MBB = *MI.getParent();
223 DebugLoc DL = II->getDebugLoc();
224 const TargetRegisterClass *PtrRC =
225 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
226 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
227 unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
228 const MipsSEInstrInfo &TII =
229 *static_cast<const MipsSEInstrInfo *>(
230 MBB.getParent()->getSubtarget().getInstrInfo());
231 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
238 } else if (!isInt<16>(Offset)) {
239 // Otherwise split the offset into 16-bit pieces and add it in multiple
241 MachineBasicBlock &MBB = *MI.getParent();
242 DebugLoc DL = II->getDebugLoc();
244 const MipsSEInstrInfo &TII =
245 *static_cast<const MipsSEInstrInfo *>(
246 MBB.getParent()->getSubtarget().getInstrInfo());
247 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
248 OffsetBitSize == 16 ? &NewImm : nullptr);
249 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
250 .addReg(Reg, RegState::Kill);
253 Offset = SignExtend64<16>(NewImm);
258 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
259 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);