1 //==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def MipsP5600Model : SchedMachineModel {
11 int IssueWidth = 2; // 2x dispatched per cycle
12 int MicroOpBufferSize = 48; // min(48, 48, 64)
14 int MispredictPenalty = 8; // TODO: Estimated
16 let CompleteModel = 1;
18 list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6,
19 HasMips64, HasMips64r2, HasCnMips,
20 InMicroMips, InMips16Mode,
21 HasMicroMips32r6, HasMicroMips64r6,
22 HasDSP, HasDSPR2, HasMT];
26 let SchedModel = MipsP5600Model in {
31 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
32 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
37 def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>;
39 // and, lui, nor, or, slti, sltiu, sub, subu, xor
40 def : ItinRW<[P5600WriteALU],
41 [II_AND, II_LUI, II_NOR, II_OR, II_SLTI_SLTIU, II_SUB, II_SUBU,
47 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
48 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
49 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
50 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
52 def P5600AL2Div : ProcResource<1>;
53 // Pseudo-resource used to block CTISTD when handling multi-pipeline splits.
54 def P5600CTISTD : ProcResource<1>;
59 def P5600WriteJump : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>;
60 def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> {
64 // b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal,
66 def : ItinRW<[P5600WriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, II_JR,
67 II_JR_HB, II_DERET, II_ERET, II_ERETNC,
68 II_SYSCALL, II_BREAK, II_SDBBP, II_SSNOP,
69 II_TEQ, II_TEQI, II_TGE, II_TGEI, II_TGEIU,
70 II_TGEU, II_TLT, II_TLTI, II_TLTU, II_TNE,
71 II_TNEI, II_TRAP, II_TTLTIU, II_WAIT,
74 def : ItinRW<[P5600WriteJumpAndLink], [II_JAL, II_JALR, II_JALR_HB]>;
76 def P5600COP0 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>;
78 def : ItinRW<[P5600COP0], [II_TLBINV, II_TLBINVF, II_TLBP, II_TLBR, II_TLBWI,
79 II_TLBWR, II_MFC0, II_MTC0]>;
83 def P5600WriteLoad : SchedWriteRes<[P5600IssueLDST]> {
87 def P5600WriteLoadShifted : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
91 def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>;
93 def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
94 // FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2
95 // not during 0, 1, and 2.
96 let ResourceCycles = [ 1, 3 ];
99 def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> {
103 def P5600WriteStoreFromOtherUnits : SchedWriteRes<[P5600IssueLDST]>;
104 def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {
108 // l[bhw], l[bh]u, ll
109 def : ItinRW<[P5600WriteLoad], [II_LB, II_LBE, II_LBU, II_LBUE, II_LH, II_LHE,
110 II_LHU, II_LHUE, II_LW, II_LWE, II_LL, II_LLE,
114 def : ItinRW<[P5600WriteLoadShifted], [II_LWL, II_LWLE, II_LWR, II_LWRE]>;
117 def : ItinRW<[P5600WriteStore], [II_SB, II_SBE, II_SH, II_SHE, II_SW, II_SWE,
118 II_SWL, II_SWLE, II_SWR, II_SWRE, II_SC,
121 // pref, cache, sync, synci
122 def : ItinRW<[P5600WriteCache], [II_PREF, II_PREFE, II_CACHE, II_CACHEE,
125 // LDST is also used in moves from general purpose registers to floating point
127 def P5600WriteMoveGPRToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {
134 def P5600WriteAL2 : SchedWriteRes<[P5600IssueAL2]>;
135 def P5600WriteAL2BitExt : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
136 def P5600WriteAL2ShadowMov : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
137 def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
140 def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
141 // Estimated worst case
143 let ResourceCycles = [1, 34];
145 def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
146 // Estimated worst case
148 let ResourceCycles = [1, 34];
150 def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; }
151 def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; }
152 def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
156 // clo, clz, di, ei, mfhi, mflo
157 def : ItinRW<[P5600WriteAL2], [II_CLO, II_CLZ, II_DI, II_EI, II_MFHI_MFLO]>;
159 // ehb, rdhwr, rdpgpr, wrpgpr, wsbh
160 def : ItinRW<[P5600WriteAL2ShadowMov], [II_EHB, II_RDHWR, II_WSBH]>;
163 def : ItinRW<[P5600WriteAL2CondMov], [II_MOVN, II_MOVZ]>;
166 def : ItinRW<[P5600WriteAL2Div], [II_DIV]>;
167 def : ItinRW<[P5600WriteAL2DivU], [II_DIVU]>;
170 def : ItinRW<[P5600WriteAL2Mul], [II_MUL]>;
172 def : ItinRW<[P5600WriteAL2Mult], [II_MULT, II_MULTU]>;
173 // maddu?, msubu?, mthi, mtlo
174 def : ItinRW<[P5600WriteAL2MAdd],
175 [II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_MTHI_MTLO]>;
178 def : ItinRW<[P5600WriteAL2BitExt], [II_EXT, II_INS]>;
180 // Either ALU or AL2 Pipelines
181 // ---------------------------
183 // Some instructions can choose between ALU and AL2, but once dispatched to
184 // ALQ or AGQ respectively they are committed to that path.
185 // The decision is based on the outcome of the most recent selection when the
186 // choice was last available. For now, we assume ALU is always chosen.
188 def P5600WriteEitherALU : SchedWriteVariant<
189 // FIXME: Implement selection predicate
190 [SchedVar<SchedPredicate<[{1}]>, [P5600WriteALU]>,
191 SchedVar<SchedPredicate<[{0}]>, [P5600WriteAL2]>
194 // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu,
196 def : ItinRW<[P5600WriteEitherALU],
197 [II_ADD, II_ADDI, II_ADDIU, II_ANDI, II_ORI, II_ROTR, II_SEB, II_SEH,
198 II_SLT_SLTU, II_SLL, II_SRA, II_SRL, II_XORI, II_ADDU, II_SLLV,
199 II_SRAV, II_SRLV, II_LSA]>;
200 def : InstRW<[], (instrs COPY)>;
205 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
206 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
207 def P5600IssueFPUL : ProcResource<1> { let Super = P5600FPQ; }
208 def P5600IssueFPULoad : ProcResource<1> { let Super = P5600FPQ; }
210 def P5600FPUDivSqrt : ProcResource<2>;
212 def P5600WriteFPUS : SchedWriteRes<[P5600IssueFPUS]>;
213 def P5600WriteFPUL : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 4; }
214 def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6; }
215 def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
216 // Best/Common/Worst case = 7 / 23 / 27
217 let Latency = 23; // Using common case
218 let ResourceCycles = [ 1, 23 ];
220 def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
221 // Best/Common/Worst case = 7 / 23 / 27
222 let Latency = 23; // Using common case
223 let ResourceCycles = [ 1, 23 ];
225 def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
226 // Best/Common/Worst case = 7 / 31 / 35
227 let Latency = 31; // Using common case
228 let ResourceCycles = [ 1, 31 ];
230 def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
231 // Best/Common/Worst case = 7 / 19 / 23
232 let Latency = 19; // Using common case
233 let ResourceCycles = [ 1, 19 ];
235 def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
236 // Best/Common/Worst case = 7 / 27 / 31
237 let Latency = 27; // Using common case
238 let ResourceCycles = [ 1, 27 ];
240 def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
241 // Best/Common/Worst case = 7 / 27 / 27
242 let Latency = 27; // Using common case
243 let ResourceCycles = [ 1, 27 ];
245 def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
246 // Best/Common/Worst case = 7 / 27 / 31
247 let Latency = 27; // Using common case
248 let ResourceCycles = [ 1, 27 ];
250 def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
251 // Best/Common/Worst case = 7 / 27 / 31
252 let Latency = 27; // Using common case
253 let ResourceCycles = [ 1, 27 ];
255 def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
256 // Best/Common/Worst case = 7 / 35 / 39
257 let Latency = 35; // Using common case
258 let ResourceCycles = [ 1, 35 ];
260 def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>;
261 def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; }
262 def P5600WriteMoveOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPUS]>;
263 def P5600WriteMSAOther3 : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 3; }
264 def P5600WriteMSALongInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 5; }
266 // vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd],
267 // bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b
268 def : InstRW<[P5600WriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>;
269 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>;
270 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>;
271 def : InstRW<[P5600WriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>;
272 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>;
273 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>;
274 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>;
275 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>;
276 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>;
277 def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>;
279 // pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd]
280 def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>;
281 def : InstRW<[P5600WriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>;
283 // bnz.[bhwdv], cfcmsa, ctcmsa
284 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>;
285 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>;
287 // FPUS is also used in moves from floating point and MSA registers to general
288 // purpose registers.
289 def P5600WriteMoveFPUSToOtherUnits : SchedWriteRes<[P5600IssueFPUS]> {
293 // FPUL is also used in moves from floating point and MSA registers to general
294 // purpose registers.
295 def P5600WriteMoveFPULToOtherUnits : SchedWriteRes<[P5600IssueFPUL]>;
300 // abs.[ds], abs.ps, bc1[tf]l?, mov[tf].[ds], mov[tf], mov.[ds], [cm][ft]c1,
301 // m[ft]hc1, neg.[ds], neg.ps, nor.v, nori.b, or.v, ori.b, xor.v, xori.b,
302 // sdxc1, sdc1, st.[bhwd], swc1, swxc1
303 def : ItinRW<[P5600WriteFPUS], [II_ABS, II_MOVF_D, II_MOVF_S, II_MOVT_D,
304 II_MOVT_S, II_MOV_D, II_MOV_S, II_NEG]>;
306 // adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd],
307 // aver?_[us].[bhwd], shf.[bhw], fill[bhwd], splat?.[bhwd]
308 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>;
309 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>;
310 // TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it.
311 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>;
312 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>;
313 def : InstRW<[P5600WriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>;
314 def : InstRW<[P5600WriteMSAShortInt], (instregex "^SHF_[BHW]$")>;
315 def : InstRW<[P5600WriteMSAShortInt], (instregex "^FILL_[BHWD]$")>;
316 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>;
318 // and.v, andi.b, move.v, ldi.[bhwd]
319 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>;
320 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>;
321 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>;
322 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>;
324 // vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd],
325 // bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b
326 def : InstRW<[P5600WriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>;
327 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>;
328 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>;
329 def : InstRW<[P5600WriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>;
330 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>;
331 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>;
332 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>;
333 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>;
334 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>;
335 def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>;
337 // pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd]
338 def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>;
339 def : InstRW<[P5600WriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>;
342 def : InstRW<[P5600WriteFPUS], (instregex "^FEXP2_(W|D)$")>;
344 // compare, converts, round to int, floating point truncate.
345 def : InstRW<[P5600WriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>;
346 def : InstRW<[P5600WriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>;
347 def : InstRW<[P5600WriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>;
348 def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UN_(S|D)$")>;
349 def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>;
350 def : InstRW<[P5600WriteFPUS], (instregex "^CMP_EQ_(S|D)$")>;
351 def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LT_(S|D)$")>;
352 def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULT_(S|D)$")>;
353 def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LE_(S|D)$")>;
354 def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULE_(S|D)$")>;
355 def : InstRW<[P5600WriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>;
356 def : InstRW<[P5600WriteFPUS], (instregex "^FSUEQ_(W|D)$")>;
357 def : InstRW<[P5600WriteFPUS], (instregex "^FSULE_(W|D)$")>;
358 def : InstRW<[P5600WriteFPUS], (instregex "^FSULT_(W|D)$")>;
359 def : InstRW<[P5600WriteFPUS], (instregex "^FSUNE_(W|D)$")>;
360 def : InstRW<[P5600WriteFPUS], (instregex "^FSUN_(W|D)$")>;
361 def : InstRW<[P5600WriteFPUS], (instregex "^FCAF_(W|D)$")>;
362 def : InstRW<[P5600WriteFPUS], (instregex "^FCEQ_(W|D)$")>;
363 def : InstRW<[P5600WriteFPUS], (instregex "^FCLE_(W|D)$")>;
364 def : InstRW<[P5600WriteFPUS], (instregex "^FCLT_(W|D)$")>;
365 def : InstRW<[P5600WriteFPUS], (instregex "^FCNE_(W|D)$")>;
366 def : InstRW<[P5600WriteFPUS], (instregex "^FCOR_(W|D)$")>;
367 def : InstRW<[P5600WriteFPUS], (instregex "^FCUEQ_(W|D)$")>;
368 def : InstRW<[P5600WriteFPUS], (instregex "^FCULE_(W|D)$")>;
369 def : InstRW<[P5600WriteFPUS], (instregex "^FCULT_(W|D)$")>;
370 def : InstRW<[P5600WriteFPUS], (instregex "^FCUNE_(W|D)$")>;
371 def : InstRW<[P5600WriteFPUS], (instregex "^FCUN_(W|D)$")>;
372 def : InstRW<[P5600WriteFPUS], (instregex "^FABS_(W|D)$")>;
373 def : InstRW<[P5600WriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>;
374 def : InstRW<[P5600WriteFPUS], (instregex "^FFQL_(W|D)$")>;
375 def : InstRW<[P5600WriteFPUS], (instregex "^FFQR_(W|D)$")>;
376 def : InstRW<[P5600WriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>;
377 def : InstRW<[P5600WriteFPUS], (instregex "^FRINT_(W|D)$")>;
378 def : InstRW<[P5600WriteFPUS], (instregex "^FTQ_(H|W)$")>;
379 def : InstRW<[P5600WriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>;
381 // fexdo.[hw], fexupl.[wd], fexupr.[wd]
382 def : InstRW<[P5600WriteFPUS], (instregex "^FEXDO_(H|W)$")>;
383 def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPL_(W|D)$")>;
384 def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPR_(W|D)$")>;
386 // fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd]
387 def : InstRW<[P5600WriteFPUS], (instregex "^FCLASS_(W|D)$")>;
388 def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_A_(W|D)$")>;
389 def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_(W|D)$")>;
390 def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_A_(W|D)$")>;
391 def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_(W|D)$")>;
392 def : InstRW<[P5600WriteFPUS], (instregex "^FLOG2_(W|D)$")>;
394 // interleave right/left, interleave even/odd, insert
395 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>;
396 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>;
397 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>;
399 // subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd],
400 def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>;
401 def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>;
402 def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>;
403 def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>;
404 def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>;
406 // mod_[su].[bhwd], div_[su].[bhwd]
407 def : InstRW<[P5600WriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>;
408 def : InstRW<[P5600WriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>;
410 // hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd],
411 // maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd],
412 // sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd],
414 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>;
415 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>;
416 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>;
417 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>;
418 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>;
419 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>;
420 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>;
421 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
422 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>;
423 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>;
424 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
425 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>;
426 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>;
427 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>;
432 // add.[ds], add.ps, cvt.d.[sw], cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps,
433 // cvt.ps.[sw], c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, sub.[ds], sub.ps,
434 // trunc.w.[ds], trunc.w.ps
435 def : ItinRW<[P5600WriteFPUL],
436 [II_ADD_D, II_ADD_S, II_CVT, II_C_CC_D, II_C_CC_S, II_MUL_D,
437 II_MUL_S, II_SUB_D, II_SUB_S, II_TRUNC]>;
440 def : ItinRW<[P5600WriteFPUDivS], [II_DIV_S]>;
441 def : ItinRW<[P5600WriteFPUDivD], [II_DIV_D]>;
443 // sqrt.[ds], sqrt.ps
444 def : ItinRW<[P5600WriteFPUSqrtS], [II_SQRT_S]>;
445 def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>;
447 // frcp.[wd], frsqrt.[wd]
448 def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>;
449 def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>;
451 def : ItinRW<[P5600WriteFPURsqrtD], [II_RECIP_D, II_RSQRT_D]>;
452 def : ItinRW<[P5600WriteFPURsqrtS], [II_RECIP_S, II_RSQRT_S]>;
454 // fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd],
456 def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>;
457 def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMSUB_(W|D)$")>;
458 def : InstRW<[P5600WriteFPUDivS], (instregex "^FDIV_W$")>;
459 def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>;
460 def : InstRW<[P5600WriteFPUSqrtS], (instregex "^FSQRT_W$")>;
461 def : InstRW<[P5600WriteFPUSqrtD], (instregex "^FSQRT_D$")>;
462 def : InstRW<[P5600WriteFPUL], (instregex "^FMUL_(W|D)$")>;
463 def : InstRW<[P5600WriteFPUL], (instregex "^FADD_(W|D)$")>;
464 def : InstRW<[P5600WriteFPUL], (instregex "^FSUB_(W|D)$")>;
466 // dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd]
468 def : InstRW<[P5600WriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>;
469 def : InstRW<[P5600WriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>;
470 def : InstRW<[P5600WriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>;
471 def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>;
472 def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDV_[BHWD]$")>;
473 def : InstRW<[P5600WriteMSALongInt], (instregex "^MULV_[BHWD]$")>;
475 def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>;
476 def : InstRW<[P5600WriteMSALongInt], (instregex "^MADD_Q_[HW]$")>;
477 def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>;
478 def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>;
479 def : InstRW<[P5600WriteMSALongInt], (instregex "^MULR_Q_[HW]$")>;
480 def : InstRW<[P5600WriteMSALongInt], (instregex "^MUL_Q_[HW]$")>;
482 // madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds],
483 // Operand 0 is read on cycle 5. All other operands are read on operand 0.
484 def : ItinRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB],
485 [II_MADD_D, II_MADD_S, II_MSUB_D, II_MSUB_S, II_NMADD_D,
486 II_NMADD_S, II_NMSUB_D, II_NMSUB_S]>;
488 // madd.ps, msub.ps, nmadd.ps, nmsub.ps
489 // Operand 0 and 1 are read on cycle 5. All others are read on operand 0.
490 // (none of these instructions exist in the backend yet)
495 // This is typically used in conjunction with the load pipeline under the AGQ
496 // All the instructions are in the 'Tricky Instructions' section.
498 def P5600WriteLoadOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPULoad]> {
502 // Tricky Instructions
503 // ===================
505 // These instructions are split across multiple uops (in different pipelines)
506 // that must cooperate to complete the operation
508 // FIXME: This isn't quite right since the implementation of WriteSequence
509 // current aggregates the resources and ignores the exact cycle they are
511 def P5600WriteMoveGPRToFPU : WriteSequence<[P5600WriteMoveGPRToOtherUnits,
512 P5600WriteMoveOtherUnitsToFPU]>;
514 // FIXME: This isn't quite right since the implementation of WriteSequence
515 // current aggregates the resources and ignores the exact cycle they are
517 def P5600WriteMoveFPUToGPR : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
518 P5600WriteGPRFromBypass]>;
520 // FIXME: This isn't quite right since the implementation of WriteSequence
521 // current aggregates the resources and ignores the exact cycle they are
523 def P5600WriteStoreFPUS : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
524 P5600WriteStoreFromOtherUnits]>;
526 // FIXME: This isn't quite right since the implementation of WriteSequence
527 // current aggregates the resources and ignores the exact cycle they are
529 def P5600WriteStoreFPUL : WriteSequence<[P5600WriteMoveFPULToOtherUnits,
530 P5600WriteStoreFromOtherUnits]>;
532 // FIXME: This isn't quite right since the implementation of WriteSequence
533 // current aggregates the resources and ignores the exact cycle they are
535 def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits,
536 P5600WriteLoadOtherUnitsToFPU]>;
539 def : ItinRW<[P5600WriteMoveGPRToFPU], [II_CTC1, II_MTC1, II_MTHC1]>;
542 def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_U_[BHW]$")>;
543 def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_S_[BHWD]$")>;
545 // bc1[ft], cfc1, mfc1, mfhc1, movf, movt
546 def : ItinRW<[P5600WriteMoveFPUToGPR],
547 [II_BC1F, II_BC1FL, II_BC1T, II_BC1TL, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
549 // swc1, swxc1, st.[bhwd]
550 def : ItinRW<[P5600WriteStoreFPUS], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1,
552 def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>;
554 // movn.[ds], movz.[ds]
555 def : ItinRW<[P5600WriteStoreFPUL], [II_MOVN_D, II_MOVN_S, II_MOVZ_D, II_MOVZ_S]>;
557 // l[dw]x?c1, ld.[bhwd]
558 def : ItinRW<[P5600WriteLoadFPU], [II_LDC1, II_LDXC1, II_LWC1, II_LWXC1, II_LUXC1]>;
559 def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>;
561 // Unsupported Instructions
562 // ========================
564 // The following instruction classes are never valid on P5600.
565 // II_DADDIU, II_DADDU, II_DMFC1, II_DMTC1, II_DMULT, II_DMULTU, II_DROTR,
566 // II_DROTR32, II_DROTRV, II_DDIV, II_DSLL, II_DSLL32, II_DSLLV, II_DSRA,
567 // II_DSRA32, II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, II_DSUBU, II_DDIVU,
568 // II_JALRC, II_LD, II_LD[LR], II_RESTORE, II_SAVE, II_SD, II_SDC1, II_SD[LR]
570 // The following instructions are never valid on P5600.
571 // addq.ph, repl.ph, repl.qb, subq.ph, subu_s.qb
576 // This section is largely temporary guesswork.
578 // ceil.[lw].[ds], floor.[lw].[ds]
579 // Reason behind guess: trunc.[lw].ds and the various cvt's are in FPUL
580 def : ItinRW<[P5600WriteFPUL], [II_CEIL, II_FLOOR, II_ROUND]>;
583 // Reason behind guess: rotr is in the same category and the two register forms
584 // generally follow the immediate forms in this category
585 def : ItinRW<[P5600WriteEitherALU], [II_ROTRV]>;