1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSubtarget.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
37 Mixed16_32("mips-mixed-16-32", cl::init(false),
38 cl::desc("Allow for a mixture of Mips16 "
39 "and Mips32 code in a single output file"),
42 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
43 cl::desc("Compile all functions that don't use "
44 "floating point as Mips 16"),
47 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
48 cl::desc("Enable mips16 hard float."),
52 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
53 cl::desc("Enable mips16 constant islands."),
57 GPOpt("mgpopt", cl::Hidden,
58 cl::desc("Enable gp-relative addressing of mips small data items"));
60 void MipsSubtarget::anchor() { }
62 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
63 bool little, const MipsTargetMachine &TM)
64 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
65 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
66 NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
67 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
68 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
69 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
70 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
71 HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
72 Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
73 HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM),
74 TargetTriple(TT), TSInfo(),
76 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
77 FrameLowering(MipsFrameLowering::create(*this)),
78 TLInfo(MipsTargetLowering::create(TM, *this)) {
80 if (MipsArchVersion == MipsDefault)
81 MipsArchVersion = Mips32;
83 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
84 // been tested and currently exist for the integrated assembler only.
85 if (MipsArchVersion == Mips1)
86 report_fatal_error("Code generation for MIPS-I is not implemented", false);
87 if (MipsArchVersion == Mips5)
88 report_fatal_error("Code generation for MIPS-V is not implemented", false);
90 // Check if Architecture and ABI are compatible.
91 assert(((!isGP64bit() && isABI_O32()) ||
92 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
93 "Invalid Arch & ABI pair.");
95 if (hasMSA() && !isFP64bit())
96 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
100 if (!isABI_O32() && !useOddSPReg())
101 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
103 if (IsFPXX && (isABI_N32() || isABI_N64()))
104 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
107 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
112 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
115 if (NoABICalls && TM.isPositionIndependent())
116 report_fatal_error("position-independent code requires '-mabicalls'");
118 if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
121 // Set UseSmallSection.
122 UseSmallSection = GPOpt;
123 if (!NoABICalls && GPOpt) {
124 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
126 UseSmallSection = false;
130 bool MipsSubtarget::isPositionIndependent() const {
131 return TM.isPositionIndependent();
134 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
135 bool MipsSubtarget::enablePostRAScheduler() const { return true; }
137 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
138 CriticalPathRCs.clear();
139 CriticalPathRCs.push_back(isGP64bit() ?
140 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
143 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
144 return CodeGenOpt::Aggressive;
148 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
149 const TargetMachine &TM) {
150 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
152 // Parse features string.
153 ParseSubtargetFeatures(CPUName, FS);
154 // Initialize scheduling itinerary for the specified CPU.
155 InstrItins = getInstrItineraryForCPU(CPUName);
157 if (InMips16Mode && !IsSoftFloat)
158 InMips16HardFloat = true;
163 bool MipsSubtarget::useConstantIslands() {
164 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
165 return Mips16ConstantIslands;
168 Reloc::Model MipsSubtarget::getRelocationModel() const {
169 return TM.getRelocationModel();
172 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
173 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
174 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
175 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }