1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Support/ErrorHandling.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
41 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
45 enum class CPU { P5600 };
47 // Mips architecture version
48 MipsArchEnum MipsArchVersion;
50 // Processor implementation (unused but required to exist by
51 // tablegen-erated code).
54 // IsLittle - The target is Little Endian
57 // IsSoftFloat - The target does not support any floating point instructions.
60 // IsSingleFloat - The target only supports single precision float
61 // point operations. This enable the target to use all 32 32-bit
62 // floating point registers instead of only using even ones.
65 // IsFPXX - MIPS O32 modeless ABI.
68 // NoABICalls - Disable SVR4-style position-independent code.
71 // IsFP64bit - The target processor has 64-bit floating point registers.
74 /// Are odd single-precision registers permitted?
75 /// This corresponds to -modd-spreg and -mno-odd-spreg
78 // IsNan2008 - IEEE 754-2008 NaN encoding.
81 // IsGP64bit - General-purpose registers are 64 bits wide
84 // IsPTR64bit - Pointers are 64 bit wide
87 // HasVFPU - Processor has a vector floating point unit.
90 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
93 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
96 // UseSmallSection - Small section is used.
99 /// Features related to the presence of specific instructions.
101 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
104 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
107 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
110 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
113 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
116 // InMips16 -- can process Mips16 instructions
120 bool InMips16HardFloat;
122 // InMicroMips -- can process MicroMips instructions
123 bool InMicroMipsMode;
125 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
126 bool HasDSP, HasDSPR2, HasDSPR3;
128 // Allow mixed Mips16 and Mips32 in one source file
129 bool AllowMixed16_32;
131 // Optimize for space by compiling all functions as Mips 16 unless
132 // it needs floating point. Functions needing floating point are
133 // compiled as Mips32
136 // HasMSA -- supports MSA ASE.
139 // UseTCCInDIV -- Enables the use of trapping in the assembler.
142 // Sym32 -- On Mips64 symbols are 32 bits.
145 // HasEVA -- supports EVA ASE.
148 // nomadd4 - disables generation of 4-operand madd.s, madd.d and
149 // related instructions.
152 // HasMT -- support MT ASE.
155 // Disable use of the `jal` instruction.
156 bool UseLongCalls = false;
158 /// The minimum alignment known to hold of the stack frame on
159 /// entry to the function and which must be maintained by every function.
160 unsigned stackAlignment;
162 /// The overridden stack alignment.
163 unsigned StackAlignOverride;
165 InstrItineraryData InstrItins;
167 // We can override the determination of whether we are in mips16 mode
168 // as from the command line
169 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
171 const MipsTargetMachine &TM;
175 const SelectionDAGTargetInfo TSInfo;
176 std::unique_ptr<const MipsInstrInfo> InstrInfo;
177 std::unique_ptr<const MipsFrameLowering> FrameLowering;
178 std::unique_ptr<const MipsTargetLowering> TLInfo;
181 bool isPositionIndependent() const;
182 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
183 bool enablePostRAScheduler() const override;
184 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
185 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
187 bool isABI_N64() const;
188 bool isABI_N32() const;
189 bool isABI_O32() const;
190 const MipsABIInfo &getABI() const;
191 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
193 /// This constructor initializes the data members to match that
194 /// of the specified triple.
195 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
196 const MipsTargetMachine &TM, unsigned StackAlignOverride);
198 /// ParseSubtargetFeatures - Parses features string setting specified
199 /// subtarget options. Definition of function is auto generated by tblgen.
200 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
202 bool hasMips1() const { return MipsArchVersion >= Mips1; }
203 bool hasMips2() const { return MipsArchVersion >= Mips2; }
204 bool hasMips3() const { return MipsArchVersion >= Mips3; }
205 bool hasMips4() const { return MipsArchVersion >= Mips4; }
206 bool hasMips5() const { return MipsArchVersion >= Mips5; }
207 bool hasMips4_32() const { return HasMips4_32; }
208 bool hasMips4_32r2() const { return HasMips4_32r2; }
209 bool hasMips32() const {
210 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
213 bool hasMips32r2() const {
214 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
217 bool hasMips32r3() const {
218 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
221 bool hasMips32r5() const {
222 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
225 bool hasMips32r6() const {
226 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
229 bool hasMips64() const { return MipsArchVersion >= Mips64; }
230 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
231 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
232 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
233 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
235 bool hasCnMips() const { return HasCnMips; }
237 bool isLittle() const { return IsLittle; }
238 bool isABICalls() const { return !NoABICalls; }
239 bool isFPXX() const { return IsFPXX; }
240 bool isFP64bit() const { return IsFP64bit; }
241 bool useOddSPReg() const { return UseOddSPReg; }
242 bool noOddSPReg() const { return !UseOddSPReg; }
243 bool isNaN2008() const { return IsNaN2008bit; }
244 bool isGP64bit() const { return IsGP64bit; }
245 bool isGP32bit() const { return !IsGP64bit; }
246 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
247 bool isPTR64bit() const { return IsPTR64bit; }
248 bool isPTR32bit() const { return !IsPTR64bit; }
249 bool hasSym32() const {
250 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
252 bool isSingleFloat() const { return IsSingleFloat; }
253 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
254 bool hasVFPU() const { return HasVFPU; }
255 bool inMips16Mode() const { return InMips16Mode; }
256 bool inMips16ModeDefault() const {
259 // Hard float for mips16 means essentially to compile as soft float
260 // but to use a runtime library for soft float that is written with
261 // native mips32 floating point instructions (those runtime routines
262 // run in mips32 hard float mode).
263 bool inMips16HardFloat() const {
264 return inMips16Mode() && InMips16HardFloat;
266 bool inMicroMipsMode() const { return InMicroMipsMode; }
267 bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
268 bool hasDSP() const { return HasDSP; }
269 bool hasDSPR2() const { return HasDSPR2; }
270 bool hasDSPR3() const { return HasDSPR3; }
271 bool hasMSA() const { return HasMSA; }
272 bool disableMadd4() const { return DisableMadd4; }
273 bool hasEVA() const { return HasEVA; }
274 bool hasMT() const { return HasMT; }
275 bool useSmallSection() const { return UseSmallSection; }
277 bool hasStandardEncoding() const { return !inMips16Mode(); }
279 bool useSoftFloat() const { return IsSoftFloat; }
281 bool useLongCalls() const { return UseLongCalls; }
283 bool enableLongBranchPass() const {
284 return hasStandardEncoding() || allowMixed16_32();
287 /// Features related to the presence of specific instructions.
288 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
289 bool hasMTHC1() const { return hasMips32r2(); }
291 bool allowMixed16_32() const { return inMips16ModeDefault() |
294 bool os16() const { return Os16; }
296 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
298 bool isXRaySupported() const override { return true; }
300 // for now constant islands are on for the whole compilation unit but we only
301 // really use them if in addition we are in mips16 mode
302 static bool useConstantIslands();
304 unsigned getStackAlignment() const { return stackAlignment; }
306 // Grab relocation model
307 Reloc::Model getRelocationModel() const;
309 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
310 const TargetMachine &TM);
312 /// Does the system support unaligned memory access.
314 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
315 /// specify which component of the system provides it. Hardware, software, and
316 /// hybrid implementations are all valid.
317 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
319 // Set helper classes
320 void setHelperClassesMips16();
321 void setHelperClassesMipsSE();
323 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
326 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
327 const TargetFrameLowering *getFrameLowering() const override {
328 return FrameLowering.get();
330 const MipsRegisterInfo *getRegisterInfo() const override {
331 return &InstrInfo->getRegisterInfo();
333 const MipsTargetLowering *getTargetLowering() const override {
336 const InstrItineraryData *getInstrItineraryData() const override {
340 } // End llvm namespace