1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
26 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/MC/MCInstrItineraries.h"
29 #include "llvm/Support/ErrorHandling.h"
32 #define GET_SUBTARGETINFO_HEADER
33 #include "MipsGenSubtargetInfo.inc"
38 class MipsTargetMachine;
40 class MipsSubtarget : public MipsGenSubtargetInfo {
41 virtual void anchor();
45 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
46 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
49 enum class CPU { P5600 };
51 // Used to avoid printing dsp warnings multiple times.
52 static bool DspWarningPrinted;
54 // Used to avoid printing msa warnings multiple times.
55 static bool MSAWarningPrinted;
57 // Used to avoid printing crc warnings multiple times.
58 static bool CRCWarningPrinted;
60 // Used to avoid printing ginv warnings multiple times.
61 static bool GINVWarningPrinted;
63 // Used to avoid printing virt warnings multiple times.
64 static bool VirtWarningPrinted;
66 // Mips architecture version
67 MipsArchEnum MipsArchVersion;
69 // Processor implementation (unused but required to exist by
70 // tablegen-erated code).
73 // IsLittle - The target is Little Endian
76 // IsSoftFloat - The target does not support any floating point instructions.
79 // IsSingleFloat - The target only supports single precision float
80 // point operations. This enable the target to use all 32 32-bit
81 // floating point registers instead of only using even ones.
84 // IsFPXX - MIPS O32 modeless ABI.
87 // NoABICalls - Disable SVR4-style position-independent code.
90 // IsFP64bit - The target processor has 64-bit floating point registers.
93 /// Are odd single-precision registers permitted?
94 /// This corresponds to -modd-spreg and -mno-odd-spreg
97 // IsNan2008 - IEEE 754-2008 NaN encoding.
100 // IsGP64bit - General-purpose registers are 64 bits wide
103 // IsPTR64bit - Pointers are 64 bit wide
106 // HasVFPU - Processor has a vector floating point unit.
109 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
112 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
115 // UseSmallSection - Small section is used.
116 bool UseSmallSection;
118 /// Features related to the presence of specific instructions.
120 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
123 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
126 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
129 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
132 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
135 // InMips16 -- can process Mips16 instructions
139 bool InMips16HardFloat;
141 // InMicroMips -- can process MicroMips instructions
142 bool InMicroMipsMode;
144 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
145 bool HasDSP, HasDSPR2, HasDSPR3;
147 // Allow mixed Mips16 and Mips32 in one source file
148 bool AllowMixed16_32;
150 // Optimize for space by compiling all functions as Mips 16 unless
151 // it needs floating point. Functions needing floating point are
152 // compiled as Mips32
155 // HasMSA -- supports MSA ASE.
158 // UseTCCInDIV -- Enables the use of trapping in the assembler.
161 // Sym32 -- On Mips64 symbols are 32 bits.
164 // HasEVA -- supports EVA ASE.
167 // nomadd4 - disables generation of 4-operand madd.s, madd.d and
168 // related instructions.
171 // HasMT -- support MT ASE.
174 // HasCRC -- supports R6 CRC ASE
177 // HasVirt -- supports Virtualization ASE
180 // HasGINV -- supports R6 Global INValidate ASE
183 // Use hazard variants of the jump register instructions for indirect
184 // function calls and jump tables.
185 bool UseIndirectJumpsHazard;
187 // Disable use of the `jal` instruction.
188 bool UseLongCalls = false;
190 /// The minimum alignment known to hold of the stack frame on
191 /// entry to the function and which must be maintained by every function.
192 unsigned stackAlignment;
194 /// The overridden stack alignment.
195 unsigned StackAlignOverride;
197 InstrItineraryData InstrItins;
199 // We can override the determination of whether we are in mips16 mode
200 // as from the command line
201 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
203 const MipsTargetMachine &TM;
207 const SelectionDAGTargetInfo TSInfo;
208 std::unique_ptr<const MipsInstrInfo> InstrInfo;
209 std::unique_ptr<const MipsFrameLowering> FrameLowering;
210 std::unique_ptr<const MipsTargetLowering> TLInfo;
213 bool isPositionIndependent() const;
214 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
215 bool enablePostRAScheduler() const override;
216 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
217 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
219 bool isABI_N64() const;
220 bool isABI_N32() const;
221 bool isABI_O32() const;
222 const MipsABIInfo &getABI() const;
223 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
225 /// This constructor initializes the data members to match that
226 /// of the specified triple.
227 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
228 const MipsTargetMachine &TM, unsigned StackAlignOverride);
230 /// ParseSubtargetFeatures - Parses features string setting specified
231 /// subtarget options. Definition of function is auto generated by tblgen.
232 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
234 bool hasMips1() const { return MipsArchVersion >= Mips1; }
235 bool hasMips2() const { return MipsArchVersion >= Mips2; }
236 bool hasMips3() const { return MipsArchVersion >= Mips3; }
237 bool hasMips4() const { return MipsArchVersion >= Mips4; }
238 bool hasMips5() const { return MipsArchVersion >= Mips5; }
239 bool hasMips4_32() const { return HasMips4_32; }
240 bool hasMips4_32r2() const { return HasMips4_32r2; }
241 bool hasMips32() const {
242 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
245 bool hasMips32r2() const {
246 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
249 bool hasMips32r3() const {
250 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
253 bool hasMips32r5() const {
254 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
257 bool hasMips32r6() const {
258 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
261 bool hasMips64() const { return MipsArchVersion >= Mips64; }
262 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
263 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
264 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
265 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
267 bool hasCnMips() const { return HasCnMips; }
269 bool isLittle() const { return IsLittle; }
270 bool isABICalls() const { return !NoABICalls; }
271 bool isFPXX() const { return IsFPXX; }
272 bool isFP64bit() const { return IsFP64bit; }
273 bool useOddSPReg() const { return UseOddSPReg; }
274 bool noOddSPReg() const { return !UseOddSPReg; }
275 bool isNaN2008() const { return IsNaN2008bit; }
276 bool isGP64bit() const { return IsGP64bit; }
277 bool isGP32bit() const { return !IsGP64bit; }
278 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
279 bool isPTR64bit() const { return IsPTR64bit; }
280 bool isPTR32bit() const { return !IsPTR64bit; }
281 bool hasSym32() const {
282 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
284 bool isSingleFloat() const { return IsSingleFloat; }
285 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
286 bool hasVFPU() const { return HasVFPU; }
287 bool inMips16Mode() const { return InMips16Mode; }
288 bool inMips16ModeDefault() const {
291 // Hard float for mips16 means essentially to compile as soft float
292 // but to use a runtime library for soft float that is written with
293 // native mips32 floating point instructions (those runtime routines
294 // run in mips32 hard float mode).
295 bool inMips16HardFloat() const {
296 return inMips16Mode() && InMips16HardFloat;
298 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
299 bool inMicroMips32r6Mode() const {
300 return inMicroMipsMode() && hasMips32r6();
302 bool hasDSP() const { return HasDSP; }
303 bool hasDSPR2() const { return HasDSPR2; }
304 bool hasDSPR3() const { return HasDSPR3; }
305 bool hasMSA() const { return HasMSA; }
306 bool disableMadd4() const { return DisableMadd4; }
307 bool hasEVA() const { return HasEVA; }
308 bool hasMT() const { return HasMT; }
309 bool hasCRC() const { return HasCRC; }
310 bool hasVirt() const { return HasVirt; }
311 bool hasGINV() const { return HasGINV; }
312 bool useIndirectJumpsHazard() const {
313 return UseIndirectJumpsHazard && hasMips32r2();
315 bool useSmallSection() const { return UseSmallSection; }
317 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
319 bool useSoftFloat() const { return IsSoftFloat; }
321 bool useLongCalls() const { return UseLongCalls; }
323 bool enableLongBranchPass() const {
324 return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
327 /// Features related to the presence of specific instructions.
328 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
329 bool hasMTHC1() const { return hasMips32r2(); }
331 bool allowMixed16_32() const { return inMips16ModeDefault() |
334 bool os16() const { return Os16; }
336 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
338 bool isXRaySupported() const override { return true; }
340 // for now constant islands are on for the whole compilation unit but we only
341 // really use them if in addition we are in mips16 mode
342 static bool useConstantIslands();
344 unsigned getStackAlignment() const { return stackAlignment; }
346 // Grab relocation model
347 Reloc::Model getRelocationModel() const;
349 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
350 const TargetMachine &TM);
352 /// Does the system support unaligned memory access.
354 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
355 /// specify which component of the system provides it. Hardware, software, and
356 /// hybrid implementations are all valid.
357 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
359 // Set helper classes
360 void setHelperClassesMips16();
361 void setHelperClassesMipsSE();
363 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
366 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
367 const TargetFrameLowering *getFrameLowering() const override {
368 return FrameLowering.get();
370 const MipsRegisterInfo *getRegisterInfo() const override {
371 return &InstrInfo->getRegisterInfo();
373 const MipsTargetLowering *getTargetLowering() const override {
376 const InstrItineraryData *getInstrItineraryData() const override {
381 // GlobalISel related APIs.
382 std::unique_ptr<CallLowering> CallLoweringInfo;
383 std::unique_ptr<LegalizerInfo> Legalizer;
384 std::unique_ptr<RegisterBankInfo> RegBankInfo;
385 std::unique_ptr<InstructionSelector> InstSelector;
388 const CallLowering *getCallLowering() const override;
389 const LegalizerInfo *getLegalizerInfo() const override;
390 const RegisterBankInfo *getRegBankInfo() const override;
391 const InstructionSelector *getInstructionSelector() const override;
393 } // End llvm namespace