1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
41 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
45 enum class CPU { P5600 };
47 // Mips architecture version
48 MipsArchEnum MipsArchVersion;
50 // Processor implementation (unused but required to exist by
51 // tablegen-erated code).
54 // IsLittle - The target is Little Endian
57 // IsSoftFloat - The target does not support any floating point instructions.
60 // IsSingleFloat - The target only supports single precision float
61 // point operations. This enable the target to use all 32 32-bit
62 // floating point registers instead of only using even ones.
65 // IsFPXX - MIPS O32 modeless ABI.
68 // NoABICalls - Disable SVR4-style position-independent code.
71 // IsFP64bit - The target processor has 64-bit floating point registers.
74 /// Are odd single-precision registers permitted?
75 /// This corresponds to -modd-spreg and -mno-odd-spreg
78 // IsNan2008 - IEEE 754-2008 NaN encoding.
81 // IsFP64bit - General-purpose registers are 64 bits wide
84 // IsPTR64bit - Pointers are 64 bit wide
87 // HasVFPU - Processor has a vector floating point unit.
90 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
93 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
96 // UseSmallSection - Small section is used.
99 /// Features related to the presence of specific instructions.
101 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
104 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
107 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
110 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
113 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
116 // InMips16 -- can process Mips16 instructions
120 bool InMips16HardFloat;
122 // InMicroMips -- can process MicroMips instructions
123 bool InMicroMipsMode;
125 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
126 bool HasDSP, HasDSPR2, HasDSPR3;
128 // Allow mixed Mips16 and Mips32 in one source file
129 bool AllowMixed16_32;
131 // Optimize for space by compiling all functions as Mips 16 unless
132 // it needs floating point. Functions needing floating point are
133 // compiled as Mips32
136 // HasMSA -- supports MSA ASE.
139 // UseTCCInDIV -- Enables the use of trapping in the assembler.
142 // Sym32 -- On Mips64 symbols are 32 bits.
145 // HasEVA -- supports EVA ASE.
148 InstrItineraryData InstrItins;
150 // We can override the determination of whether we are in mips16 mode
151 // as from the command line
152 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
154 const MipsTargetMachine &TM;
158 const SelectionDAGTargetInfo TSInfo;
159 std::unique_ptr<const MipsInstrInfo> InstrInfo;
160 std::unique_ptr<const MipsFrameLowering> FrameLowering;
161 std::unique_ptr<const MipsTargetLowering> TLInfo;
164 bool isPositionIndependent() const;
165 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
166 bool enablePostRAScheduler() const override;
167 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
168 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
170 bool isABI_N64() const;
171 bool isABI_N32() const;
172 bool isABI_O32() const;
173 const MipsABIInfo &getABI() const;
174 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
176 /// This constructor initializes the data members to match that
177 /// of the specified triple.
178 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
179 const MipsTargetMachine &TM);
181 /// ParseSubtargetFeatures - Parses features string setting specified
182 /// subtarget options. Definition of function is auto generated by tblgen.
183 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
185 bool hasMips1() const { return MipsArchVersion >= Mips1; }
186 bool hasMips2() const { return MipsArchVersion >= Mips2; }
187 bool hasMips3() const { return MipsArchVersion >= Mips3; }
188 bool hasMips4() const { return MipsArchVersion >= Mips4; }
189 bool hasMips5() const { return MipsArchVersion >= Mips5; }
190 bool hasMips4_32() const { return HasMips4_32; }
191 bool hasMips4_32r2() const { return HasMips4_32r2; }
192 bool hasMips32() const {
193 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
196 bool hasMips32r2() const {
197 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
200 bool hasMips32r3() const {
201 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
204 bool hasMips32r5() const {
205 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
208 bool hasMips32r6() const {
209 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
212 bool hasMips64() const { return MipsArchVersion >= Mips64; }
213 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
214 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
215 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
216 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
218 bool hasCnMips() const { return HasCnMips; }
220 bool isLittle() const { return IsLittle; }
221 bool isABICalls() const { return !NoABICalls; }
222 bool isFPXX() const { return IsFPXX; }
223 bool isFP64bit() const { return IsFP64bit; }
224 bool useOddSPReg() const { return UseOddSPReg; }
225 bool noOddSPReg() const { return !UseOddSPReg; }
226 bool isNaN2008() const { return IsNaN2008bit; }
227 bool isGP64bit() const { return IsGP64bit; }
228 bool isGP32bit() const { return !IsGP64bit; }
229 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
230 bool isPTR64bit() const { return IsPTR64bit; }
231 bool isPTR32bit() const { return !IsPTR64bit; }
232 bool hasSym32() const {
233 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
235 bool isSingleFloat() const { return IsSingleFloat; }
236 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
237 bool hasVFPU() const { return HasVFPU; }
238 bool inMips16Mode() const { return InMips16Mode; }
239 bool inMips16ModeDefault() const {
242 // Hard float for mips16 means essentially to compile as soft float
243 // but to use a runtime library for soft float that is written with
244 // native mips32 floating point instructions (those runtime routines
245 // run in mips32 hard float mode).
246 bool inMips16HardFloat() const {
247 return inMips16Mode() && InMips16HardFloat;
249 bool inMicroMipsMode() const { return InMicroMipsMode; }
250 bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
251 bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
252 bool hasDSP() const { return HasDSP; }
253 bool hasDSPR2() const { return HasDSPR2; }
254 bool hasDSPR3() const { return HasDSPR3; }
255 bool hasMSA() const { return HasMSA; }
256 bool hasEVA() const { return HasEVA; }
257 bool useSmallSection() const { return UseSmallSection; }
259 bool hasStandardEncoding() const { return !inMips16Mode(); }
261 bool useSoftFloat() const { return IsSoftFloat; }
263 bool enableLongBranchPass() const {
264 return hasStandardEncoding() || allowMixed16_32();
267 /// Features related to the presence of specific instructions.
268 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
269 bool hasMTHC1() const { return hasMips32r2(); }
271 bool allowMixed16_32() const { return inMips16ModeDefault() |
274 bool os16() const { return Os16; }
276 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
278 bool isXRaySupported() const override { return true; }
280 // for now constant islands are on for the whole compilation unit but we only
281 // really use them if in addition we are in mips16 mode
282 static bool useConstantIslands();
284 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
286 // Grab relocation model
287 Reloc::Model getRelocationModel() const;
289 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
290 const TargetMachine &TM);
292 /// Does the system support unaligned memory access.
294 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
295 /// specify which component of the system provides it. Hardware, software, and
296 /// hybrid implementations are all valid.
297 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
299 // Set helper classes
300 void setHelperClassesMips16();
301 void setHelperClassesMipsSE();
303 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
306 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
307 const TargetFrameLowering *getFrameLowering() const override {
308 return FrameLowering.get();
310 const MipsRegisterInfo *getRegisterInfo() const override {
311 return &InstrInfo->getRegisterInfo();
313 const MipsTargetLowering *getTargetLowering() const override {
316 const InstrItineraryData *getInstrItineraryData() const override {
320 } // End llvm namespace