1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
15 #include "MCTargetDesc/MipsABIInfo.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "MipsSEISelDAGToDAG.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/BasicTTIImpl.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/TargetPassConfig.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Support/CodeGen.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
41 #define DEBUG_TYPE "mips"
43 extern "C" void LLVMInitializeMipsTarget() {
44 // Register the target.
45 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
46 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
47 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
48 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
51 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
52 const TargetOptions &Options,
55 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
57 // There are both little and big endian mips.
68 // Pointers are 32 bit on some ABIs.
72 // 8 and 16 bit integers only need to have natural alignment, but try to
73 // align them to 32 bits. 64 bit integers have natural alignment.
74 Ret += "-i8:8:32-i16:16:32-i64:64";
76 // 32 bit registers are always available and the stack is at least 64 bit
77 // aligned. On N64 64 bit registers are also available and the stack is
79 if (ABI.IsN64() || ABI.IsN32())
80 Ret += "-n32:64-S128";
87 static Reloc::Model getEffectiveRelocModel(bool JIT,
88 Optional<Reloc::Model> RM) {
89 if (!RM.hasValue() || JIT)
94 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
97 return CodeModel::Small;
100 // On function prologue, the stack is created by decrementing
101 // its pointer. Once decremented, all references are done with positive
102 // offset from the stack/frame pointer, using StackGrowsUp enables
103 // an easier handling.
104 // Using CodeModel::Large enables different CALL behavior.
105 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
106 StringRef CPU, StringRef FS,
107 const TargetOptions &Options,
108 Optional<Reloc::Model> RM,
109 Optional<CodeModel::Model> CM,
110 CodeGenOpt::Level OL, bool JIT,
112 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
113 CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
114 getEffectiveCodeModel(CM), OL),
115 isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
116 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
117 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this,
118 Options.StackAlignmentOverride),
119 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
120 isLittle, *this, Options.StackAlignmentOverride),
121 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
122 isLittle, *this, Options.StackAlignmentOverride) {
123 Subtarget = &DefaultSubtarget;
127 MipsTargetMachine::~MipsTargetMachine() = default;
129 void MipsebTargetMachine::anchor() {}
131 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
132 StringRef CPU, StringRef FS,
133 const TargetOptions &Options,
134 Optional<Reloc::Model> RM,
135 Optional<CodeModel::Model> CM,
136 CodeGenOpt::Level OL, bool JIT)
137 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
139 void MipselTargetMachine::anchor() {}
141 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
142 StringRef CPU, StringRef FS,
143 const TargetOptions &Options,
144 Optional<Reloc::Model> RM,
145 Optional<CodeModel::Model> CM,
146 CodeGenOpt::Level OL, bool JIT)
147 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
149 const MipsSubtarget *
150 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
151 Attribute CPUAttr = F.getFnAttribute("target-cpu");
152 Attribute FSAttr = F.getFnAttribute("target-features");
154 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
155 ? CPUAttr.getValueAsString().str()
157 std::string FS = !FSAttr.hasAttribute(Attribute::None)
158 ? FSAttr.getValueAsString().str()
161 !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
162 bool hasNoMips16Attr =
163 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
165 bool HasMicroMipsAttr =
166 !F.getFnAttribute("micromips").hasAttribute(Attribute::None);
167 bool HasNoMicroMipsAttr =
168 !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
170 // FIXME: This is related to the code below to reset the target options,
171 // we need to know whether or not the soft float flag is set on the
172 // function, so we can enable it as a subtarget feature.
174 F.hasFnAttribute("use-soft-float") &&
175 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
178 FS += FS.empty() ? "+mips16" : ",+mips16";
179 else if (hasNoMips16Attr)
180 FS += FS.empty() ? "-mips16" : ",-mips16";
181 if (HasMicroMipsAttr)
182 FS += FS.empty() ? "+micromips" : ",+micromips";
183 else if (HasNoMicroMipsAttr)
184 FS += FS.empty() ? "-micromips" : ",-micromips";
186 FS += FS.empty() ? "+soft-float" : ",+soft-float";
188 auto &I = SubtargetMap[CPU + FS];
190 // This needs to be done before we create a new subtarget since any
191 // creation will depend on the TM and the code generation flags on the
192 // function that reside in TargetOptions.
193 resetTargetOptions(F);
194 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this,
195 Options.StackAlignmentOverride);
200 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
201 DEBUG(dbgs() << "resetSubtarget\n");
203 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(MF->getFunction()));
204 MF->setSubtarget(Subtarget);
209 /// Mips Code Generator Pass Configuration Options.
210 class MipsPassConfig : public TargetPassConfig {
212 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
213 : TargetPassConfig(TM, PM) {
214 // The current implementation of long branch pass requires a scratch
215 // register ($at) to be available before branch instructions. Tail merging
216 // can break this requirement, so disable it when long branch pass is
218 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
221 MipsTargetMachine &getMipsTargetMachine() const {
222 return getTM<MipsTargetMachine>();
225 const MipsSubtarget &getMipsSubtarget() const {
226 return *getMipsTargetMachine().getSubtargetImpl();
229 void addIRPasses() override;
230 bool addInstSelector() override;
231 void addPreEmitPass() override;
232 void addPreRegAlloc() override;
235 } // end anonymous namespace
237 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
238 return new MipsPassConfig(*this, PM);
241 void MipsPassConfig::addIRPasses() {
242 TargetPassConfig::addIRPasses();
243 addPass(createAtomicExpandPass());
244 if (getMipsSubtarget().os16())
245 addPass(createMipsOs16Pass());
246 if (getMipsSubtarget().inMips16HardFloat())
247 addPass(createMips16HardFloatPass());
249 // Install an instruction selector pass using
250 // the ISelDag to gen Mips code.
251 bool MipsPassConfig::addInstSelector() {
252 addPass(createMipsModuleISelDagPass());
253 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
254 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
258 void MipsPassConfig::addPreRegAlloc() {
259 addPass(createMipsOptimizePICCallPass());
263 MipsTargetMachine::getTargetTransformInfo(const Function &F) {
264 if (Subtarget->allowMixed16_32()) {
265 DEBUG(errs() << "No Target Transform Info Pass Added\n");
266 // FIXME: This is no longer necessary as the TTI returned is per-function.
267 return TargetTransformInfo(F.getParent()->getDataLayout());
270 DEBUG(errs() << "Target Transform Info Pass Added\n");
271 return TargetTransformInfo(BasicTTIImpl(this, F));
274 // Implemented by targets that want to run passes immediately before
275 // machine code is emitted. return true if -print-machineinstrs should
276 // print out the code after the passes.
277 void MipsPassConfig::addPreEmitPass() {
278 addPass(createMicroMipsSizeReductionPass());
280 // The delay slot filler and the long branch passes can potientially create
281 // forbidden slot/ hazards for MIPSR6 which the hazard schedule pass will
282 // fix. Any new pass must come before the hazard schedule pass.
283 addPass(createMipsDelaySlotFillerPass());
284 addPass(createMipsLongBranchPass());
285 addPass(createMipsHazardSchedule());
286 addPass(createMipsConstantIslandPass());