1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelDAGToDAG.h"
15 #include "NVPTXUtilities.h"
16 #include "llvm/Analysis/ValueTracking.h"
17 #include "llvm/IR/GlobalValue.h"
18 #include "llvm/IR/Instructions.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetIntrinsicInfo.h"
27 #define DEBUG_TYPE "nvptx-isel"
29 static cl::opt<int> UsePrecDivF32(
30 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
31 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
32 " IEEE Compliant F32 div.rnd if available."),
36 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
37 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
41 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
42 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
46 /// createNVPTXISelDag - This pass converts a legalized DAG into a
47 /// NVPTX-specific DAG, ready for instruction scheduling.
48 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
49 llvm::CodeGenOpt::Level OptLevel) {
50 return new NVPTXDAGToDAGISel(TM, OptLevel);
53 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
54 CodeGenOpt::Level OptLevel)
55 : SelectionDAGISel(tm, OptLevel), TM(tm) {
56 doMulWide = (OptLevel > 0);
59 bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
60 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
61 return SelectionDAGISel::runOnMachineFunction(MF);
64 int NVPTXDAGToDAGISel::getDivF32Level() const {
65 if (UsePrecDivF32.getNumOccurrences() > 0) {
66 // If nvptx-prec-div32=N is used on the command-line, always honor it
69 // Otherwise, use div.approx if fast math is enabled
70 if (TM.Options.UnsafeFPMath)
77 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
78 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
79 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
80 return UsePrecSqrtF32;
82 // Otherwise, use sqrt.approx if fast math is enabled
83 return !TM.Options.UnsafeFPMath;
87 bool NVPTXDAGToDAGISel::useF32FTZ() const {
88 if (FtzEnabled.getNumOccurrences() > 0) {
89 // If nvptx-f32ftz is used on the command-line, always honor it
92 const Function *F = MF->getFunction();
93 // Otherwise, check for an nvptx-f32ftz attribute on the function
94 if (F->hasFnAttribute("nvptx-f32ftz"))
95 return F->getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
101 bool NVPTXDAGToDAGISel::allowFMA() const {
102 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
103 return TL->allowFMA(*MF, OptLevel);
106 /// Select - Select instructions not customized! Used for
107 /// expanded, promoted and normal instructions.
108 void NVPTXDAGToDAGISel::Select(SDNode *N) {
110 if (N->isMachineOpcode()) {
112 return; // Already selected.
115 switch (N->getOpcode()) {
124 case NVPTXISD::LoadV2:
125 case NVPTXISD::LoadV4:
126 if (tryLoadVector(N))
129 case NVPTXISD::LDGV2:
130 case NVPTXISD::LDGV4:
131 case NVPTXISD::LDUV2:
132 case NVPTXISD::LDUV4:
136 case NVPTXISD::StoreV2:
137 case NVPTXISD::StoreV4:
138 if (tryStoreVector(N))
141 case NVPTXISD::LoadParam:
142 case NVPTXISD::LoadParamV2:
143 case NVPTXISD::LoadParamV4:
147 case NVPTXISD::StoreRetval:
148 case NVPTXISD::StoreRetvalV2:
149 case NVPTXISD::StoreRetvalV4:
150 if (tryStoreRetval(N))
153 case NVPTXISD::StoreParam:
154 case NVPTXISD::StoreParamV2:
155 case NVPTXISD::StoreParamV4:
156 case NVPTXISD::StoreParamS32:
157 case NVPTXISD::StoreParamU32:
158 if (tryStoreParam(N))
161 case ISD::INTRINSIC_WO_CHAIN:
162 if (tryIntrinsicNoChain(N))
165 case ISD::INTRINSIC_W_CHAIN:
166 if (tryIntrinsicChain(N))
169 case NVPTXISD::Tex1DFloatS32:
170 case NVPTXISD::Tex1DFloatFloat:
171 case NVPTXISD::Tex1DFloatFloatLevel:
172 case NVPTXISD::Tex1DFloatFloatGrad:
173 case NVPTXISD::Tex1DS32S32:
174 case NVPTXISD::Tex1DS32Float:
175 case NVPTXISD::Tex1DS32FloatLevel:
176 case NVPTXISD::Tex1DS32FloatGrad:
177 case NVPTXISD::Tex1DU32S32:
178 case NVPTXISD::Tex1DU32Float:
179 case NVPTXISD::Tex1DU32FloatLevel:
180 case NVPTXISD::Tex1DU32FloatGrad:
181 case NVPTXISD::Tex1DArrayFloatS32:
182 case NVPTXISD::Tex1DArrayFloatFloat:
183 case NVPTXISD::Tex1DArrayFloatFloatLevel:
184 case NVPTXISD::Tex1DArrayFloatFloatGrad:
185 case NVPTXISD::Tex1DArrayS32S32:
186 case NVPTXISD::Tex1DArrayS32Float:
187 case NVPTXISD::Tex1DArrayS32FloatLevel:
188 case NVPTXISD::Tex1DArrayS32FloatGrad:
189 case NVPTXISD::Tex1DArrayU32S32:
190 case NVPTXISD::Tex1DArrayU32Float:
191 case NVPTXISD::Tex1DArrayU32FloatLevel:
192 case NVPTXISD::Tex1DArrayU32FloatGrad:
193 case NVPTXISD::Tex2DFloatS32:
194 case NVPTXISD::Tex2DFloatFloat:
195 case NVPTXISD::Tex2DFloatFloatLevel:
196 case NVPTXISD::Tex2DFloatFloatGrad:
197 case NVPTXISD::Tex2DS32S32:
198 case NVPTXISD::Tex2DS32Float:
199 case NVPTXISD::Tex2DS32FloatLevel:
200 case NVPTXISD::Tex2DS32FloatGrad:
201 case NVPTXISD::Tex2DU32S32:
202 case NVPTXISD::Tex2DU32Float:
203 case NVPTXISD::Tex2DU32FloatLevel:
204 case NVPTXISD::Tex2DU32FloatGrad:
205 case NVPTXISD::Tex2DArrayFloatS32:
206 case NVPTXISD::Tex2DArrayFloatFloat:
207 case NVPTXISD::Tex2DArrayFloatFloatLevel:
208 case NVPTXISD::Tex2DArrayFloatFloatGrad:
209 case NVPTXISD::Tex2DArrayS32S32:
210 case NVPTXISD::Tex2DArrayS32Float:
211 case NVPTXISD::Tex2DArrayS32FloatLevel:
212 case NVPTXISD::Tex2DArrayS32FloatGrad:
213 case NVPTXISD::Tex2DArrayU32S32:
214 case NVPTXISD::Tex2DArrayU32Float:
215 case NVPTXISD::Tex2DArrayU32FloatLevel:
216 case NVPTXISD::Tex2DArrayU32FloatGrad:
217 case NVPTXISD::Tex3DFloatS32:
218 case NVPTXISD::Tex3DFloatFloat:
219 case NVPTXISD::Tex3DFloatFloatLevel:
220 case NVPTXISD::Tex3DFloatFloatGrad:
221 case NVPTXISD::Tex3DS32S32:
222 case NVPTXISD::Tex3DS32Float:
223 case NVPTXISD::Tex3DS32FloatLevel:
224 case NVPTXISD::Tex3DS32FloatGrad:
225 case NVPTXISD::Tex3DU32S32:
226 case NVPTXISD::Tex3DU32Float:
227 case NVPTXISD::Tex3DU32FloatLevel:
228 case NVPTXISD::Tex3DU32FloatGrad:
229 case NVPTXISD::TexCubeFloatFloat:
230 case NVPTXISD::TexCubeFloatFloatLevel:
231 case NVPTXISD::TexCubeS32Float:
232 case NVPTXISD::TexCubeS32FloatLevel:
233 case NVPTXISD::TexCubeU32Float:
234 case NVPTXISD::TexCubeU32FloatLevel:
235 case NVPTXISD::TexCubeArrayFloatFloat:
236 case NVPTXISD::TexCubeArrayFloatFloatLevel:
237 case NVPTXISD::TexCubeArrayS32Float:
238 case NVPTXISD::TexCubeArrayS32FloatLevel:
239 case NVPTXISD::TexCubeArrayU32Float:
240 case NVPTXISD::TexCubeArrayU32FloatLevel:
241 case NVPTXISD::Tld4R2DFloatFloat:
242 case NVPTXISD::Tld4G2DFloatFloat:
243 case NVPTXISD::Tld4B2DFloatFloat:
244 case NVPTXISD::Tld4A2DFloatFloat:
245 case NVPTXISD::Tld4R2DS64Float:
246 case NVPTXISD::Tld4G2DS64Float:
247 case NVPTXISD::Tld4B2DS64Float:
248 case NVPTXISD::Tld4A2DS64Float:
249 case NVPTXISD::Tld4R2DU64Float:
250 case NVPTXISD::Tld4G2DU64Float:
251 case NVPTXISD::Tld4B2DU64Float:
252 case NVPTXISD::Tld4A2DU64Float:
253 case NVPTXISD::TexUnified1DFloatS32:
254 case NVPTXISD::TexUnified1DFloatFloat:
255 case NVPTXISD::TexUnified1DFloatFloatLevel:
256 case NVPTXISD::TexUnified1DFloatFloatGrad:
257 case NVPTXISD::TexUnified1DS32S32:
258 case NVPTXISD::TexUnified1DS32Float:
259 case NVPTXISD::TexUnified1DS32FloatLevel:
260 case NVPTXISD::TexUnified1DS32FloatGrad:
261 case NVPTXISD::TexUnified1DU32S32:
262 case NVPTXISD::TexUnified1DU32Float:
263 case NVPTXISD::TexUnified1DU32FloatLevel:
264 case NVPTXISD::TexUnified1DU32FloatGrad:
265 case NVPTXISD::TexUnified1DArrayFloatS32:
266 case NVPTXISD::TexUnified1DArrayFloatFloat:
267 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
268 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
269 case NVPTXISD::TexUnified1DArrayS32S32:
270 case NVPTXISD::TexUnified1DArrayS32Float:
271 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
272 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
273 case NVPTXISD::TexUnified1DArrayU32S32:
274 case NVPTXISD::TexUnified1DArrayU32Float:
275 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
276 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
277 case NVPTXISD::TexUnified2DFloatS32:
278 case NVPTXISD::TexUnified2DFloatFloat:
279 case NVPTXISD::TexUnified2DFloatFloatLevel:
280 case NVPTXISD::TexUnified2DFloatFloatGrad:
281 case NVPTXISD::TexUnified2DS32S32:
282 case NVPTXISD::TexUnified2DS32Float:
283 case NVPTXISD::TexUnified2DS32FloatLevel:
284 case NVPTXISD::TexUnified2DS32FloatGrad:
285 case NVPTXISD::TexUnified2DU32S32:
286 case NVPTXISD::TexUnified2DU32Float:
287 case NVPTXISD::TexUnified2DU32FloatLevel:
288 case NVPTXISD::TexUnified2DU32FloatGrad:
289 case NVPTXISD::TexUnified2DArrayFloatS32:
290 case NVPTXISD::TexUnified2DArrayFloatFloat:
291 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
292 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
293 case NVPTXISD::TexUnified2DArrayS32S32:
294 case NVPTXISD::TexUnified2DArrayS32Float:
295 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
296 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
297 case NVPTXISD::TexUnified2DArrayU32S32:
298 case NVPTXISD::TexUnified2DArrayU32Float:
299 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
300 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
301 case NVPTXISD::TexUnified3DFloatS32:
302 case NVPTXISD::TexUnified3DFloatFloat:
303 case NVPTXISD::TexUnified3DFloatFloatLevel:
304 case NVPTXISD::TexUnified3DFloatFloatGrad:
305 case NVPTXISD::TexUnified3DS32S32:
306 case NVPTXISD::TexUnified3DS32Float:
307 case NVPTXISD::TexUnified3DS32FloatLevel:
308 case NVPTXISD::TexUnified3DS32FloatGrad:
309 case NVPTXISD::TexUnified3DU32S32:
310 case NVPTXISD::TexUnified3DU32Float:
311 case NVPTXISD::TexUnified3DU32FloatLevel:
312 case NVPTXISD::TexUnified3DU32FloatGrad:
313 case NVPTXISD::TexUnifiedCubeFloatFloat:
314 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
315 case NVPTXISD::TexUnifiedCubeS32Float:
316 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
317 case NVPTXISD::TexUnifiedCubeU32Float:
318 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
319 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
320 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
321 case NVPTXISD::TexUnifiedCubeArrayS32Float:
322 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
323 case NVPTXISD::TexUnifiedCubeArrayU32Float:
324 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
325 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
326 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
327 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
328 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
329 case NVPTXISD::Tld4UnifiedR2DS64Float:
330 case NVPTXISD::Tld4UnifiedG2DS64Float:
331 case NVPTXISD::Tld4UnifiedB2DS64Float:
332 case NVPTXISD::Tld4UnifiedA2DS64Float:
333 case NVPTXISD::Tld4UnifiedR2DU64Float:
334 case NVPTXISD::Tld4UnifiedG2DU64Float:
335 case NVPTXISD::Tld4UnifiedB2DU64Float:
336 case NVPTXISD::Tld4UnifiedA2DU64Float:
337 if (tryTextureIntrinsic(N))
340 case NVPTXISD::Suld1DI8Clamp:
341 case NVPTXISD::Suld1DI16Clamp:
342 case NVPTXISD::Suld1DI32Clamp:
343 case NVPTXISD::Suld1DI64Clamp:
344 case NVPTXISD::Suld1DV2I8Clamp:
345 case NVPTXISD::Suld1DV2I16Clamp:
346 case NVPTXISD::Suld1DV2I32Clamp:
347 case NVPTXISD::Suld1DV2I64Clamp:
348 case NVPTXISD::Suld1DV4I8Clamp:
349 case NVPTXISD::Suld1DV4I16Clamp:
350 case NVPTXISD::Suld1DV4I32Clamp:
351 case NVPTXISD::Suld1DArrayI8Clamp:
352 case NVPTXISD::Suld1DArrayI16Clamp:
353 case NVPTXISD::Suld1DArrayI32Clamp:
354 case NVPTXISD::Suld1DArrayI64Clamp:
355 case NVPTXISD::Suld1DArrayV2I8Clamp:
356 case NVPTXISD::Suld1DArrayV2I16Clamp:
357 case NVPTXISD::Suld1DArrayV2I32Clamp:
358 case NVPTXISD::Suld1DArrayV2I64Clamp:
359 case NVPTXISD::Suld1DArrayV4I8Clamp:
360 case NVPTXISD::Suld1DArrayV4I16Clamp:
361 case NVPTXISD::Suld1DArrayV4I32Clamp:
362 case NVPTXISD::Suld2DI8Clamp:
363 case NVPTXISD::Suld2DI16Clamp:
364 case NVPTXISD::Suld2DI32Clamp:
365 case NVPTXISD::Suld2DI64Clamp:
366 case NVPTXISD::Suld2DV2I8Clamp:
367 case NVPTXISD::Suld2DV2I16Clamp:
368 case NVPTXISD::Suld2DV2I32Clamp:
369 case NVPTXISD::Suld2DV2I64Clamp:
370 case NVPTXISD::Suld2DV4I8Clamp:
371 case NVPTXISD::Suld2DV4I16Clamp:
372 case NVPTXISD::Suld2DV4I32Clamp:
373 case NVPTXISD::Suld2DArrayI8Clamp:
374 case NVPTXISD::Suld2DArrayI16Clamp:
375 case NVPTXISD::Suld2DArrayI32Clamp:
376 case NVPTXISD::Suld2DArrayI64Clamp:
377 case NVPTXISD::Suld2DArrayV2I8Clamp:
378 case NVPTXISD::Suld2DArrayV2I16Clamp:
379 case NVPTXISD::Suld2DArrayV2I32Clamp:
380 case NVPTXISD::Suld2DArrayV2I64Clamp:
381 case NVPTXISD::Suld2DArrayV4I8Clamp:
382 case NVPTXISD::Suld2DArrayV4I16Clamp:
383 case NVPTXISD::Suld2DArrayV4I32Clamp:
384 case NVPTXISD::Suld3DI8Clamp:
385 case NVPTXISD::Suld3DI16Clamp:
386 case NVPTXISD::Suld3DI32Clamp:
387 case NVPTXISD::Suld3DI64Clamp:
388 case NVPTXISD::Suld3DV2I8Clamp:
389 case NVPTXISD::Suld3DV2I16Clamp:
390 case NVPTXISD::Suld3DV2I32Clamp:
391 case NVPTXISD::Suld3DV2I64Clamp:
392 case NVPTXISD::Suld3DV4I8Clamp:
393 case NVPTXISD::Suld3DV4I16Clamp:
394 case NVPTXISD::Suld3DV4I32Clamp:
395 case NVPTXISD::Suld1DI8Trap:
396 case NVPTXISD::Suld1DI16Trap:
397 case NVPTXISD::Suld1DI32Trap:
398 case NVPTXISD::Suld1DI64Trap:
399 case NVPTXISD::Suld1DV2I8Trap:
400 case NVPTXISD::Suld1DV2I16Trap:
401 case NVPTXISD::Suld1DV2I32Trap:
402 case NVPTXISD::Suld1DV2I64Trap:
403 case NVPTXISD::Suld1DV4I8Trap:
404 case NVPTXISD::Suld1DV4I16Trap:
405 case NVPTXISD::Suld1DV4I32Trap:
406 case NVPTXISD::Suld1DArrayI8Trap:
407 case NVPTXISD::Suld1DArrayI16Trap:
408 case NVPTXISD::Suld1DArrayI32Trap:
409 case NVPTXISD::Suld1DArrayI64Trap:
410 case NVPTXISD::Suld1DArrayV2I8Trap:
411 case NVPTXISD::Suld1DArrayV2I16Trap:
412 case NVPTXISD::Suld1DArrayV2I32Trap:
413 case NVPTXISD::Suld1DArrayV2I64Trap:
414 case NVPTXISD::Suld1DArrayV4I8Trap:
415 case NVPTXISD::Suld1DArrayV4I16Trap:
416 case NVPTXISD::Suld1DArrayV4I32Trap:
417 case NVPTXISD::Suld2DI8Trap:
418 case NVPTXISD::Suld2DI16Trap:
419 case NVPTXISD::Suld2DI32Trap:
420 case NVPTXISD::Suld2DI64Trap:
421 case NVPTXISD::Suld2DV2I8Trap:
422 case NVPTXISD::Suld2DV2I16Trap:
423 case NVPTXISD::Suld2DV2I32Trap:
424 case NVPTXISD::Suld2DV2I64Trap:
425 case NVPTXISD::Suld2DV4I8Trap:
426 case NVPTXISD::Suld2DV4I16Trap:
427 case NVPTXISD::Suld2DV4I32Trap:
428 case NVPTXISD::Suld2DArrayI8Trap:
429 case NVPTXISD::Suld2DArrayI16Trap:
430 case NVPTXISD::Suld2DArrayI32Trap:
431 case NVPTXISD::Suld2DArrayI64Trap:
432 case NVPTXISD::Suld2DArrayV2I8Trap:
433 case NVPTXISD::Suld2DArrayV2I16Trap:
434 case NVPTXISD::Suld2DArrayV2I32Trap:
435 case NVPTXISD::Suld2DArrayV2I64Trap:
436 case NVPTXISD::Suld2DArrayV4I8Trap:
437 case NVPTXISD::Suld2DArrayV4I16Trap:
438 case NVPTXISD::Suld2DArrayV4I32Trap:
439 case NVPTXISD::Suld3DI8Trap:
440 case NVPTXISD::Suld3DI16Trap:
441 case NVPTXISD::Suld3DI32Trap:
442 case NVPTXISD::Suld3DI64Trap:
443 case NVPTXISD::Suld3DV2I8Trap:
444 case NVPTXISD::Suld3DV2I16Trap:
445 case NVPTXISD::Suld3DV2I32Trap:
446 case NVPTXISD::Suld3DV2I64Trap:
447 case NVPTXISD::Suld3DV4I8Trap:
448 case NVPTXISD::Suld3DV4I16Trap:
449 case NVPTXISD::Suld3DV4I32Trap:
450 case NVPTXISD::Suld1DI8Zero:
451 case NVPTXISD::Suld1DI16Zero:
452 case NVPTXISD::Suld1DI32Zero:
453 case NVPTXISD::Suld1DI64Zero:
454 case NVPTXISD::Suld1DV2I8Zero:
455 case NVPTXISD::Suld1DV2I16Zero:
456 case NVPTXISD::Suld1DV2I32Zero:
457 case NVPTXISD::Suld1DV2I64Zero:
458 case NVPTXISD::Suld1DV4I8Zero:
459 case NVPTXISD::Suld1DV4I16Zero:
460 case NVPTXISD::Suld1DV4I32Zero:
461 case NVPTXISD::Suld1DArrayI8Zero:
462 case NVPTXISD::Suld1DArrayI16Zero:
463 case NVPTXISD::Suld1DArrayI32Zero:
464 case NVPTXISD::Suld1DArrayI64Zero:
465 case NVPTXISD::Suld1DArrayV2I8Zero:
466 case NVPTXISD::Suld1DArrayV2I16Zero:
467 case NVPTXISD::Suld1DArrayV2I32Zero:
468 case NVPTXISD::Suld1DArrayV2I64Zero:
469 case NVPTXISD::Suld1DArrayV4I8Zero:
470 case NVPTXISD::Suld1DArrayV4I16Zero:
471 case NVPTXISD::Suld1DArrayV4I32Zero:
472 case NVPTXISD::Suld2DI8Zero:
473 case NVPTXISD::Suld2DI16Zero:
474 case NVPTXISD::Suld2DI32Zero:
475 case NVPTXISD::Suld2DI64Zero:
476 case NVPTXISD::Suld2DV2I8Zero:
477 case NVPTXISD::Suld2DV2I16Zero:
478 case NVPTXISD::Suld2DV2I32Zero:
479 case NVPTXISD::Suld2DV2I64Zero:
480 case NVPTXISD::Suld2DV4I8Zero:
481 case NVPTXISD::Suld2DV4I16Zero:
482 case NVPTXISD::Suld2DV4I32Zero:
483 case NVPTXISD::Suld2DArrayI8Zero:
484 case NVPTXISD::Suld2DArrayI16Zero:
485 case NVPTXISD::Suld2DArrayI32Zero:
486 case NVPTXISD::Suld2DArrayI64Zero:
487 case NVPTXISD::Suld2DArrayV2I8Zero:
488 case NVPTXISD::Suld2DArrayV2I16Zero:
489 case NVPTXISD::Suld2DArrayV2I32Zero:
490 case NVPTXISD::Suld2DArrayV2I64Zero:
491 case NVPTXISD::Suld2DArrayV4I8Zero:
492 case NVPTXISD::Suld2DArrayV4I16Zero:
493 case NVPTXISD::Suld2DArrayV4I32Zero:
494 case NVPTXISD::Suld3DI8Zero:
495 case NVPTXISD::Suld3DI16Zero:
496 case NVPTXISD::Suld3DI32Zero:
497 case NVPTXISD::Suld3DI64Zero:
498 case NVPTXISD::Suld3DV2I8Zero:
499 case NVPTXISD::Suld3DV2I16Zero:
500 case NVPTXISD::Suld3DV2I32Zero:
501 case NVPTXISD::Suld3DV2I64Zero:
502 case NVPTXISD::Suld3DV4I8Zero:
503 case NVPTXISD::Suld3DV4I16Zero:
504 case NVPTXISD::Suld3DV4I32Zero:
505 if (trySurfaceIntrinsic(N))
515 case ISD::ADDRSPACECAST:
516 SelectAddrSpaceCast(N);
524 bool NVPTXDAGToDAGISel::tryIntrinsicChain(SDNode *N) {
525 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
529 case Intrinsic::nvvm_ldg_global_f:
530 case Intrinsic::nvvm_ldg_global_i:
531 case Intrinsic::nvvm_ldg_global_p:
532 case Intrinsic::nvvm_ldu_global_f:
533 case Intrinsic::nvvm_ldu_global_i:
534 case Intrinsic::nvvm_ldu_global_p:
539 static unsigned int getCodeAddrSpace(MemSDNode *N) {
540 const Value *Src = N->getMemOperand()->getValue();
543 return NVPTX::PTXLdStInstCode::GENERIC;
545 if (auto *PT = dyn_cast<PointerType>(Src->getType())) {
546 switch (PT->getAddressSpace()) {
547 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
548 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
549 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
550 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
551 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
552 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
556 return NVPTX::PTXLdStInstCode::GENERIC;
559 static bool canLowerToLDG(MemSDNode *N, const NVPTXSubtarget &Subtarget,
560 unsigned CodeAddrSpace, MachineFunction *F) {
561 // To use non-coherent caching, the load has to be from global
562 // memory and we have to prove that the memory area is not written
563 // to anywhere for the duration of the kernel call, not even after
566 // To ensure that there are no writes to the memory, we require the
567 // underlying pointer to be a noalias (__restrict) kernel parameter
568 // that is never used for a write. We can only do this for kernel
569 // functions since from within a device function, we cannot know if
570 // there were or will be writes to the memory from the caller - or we
571 // could, but then we would have to do inter-procedural analysis.
572 if (!Subtarget.hasLDG() || CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL ||
573 !isKernelFunction(*F->getFunction())) {
577 // We use GetUnderlyingObjects() here instead of
578 // GetUnderlyingObject() mainly because the former looks through phi
579 // nodes while the latter does not. We need to look through phi
580 // nodes to handle pointer induction variables.
581 SmallVector<Value *, 8> Objs;
582 GetUnderlyingObjects(const_cast<Value *>(N->getMemOperand()->getValue()),
583 Objs, F->getDataLayout());
584 for (Value *Obj : Objs) {
585 auto *A = dyn_cast<const Argument>(Obj);
586 if (!A || !A->onlyReadsMemory() || !A->hasNoAliasAttr()) return false;
592 bool NVPTXDAGToDAGISel::tryIntrinsicNoChain(SDNode *N) {
593 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
597 case Intrinsic::nvvm_texsurf_handle_internal:
598 SelectTexSurfHandle(N);
603 void NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
604 // Op 0 is the intrinsic ID
605 SDValue Wrapper = N->getOperand(1);
606 SDValue GlobalVal = Wrapper.getOperand(0);
607 ReplaceNode(N, CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N),
608 MVT::i64, GlobalVal));
611 void NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
612 SDValue Src = N->getOperand(0);
613 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
614 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
615 unsigned DstAddrSpace = CastN->getDestAddressSpace();
617 assert(SrcAddrSpace != DstAddrSpace &&
618 "addrspacecast must be between different address spaces");
620 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
621 // Specific to generic
623 switch (SrcAddrSpace) {
624 default: report_fatal_error("Bad address space in addrspacecast");
625 case ADDRESS_SPACE_GLOBAL:
626 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
628 case ADDRESS_SPACE_SHARED:
629 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
631 case ADDRESS_SPACE_CONST:
632 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
634 case ADDRESS_SPACE_LOCAL:
635 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
638 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0),
642 // Generic to specific
643 if (SrcAddrSpace != 0)
644 report_fatal_error("Cannot cast between two non-generic address spaces");
646 switch (DstAddrSpace) {
647 default: report_fatal_error("Bad address space in addrspacecast");
648 case ADDRESS_SPACE_GLOBAL:
649 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
650 : NVPTX::cvta_to_global_yes;
652 case ADDRESS_SPACE_SHARED:
653 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
654 : NVPTX::cvta_to_shared_yes;
656 case ADDRESS_SPACE_CONST:
658 TM.is64Bit() ? NVPTX::cvta_to_const_yes_64 : NVPTX::cvta_to_const_yes;
660 case ADDRESS_SPACE_LOCAL:
662 TM.is64Bit() ? NVPTX::cvta_to_local_yes_64 : NVPTX::cvta_to_local_yes;
664 case ADDRESS_SPACE_PARAM:
665 Opc = TM.is64Bit() ? NVPTX::nvvm_ptr_gen_to_param_64
666 : NVPTX::nvvm_ptr_gen_to_param;
669 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0),
675 bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
677 LoadSDNode *LD = cast<LoadSDNode>(N);
678 EVT LoadedVT = LD->getMemoryVT();
679 SDNode *NVPTXLD = nullptr;
681 // do not support pre/post inc/dec
685 if (!LoadedVT.isSimple())
688 // Address Space Setting
689 unsigned int codeAddrSpace = getCodeAddrSpace(LD);
691 if (canLowerToLDG(LD, *Subtarget, codeAddrSpace, MF)) {
696 // - .volatile is only availalble for .global and .shared
697 bool isVolatile = LD->isVolatile();
698 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
699 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
700 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
704 MVT SimpleVT = LoadedVT.getSimpleVT();
705 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
706 if (SimpleVT.isVector()) {
707 unsigned num = SimpleVT.getVectorNumElements();
709 vecType = NVPTX::PTXLdStInstCode::V2;
711 vecType = NVPTX::PTXLdStInstCode::V4;
716 // Type Setting: fromType + fromTypeWidth
718 // Sign : ISD::SEXTLOAD
719 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
721 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
722 MVT ScalarVT = SimpleVT.getScalarType();
723 // Read at least 8 bits (predicates are stored as 8-bit values)
724 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
725 unsigned int fromType;
726 if ((LD->getExtensionType() == ISD::SEXTLOAD))
727 fromType = NVPTX::PTXLdStInstCode::Signed;
728 else if (ScalarVT.isFloatingPoint())
729 fromType = NVPTX::PTXLdStInstCode::Float;
731 fromType = NVPTX::PTXLdStInstCode::Unsigned;
733 // Create the machine instruction DAG
734 SDValue Chain = N->getOperand(0);
735 SDValue N1 = N->getOperand(1);
737 SDValue Offset, Base;
739 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
741 if (SelectDirectAddr(N1, Addr)) {
744 Opcode = NVPTX::LD_i8_avar;
747 Opcode = NVPTX::LD_i16_avar;
750 Opcode = NVPTX::LD_i32_avar;
753 Opcode = NVPTX::LD_i64_avar;
756 Opcode = NVPTX::LD_f32_avar;
759 Opcode = NVPTX::LD_f64_avar;
764 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
765 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
766 getI32Imm(fromTypeWidth, dl), Addr, Chain };
767 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
768 } else if (TM.is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
769 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
772 Opcode = NVPTX::LD_i8_asi;
775 Opcode = NVPTX::LD_i16_asi;
778 Opcode = NVPTX::LD_i32_asi;
781 Opcode = NVPTX::LD_i64_asi;
784 Opcode = NVPTX::LD_f32_asi;
787 Opcode = NVPTX::LD_f64_asi;
792 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
793 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
794 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
795 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
796 } else if (TM.is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
797 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
801 Opcode = NVPTX::LD_i8_ari_64;
804 Opcode = NVPTX::LD_i16_ari_64;
807 Opcode = NVPTX::LD_i32_ari_64;
810 Opcode = NVPTX::LD_i64_ari_64;
813 Opcode = NVPTX::LD_f32_ari_64;
816 Opcode = NVPTX::LD_f64_ari_64;
824 Opcode = NVPTX::LD_i8_ari;
827 Opcode = NVPTX::LD_i16_ari;
830 Opcode = NVPTX::LD_i32_ari;
833 Opcode = NVPTX::LD_i64_ari;
836 Opcode = NVPTX::LD_f32_ari;
839 Opcode = NVPTX::LD_f64_ari;
845 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
846 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
847 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
848 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
853 Opcode = NVPTX::LD_i8_areg_64;
856 Opcode = NVPTX::LD_i16_areg_64;
859 Opcode = NVPTX::LD_i32_areg_64;
862 Opcode = NVPTX::LD_i64_areg_64;
865 Opcode = NVPTX::LD_f32_areg_64;
868 Opcode = NVPTX::LD_f64_areg_64;
876 Opcode = NVPTX::LD_i8_areg;
879 Opcode = NVPTX::LD_i16_areg;
882 Opcode = NVPTX::LD_i32_areg;
885 Opcode = NVPTX::LD_i64_areg;
888 Opcode = NVPTX::LD_f32_areg;
891 Opcode = NVPTX::LD_f64_areg;
897 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
898 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
899 getI32Imm(fromTypeWidth, dl), N1, Chain };
900 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
906 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
907 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
908 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
910 ReplaceNode(N, NVPTXLD);
914 bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
916 SDValue Chain = N->getOperand(0);
917 SDValue Op1 = N->getOperand(1);
918 SDValue Addr, Offset, Base;
922 MemSDNode *MemSD = cast<MemSDNode>(N);
923 EVT LoadedVT = MemSD->getMemoryVT();
925 if (!LoadedVT.isSimple())
928 // Address Space Setting
929 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD);
931 if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpace, MF)) {
936 // - .volatile is only availalble for .global and .shared
937 bool IsVolatile = MemSD->isVolatile();
938 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
939 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
940 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
944 MVT SimpleVT = LoadedVT.getSimpleVT();
946 // Type Setting: fromType + fromTypeWidth
948 // Sign : ISD::SEXTLOAD
949 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
951 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
952 MVT ScalarVT = SimpleVT.getScalarType();
953 // Read at least 8 bits (predicates are stored as 8-bit values)
954 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
955 unsigned int FromType;
956 // The last operand holds the original LoadSDNode::getExtensionType() value
957 unsigned ExtensionType = cast<ConstantSDNode>(
958 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
959 if (ExtensionType == ISD::SEXTLOAD)
960 FromType = NVPTX::PTXLdStInstCode::Signed;
961 else if (ScalarVT.isFloatingPoint())
962 FromType = NVPTX::PTXLdStInstCode::Float;
964 FromType = NVPTX::PTXLdStInstCode::Unsigned;
968 switch (N->getOpcode()) {
969 case NVPTXISD::LoadV2:
970 VecType = NVPTX::PTXLdStInstCode::V2;
972 case NVPTXISD::LoadV4:
973 VecType = NVPTX::PTXLdStInstCode::V4;
979 EVT EltVT = N->getValueType(0);
981 if (SelectDirectAddr(Op1, Addr)) {
982 switch (N->getOpcode()) {
985 case NVPTXISD::LoadV2:
986 switch (EltVT.getSimpleVT().SimpleTy) {
990 Opcode = NVPTX::LDV_i8_v2_avar;
993 Opcode = NVPTX::LDV_i16_v2_avar;
996 Opcode = NVPTX::LDV_i32_v2_avar;
999 Opcode = NVPTX::LDV_i64_v2_avar;
1002 Opcode = NVPTX::LDV_f32_v2_avar;
1005 Opcode = NVPTX::LDV_f64_v2_avar;
1009 case NVPTXISD::LoadV4:
1010 switch (EltVT.getSimpleVT().SimpleTy) {
1014 Opcode = NVPTX::LDV_i8_v4_avar;
1017 Opcode = NVPTX::LDV_i16_v4_avar;
1020 Opcode = NVPTX::LDV_i32_v4_avar;
1023 Opcode = NVPTX::LDV_f32_v4_avar;
1029 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1030 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1031 getI32Imm(FromTypeWidth, DL), Addr, Chain };
1032 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1033 } else if (TM.is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
1034 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
1035 switch (N->getOpcode()) {
1038 case NVPTXISD::LoadV2:
1039 switch (EltVT.getSimpleVT().SimpleTy) {
1043 Opcode = NVPTX::LDV_i8_v2_asi;
1046 Opcode = NVPTX::LDV_i16_v2_asi;
1049 Opcode = NVPTX::LDV_i32_v2_asi;
1052 Opcode = NVPTX::LDV_i64_v2_asi;
1055 Opcode = NVPTX::LDV_f32_v2_asi;
1058 Opcode = NVPTX::LDV_f64_v2_asi;
1062 case NVPTXISD::LoadV4:
1063 switch (EltVT.getSimpleVT().SimpleTy) {
1067 Opcode = NVPTX::LDV_i8_v4_asi;
1070 Opcode = NVPTX::LDV_i16_v4_asi;
1073 Opcode = NVPTX::LDV_i32_v4_asi;
1076 Opcode = NVPTX::LDV_f32_v4_asi;
1082 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1083 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1084 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1085 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1086 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1087 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1089 switch (N->getOpcode()) {
1092 case NVPTXISD::LoadV2:
1093 switch (EltVT.getSimpleVT().SimpleTy) {
1097 Opcode = NVPTX::LDV_i8_v2_ari_64;
1100 Opcode = NVPTX::LDV_i16_v2_ari_64;
1103 Opcode = NVPTX::LDV_i32_v2_ari_64;
1106 Opcode = NVPTX::LDV_i64_v2_ari_64;
1109 Opcode = NVPTX::LDV_f32_v2_ari_64;
1112 Opcode = NVPTX::LDV_f64_v2_ari_64;
1116 case NVPTXISD::LoadV4:
1117 switch (EltVT.getSimpleVT().SimpleTy) {
1121 Opcode = NVPTX::LDV_i8_v4_ari_64;
1124 Opcode = NVPTX::LDV_i16_v4_ari_64;
1127 Opcode = NVPTX::LDV_i32_v4_ari_64;
1130 Opcode = NVPTX::LDV_f32_v4_ari_64;
1136 switch (N->getOpcode()) {
1139 case NVPTXISD::LoadV2:
1140 switch (EltVT.getSimpleVT().SimpleTy) {
1144 Opcode = NVPTX::LDV_i8_v2_ari;
1147 Opcode = NVPTX::LDV_i16_v2_ari;
1150 Opcode = NVPTX::LDV_i32_v2_ari;
1153 Opcode = NVPTX::LDV_i64_v2_ari;
1156 Opcode = NVPTX::LDV_f32_v2_ari;
1159 Opcode = NVPTX::LDV_f64_v2_ari;
1163 case NVPTXISD::LoadV4:
1164 switch (EltVT.getSimpleVT().SimpleTy) {
1168 Opcode = NVPTX::LDV_i8_v4_ari;
1171 Opcode = NVPTX::LDV_i16_v4_ari;
1174 Opcode = NVPTX::LDV_i32_v4_ari;
1177 Opcode = NVPTX::LDV_f32_v4_ari;
1184 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1185 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1186 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1188 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1191 switch (N->getOpcode()) {
1194 case NVPTXISD::LoadV2:
1195 switch (EltVT.getSimpleVT().SimpleTy) {
1199 Opcode = NVPTX::LDV_i8_v2_areg_64;
1202 Opcode = NVPTX::LDV_i16_v2_areg_64;
1205 Opcode = NVPTX::LDV_i32_v2_areg_64;
1208 Opcode = NVPTX::LDV_i64_v2_areg_64;
1211 Opcode = NVPTX::LDV_f32_v2_areg_64;
1214 Opcode = NVPTX::LDV_f64_v2_areg_64;
1218 case NVPTXISD::LoadV4:
1219 switch (EltVT.getSimpleVT().SimpleTy) {
1223 Opcode = NVPTX::LDV_i8_v4_areg_64;
1226 Opcode = NVPTX::LDV_i16_v4_areg_64;
1229 Opcode = NVPTX::LDV_i32_v4_areg_64;
1232 Opcode = NVPTX::LDV_f32_v4_areg_64;
1238 switch (N->getOpcode()) {
1241 case NVPTXISD::LoadV2:
1242 switch (EltVT.getSimpleVT().SimpleTy) {
1246 Opcode = NVPTX::LDV_i8_v2_areg;
1249 Opcode = NVPTX::LDV_i16_v2_areg;
1252 Opcode = NVPTX::LDV_i32_v2_areg;
1255 Opcode = NVPTX::LDV_i64_v2_areg;
1258 Opcode = NVPTX::LDV_f32_v2_areg;
1261 Opcode = NVPTX::LDV_f64_v2_areg;
1265 case NVPTXISD::LoadV4:
1266 switch (EltVT.getSimpleVT().SimpleTy) {
1270 Opcode = NVPTX::LDV_i8_v4_areg;
1273 Opcode = NVPTX::LDV_i16_v4_areg;
1276 Opcode = NVPTX::LDV_i32_v4_areg;
1279 Opcode = NVPTX::LDV_f32_v4_areg;
1286 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1287 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1288 getI32Imm(FromTypeWidth, DL), Op1, Chain };
1289 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1292 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1293 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1294 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1300 bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
1302 SDValue Chain = N->getOperand(0);
1307 // If this is an LDG intrinsic, the address is the third operand. If its an
1308 // LDG/LDU SD node (from custom vector handling), then its the second operand
1309 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1310 Op1 = N->getOperand(2);
1311 Mem = cast<MemIntrinsicSDNode>(N);
1312 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1316 case Intrinsic::nvvm_ldg_global_f:
1317 case Intrinsic::nvvm_ldg_global_i:
1318 case Intrinsic::nvvm_ldg_global_p:
1321 case Intrinsic::nvvm_ldu_global_f:
1322 case Intrinsic::nvvm_ldu_global_i:
1323 case Intrinsic::nvvm_ldu_global_p:
1328 Op1 = N->getOperand(1);
1329 Mem = cast<MemSDNode>(N);
1335 SDValue Base, Offset, Addr;
1337 EVT EltVT = Mem->getMemoryVT();
1338 unsigned NumElts = 1;
1339 if (EltVT.isVector()) {
1340 NumElts = EltVT.getVectorNumElements();
1341 EltVT = EltVT.getVectorElementType();
1344 // Build the "promoted" result VTList for the load. If we are really loading
1345 // i8s, then the return type will be promoted to i16 since we do not expose
1346 // 8-bit registers in NVPTX.
1347 EVT NodeVT = (EltVT == MVT::i8) ? MVT::i16 : EltVT;
1348 SmallVector<EVT, 5> InstVTs;
1349 for (unsigned i = 0; i != NumElts; ++i) {
1350 InstVTs.push_back(NodeVT);
1352 InstVTs.push_back(MVT::Other);
1353 SDVTList InstVTList = CurDAG->getVTList(InstVTs);
1355 if (SelectDirectAddr(Op1, Addr)) {
1356 switch (N->getOpcode()) {
1359 case ISD::INTRINSIC_W_CHAIN:
1361 switch (EltVT.getSimpleVT().SimpleTy) {
1365 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1368 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1371 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1374 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1377 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1380 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1384 switch (EltVT.getSimpleVT().SimpleTy) {
1388 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1391 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1394 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1397 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1400 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1403 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1408 case NVPTXISD::LDGV2:
1409 switch (EltVT.getSimpleVT().SimpleTy) {
1413 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1416 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1419 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1422 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1425 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1428 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1432 case NVPTXISD::LDUV2:
1433 switch (EltVT.getSimpleVT().SimpleTy) {
1437 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1440 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1443 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1446 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1449 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1452 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1456 case NVPTXISD::LDGV4:
1457 switch (EltVT.getSimpleVT().SimpleTy) {
1461 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1464 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1467 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1470 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1474 case NVPTXISD::LDUV4:
1475 switch (EltVT.getSimpleVT().SimpleTy) {
1479 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1482 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1485 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1488 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1494 SDValue Ops[] = { Addr, Chain };
1495 LD = CurDAG->getMachineNode(Opcode, DL, InstVTList, Ops);
1496 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1497 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1499 switch (N->getOpcode()) {
1503 case ISD::INTRINSIC_W_CHAIN:
1505 switch (EltVT.getSimpleVT().SimpleTy) {
1509 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1512 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1515 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1518 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1521 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1524 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1528 switch (EltVT.getSimpleVT().SimpleTy) {
1532 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1535 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1538 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1541 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1544 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1547 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1552 case NVPTXISD::LoadV2:
1553 case NVPTXISD::LDGV2:
1554 switch (EltVT.getSimpleVT().SimpleTy) {
1558 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1561 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1564 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1567 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1570 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1573 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1577 case NVPTXISD::LDUV2:
1578 switch (EltVT.getSimpleVT().SimpleTy) {
1582 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1585 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1588 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1591 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1594 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1597 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1601 case NVPTXISD::LoadV4:
1602 case NVPTXISD::LDGV4:
1603 switch (EltVT.getSimpleVT().SimpleTy) {
1607 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1610 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1613 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1616 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1620 case NVPTXISD::LDUV4:
1621 switch (EltVT.getSimpleVT().SimpleTy) {
1625 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1628 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1631 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1634 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1640 switch (N->getOpcode()) {
1644 case ISD::INTRINSIC_W_CHAIN:
1646 switch (EltVT.getSimpleVT().SimpleTy) {
1650 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1653 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1656 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1659 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1662 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1665 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1669 switch (EltVT.getSimpleVT().SimpleTy) {
1673 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1676 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1679 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1682 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1685 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1688 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1693 case NVPTXISD::LoadV2:
1694 case NVPTXISD::LDGV2:
1695 switch (EltVT.getSimpleVT().SimpleTy) {
1699 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1702 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1705 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1708 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1711 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1714 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1718 case NVPTXISD::LDUV2:
1719 switch (EltVT.getSimpleVT().SimpleTy) {
1723 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1726 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1729 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1732 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1735 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1738 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1742 case NVPTXISD::LoadV4:
1743 case NVPTXISD::LDGV4:
1744 switch (EltVT.getSimpleVT().SimpleTy) {
1748 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1751 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1754 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1757 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1761 case NVPTXISD::LDUV4:
1762 switch (EltVT.getSimpleVT().SimpleTy) {
1766 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1769 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1772 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1775 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1782 SDValue Ops[] = { Base, Offset, Chain };
1784 LD = CurDAG->getMachineNode(Opcode, DL, InstVTList, Ops);
1787 switch (N->getOpcode()) {
1791 case ISD::INTRINSIC_W_CHAIN:
1793 switch (EltVT.getSimpleVT().SimpleTy) {
1797 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1800 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1803 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1806 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1809 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1812 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1816 switch (EltVT.getSimpleVT().SimpleTy) {
1820 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1823 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1826 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1829 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1832 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1835 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1840 case NVPTXISD::LoadV2:
1841 case NVPTXISD::LDGV2:
1842 switch (EltVT.getSimpleVT().SimpleTy) {
1846 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1849 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1852 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1855 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1858 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1861 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1865 case NVPTXISD::LDUV2:
1866 switch (EltVT.getSimpleVT().SimpleTy) {
1870 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1873 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1876 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1879 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1882 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1885 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1889 case NVPTXISD::LoadV4:
1890 case NVPTXISD::LDGV4:
1891 switch (EltVT.getSimpleVT().SimpleTy) {
1895 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1898 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1901 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1904 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1908 case NVPTXISD::LDUV4:
1909 switch (EltVT.getSimpleVT().SimpleTy) {
1913 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1916 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1919 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1922 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1928 switch (N->getOpcode()) {
1932 case ISD::INTRINSIC_W_CHAIN:
1934 switch (EltVT.getSimpleVT().SimpleTy) {
1938 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1941 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1944 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1947 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1950 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1953 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1957 switch (EltVT.getSimpleVT().SimpleTy) {
1961 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1964 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1967 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1970 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1973 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1976 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1981 case NVPTXISD::LoadV2:
1982 case NVPTXISD::LDGV2:
1983 switch (EltVT.getSimpleVT().SimpleTy) {
1987 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1990 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1993 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1996 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1999 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
2002 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
2006 case NVPTXISD::LDUV2:
2007 switch (EltVT.getSimpleVT().SimpleTy) {
2011 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
2014 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
2017 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
2020 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
2023 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
2026 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
2030 case NVPTXISD::LoadV4:
2031 case NVPTXISD::LDGV4:
2032 switch (EltVT.getSimpleVT().SimpleTy) {
2036 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
2039 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
2042 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
2045 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
2049 case NVPTXISD::LDUV4:
2050 switch (EltVT.getSimpleVT().SimpleTy) {
2054 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
2057 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
2060 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
2063 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
2070 SDValue Ops[] = { Op1, Chain };
2071 LD = CurDAG->getMachineNode(Opcode, DL, InstVTList, Ops);
2074 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2075 MemRefs0[0] = Mem->getMemOperand();
2076 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
2078 // For automatic generation of LDG (through SelectLoad[Vector], not the
2079 // intrinsics), we may have an extending load like:
2081 // i32,ch = load<LD1[%data1(addrspace=1)], zext from i8> t0, t7, undef:i64
2083 // In this case, the matching logic above will select a load for the original
2084 // memory type (in this case, i8) and our types will not match (the node needs
2085 // to return an i32 in this case). Our LDG/LDU nodes do not support the
2086 // concept of sign-/zero-extension, so emulate it here by adding an explicit
2087 // CVT instruction. Ptxas should clean up any redundancies here.
2089 EVT OrigType = N->getValueType(0);
2090 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(N);
2092 if (OrigType != EltVT && LdNode) {
2093 // We have an extending-load. The instruction we selected operates on the
2094 // smaller type, but the SDNode we are replacing has the larger type. We
2095 // need to emit a CVT to make the types match.
2096 bool IsSigned = LdNode->getExtensionType() == ISD::SEXTLOAD;
2097 unsigned CvtOpc = GetConvertOpcode(OrigType.getSimpleVT(),
2098 EltVT.getSimpleVT(), IsSigned);
2100 // For each output value, apply the manual sign/zero-extension and make sure
2101 // all users of the load go through that CVT.
2102 for (unsigned i = 0; i != NumElts; ++i) {
2104 SDValue OrigVal(N, i);
2107 CurDAG->getMachineNode(CvtOpc, DL, OrigType, Res,
2108 CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2110 ReplaceUses(OrigVal, SDValue(CvtNode, 0));
2118 bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
2120 StoreSDNode *ST = cast<StoreSDNode>(N);
2121 EVT StoreVT = ST->getMemoryVT();
2122 SDNode *NVPTXST = nullptr;
2124 // do not support pre/post inc/dec
2125 if (ST->isIndexed())
2128 if (!StoreVT.isSimple())
2131 // Address Space Setting
2132 unsigned int codeAddrSpace = getCodeAddrSpace(ST);
2135 // - .volatile is only availalble for .global and .shared
2136 bool isVolatile = ST->isVolatile();
2137 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2138 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2139 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2143 MVT SimpleVT = StoreVT.getSimpleVT();
2144 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
2145 if (SimpleVT.isVector()) {
2146 unsigned num = SimpleVT.getVectorNumElements();
2148 vecType = NVPTX::PTXLdStInstCode::V2;
2150 vecType = NVPTX::PTXLdStInstCode::V4;
2155 // Type Setting: toType + toTypeWidth
2156 // - for integer type, always use 'u'
2158 MVT ScalarVT = SimpleVT.getScalarType();
2159 unsigned toTypeWidth = ScalarVT.getSizeInBits();
2160 unsigned int toType;
2161 if (ScalarVT.isFloatingPoint())
2162 toType = NVPTX::PTXLdStInstCode::Float;
2164 toType = NVPTX::PTXLdStInstCode::Unsigned;
2166 // Create the machine instruction DAG
2167 SDValue Chain = N->getOperand(0);
2168 SDValue N1 = N->getOperand(1);
2169 SDValue N2 = N->getOperand(2);
2171 SDValue Offset, Base;
2173 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
2175 if (SelectDirectAddr(N2, Addr)) {
2178 Opcode = NVPTX::ST_i8_avar;
2181 Opcode = NVPTX::ST_i16_avar;
2184 Opcode = NVPTX::ST_i32_avar;
2187 Opcode = NVPTX::ST_i64_avar;
2190 Opcode = NVPTX::ST_f32_avar;
2193 Opcode = NVPTX::ST_f64_avar;
2198 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2199 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2200 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Addr,
2202 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2203 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2204 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2207 Opcode = NVPTX::ST_i8_asi;
2210 Opcode = NVPTX::ST_i16_asi;
2213 Opcode = NVPTX::ST_i32_asi;
2216 Opcode = NVPTX::ST_i64_asi;
2219 Opcode = NVPTX::ST_f32_asi;
2222 Opcode = NVPTX::ST_f64_asi;
2227 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2228 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2229 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2231 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2232 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2233 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2237 Opcode = NVPTX::ST_i8_ari_64;
2240 Opcode = NVPTX::ST_i16_ari_64;
2243 Opcode = NVPTX::ST_i32_ari_64;
2246 Opcode = NVPTX::ST_i64_ari_64;
2249 Opcode = NVPTX::ST_f32_ari_64;
2252 Opcode = NVPTX::ST_f64_ari_64;
2260 Opcode = NVPTX::ST_i8_ari;
2263 Opcode = NVPTX::ST_i16_ari;
2266 Opcode = NVPTX::ST_i32_ari;
2269 Opcode = NVPTX::ST_i64_ari;
2272 Opcode = NVPTX::ST_f32_ari;
2275 Opcode = NVPTX::ST_f64_ari;
2281 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2282 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2283 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2285 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2290 Opcode = NVPTX::ST_i8_areg_64;
2293 Opcode = NVPTX::ST_i16_areg_64;
2296 Opcode = NVPTX::ST_i32_areg_64;
2299 Opcode = NVPTX::ST_i64_areg_64;
2302 Opcode = NVPTX::ST_f32_areg_64;
2305 Opcode = NVPTX::ST_f64_areg_64;
2313 Opcode = NVPTX::ST_i8_areg;
2316 Opcode = NVPTX::ST_i16_areg;
2319 Opcode = NVPTX::ST_i32_areg;
2322 Opcode = NVPTX::ST_i64_areg;
2325 Opcode = NVPTX::ST_f32_areg;
2328 Opcode = NVPTX::ST_f64_areg;
2334 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2335 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2336 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), N2,
2338 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2344 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2345 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2346 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2347 ReplaceNode(N, NVPTXST);
2351 bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
2352 SDValue Chain = N->getOperand(0);
2353 SDValue Op1 = N->getOperand(1);
2354 SDValue Addr, Offset, Base;
2358 EVT EltVT = Op1.getValueType();
2359 MemSDNode *MemSD = cast<MemSDNode>(N);
2360 EVT StoreVT = MemSD->getMemoryVT();
2362 // Address Space Setting
2363 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD);
2365 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
2366 report_fatal_error("Cannot store to pointer that points to constant "
2371 // - .volatile is only availalble for .global and .shared
2372 bool IsVolatile = MemSD->isVolatile();
2373 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2374 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2375 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2378 // Type Setting: toType + toTypeWidth
2379 // - for integer type, always use 'u'
2380 assert(StoreVT.isSimple() && "Store value is not simple");
2381 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
2382 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
2384 if (ScalarVT.isFloatingPoint())
2385 ToType = NVPTX::PTXLdStInstCode::Float;
2387 ToType = NVPTX::PTXLdStInstCode::Unsigned;
2389 SmallVector<SDValue, 12> StOps;
2393 switch (N->getOpcode()) {
2394 case NVPTXISD::StoreV2:
2395 VecType = NVPTX::PTXLdStInstCode::V2;
2396 StOps.push_back(N->getOperand(1));
2397 StOps.push_back(N->getOperand(2));
2398 N2 = N->getOperand(3);
2400 case NVPTXISD::StoreV4:
2401 VecType = NVPTX::PTXLdStInstCode::V4;
2402 StOps.push_back(N->getOperand(1));
2403 StOps.push_back(N->getOperand(2));
2404 StOps.push_back(N->getOperand(3));
2405 StOps.push_back(N->getOperand(4));
2406 N2 = N->getOperand(5);
2412 StOps.push_back(getI32Imm(IsVolatile, DL));
2413 StOps.push_back(getI32Imm(CodeAddrSpace, DL));
2414 StOps.push_back(getI32Imm(VecType, DL));
2415 StOps.push_back(getI32Imm(ToType, DL));
2416 StOps.push_back(getI32Imm(ToTypeWidth, DL));
2418 if (SelectDirectAddr(N2, Addr)) {
2419 switch (N->getOpcode()) {
2422 case NVPTXISD::StoreV2:
2423 switch (EltVT.getSimpleVT().SimpleTy) {
2427 Opcode = NVPTX::STV_i8_v2_avar;
2430 Opcode = NVPTX::STV_i16_v2_avar;
2433 Opcode = NVPTX::STV_i32_v2_avar;
2436 Opcode = NVPTX::STV_i64_v2_avar;
2439 Opcode = NVPTX::STV_f32_v2_avar;
2442 Opcode = NVPTX::STV_f64_v2_avar;
2446 case NVPTXISD::StoreV4:
2447 switch (EltVT.getSimpleVT().SimpleTy) {
2451 Opcode = NVPTX::STV_i8_v4_avar;
2454 Opcode = NVPTX::STV_i16_v4_avar;
2457 Opcode = NVPTX::STV_i32_v4_avar;
2460 Opcode = NVPTX::STV_f32_v4_avar;
2465 StOps.push_back(Addr);
2466 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2467 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2468 switch (N->getOpcode()) {
2471 case NVPTXISD::StoreV2:
2472 switch (EltVT.getSimpleVT().SimpleTy) {
2476 Opcode = NVPTX::STV_i8_v2_asi;
2479 Opcode = NVPTX::STV_i16_v2_asi;
2482 Opcode = NVPTX::STV_i32_v2_asi;
2485 Opcode = NVPTX::STV_i64_v2_asi;
2488 Opcode = NVPTX::STV_f32_v2_asi;
2491 Opcode = NVPTX::STV_f64_v2_asi;
2495 case NVPTXISD::StoreV4:
2496 switch (EltVT.getSimpleVT().SimpleTy) {
2500 Opcode = NVPTX::STV_i8_v4_asi;
2503 Opcode = NVPTX::STV_i16_v4_asi;
2506 Opcode = NVPTX::STV_i32_v4_asi;
2509 Opcode = NVPTX::STV_f32_v4_asi;
2514 StOps.push_back(Base);
2515 StOps.push_back(Offset);
2516 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2517 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2519 switch (N->getOpcode()) {
2522 case NVPTXISD::StoreV2:
2523 switch (EltVT.getSimpleVT().SimpleTy) {
2527 Opcode = NVPTX::STV_i8_v2_ari_64;
2530 Opcode = NVPTX::STV_i16_v2_ari_64;
2533 Opcode = NVPTX::STV_i32_v2_ari_64;
2536 Opcode = NVPTX::STV_i64_v2_ari_64;
2539 Opcode = NVPTX::STV_f32_v2_ari_64;
2542 Opcode = NVPTX::STV_f64_v2_ari_64;
2546 case NVPTXISD::StoreV4:
2547 switch (EltVT.getSimpleVT().SimpleTy) {
2551 Opcode = NVPTX::STV_i8_v4_ari_64;
2554 Opcode = NVPTX::STV_i16_v4_ari_64;
2557 Opcode = NVPTX::STV_i32_v4_ari_64;
2560 Opcode = NVPTX::STV_f32_v4_ari_64;
2566 switch (N->getOpcode()) {
2569 case NVPTXISD::StoreV2:
2570 switch (EltVT.getSimpleVT().SimpleTy) {
2574 Opcode = NVPTX::STV_i8_v2_ari;
2577 Opcode = NVPTX::STV_i16_v2_ari;
2580 Opcode = NVPTX::STV_i32_v2_ari;
2583 Opcode = NVPTX::STV_i64_v2_ari;
2586 Opcode = NVPTX::STV_f32_v2_ari;
2589 Opcode = NVPTX::STV_f64_v2_ari;
2593 case NVPTXISD::StoreV4:
2594 switch (EltVT.getSimpleVT().SimpleTy) {
2598 Opcode = NVPTX::STV_i8_v4_ari;
2601 Opcode = NVPTX::STV_i16_v4_ari;
2604 Opcode = NVPTX::STV_i32_v4_ari;
2607 Opcode = NVPTX::STV_f32_v4_ari;
2613 StOps.push_back(Base);
2614 StOps.push_back(Offset);
2617 switch (N->getOpcode()) {
2620 case NVPTXISD::StoreV2:
2621 switch (EltVT.getSimpleVT().SimpleTy) {
2625 Opcode = NVPTX::STV_i8_v2_areg_64;
2628 Opcode = NVPTX::STV_i16_v2_areg_64;
2631 Opcode = NVPTX::STV_i32_v2_areg_64;
2634 Opcode = NVPTX::STV_i64_v2_areg_64;
2637 Opcode = NVPTX::STV_f32_v2_areg_64;
2640 Opcode = NVPTX::STV_f64_v2_areg_64;
2644 case NVPTXISD::StoreV4:
2645 switch (EltVT.getSimpleVT().SimpleTy) {
2649 Opcode = NVPTX::STV_i8_v4_areg_64;
2652 Opcode = NVPTX::STV_i16_v4_areg_64;
2655 Opcode = NVPTX::STV_i32_v4_areg_64;
2658 Opcode = NVPTX::STV_f32_v4_areg_64;
2664 switch (N->getOpcode()) {
2667 case NVPTXISD::StoreV2:
2668 switch (EltVT.getSimpleVT().SimpleTy) {
2672 Opcode = NVPTX::STV_i8_v2_areg;
2675 Opcode = NVPTX::STV_i16_v2_areg;
2678 Opcode = NVPTX::STV_i32_v2_areg;
2681 Opcode = NVPTX::STV_i64_v2_areg;
2684 Opcode = NVPTX::STV_f32_v2_areg;
2687 Opcode = NVPTX::STV_f64_v2_areg;
2691 case NVPTXISD::StoreV4:
2692 switch (EltVT.getSimpleVT().SimpleTy) {
2696 Opcode = NVPTX::STV_i8_v4_areg;
2699 Opcode = NVPTX::STV_i16_v4_areg;
2702 Opcode = NVPTX::STV_i32_v4_areg;
2705 Opcode = NVPTX::STV_f32_v4_areg;
2711 StOps.push_back(N2);
2714 StOps.push_back(Chain);
2716 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2718 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2719 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2720 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2726 bool NVPTXDAGToDAGISel::tryLoadParam(SDNode *Node) {
2727 SDValue Chain = Node->getOperand(0);
2728 SDValue Offset = Node->getOperand(2);
2729 SDValue Flag = Node->getOperand(3);
2731 MemSDNode *Mem = cast<MemSDNode>(Node);
2734 switch (Node->getOpcode()) {
2737 case NVPTXISD::LoadParam:
2740 case NVPTXISD::LoadParamV2:
2743 case NVPTXISD::LoadParamV4:
2748 EVT EltVT = Node->getValueType(0);
2749 EVT MemVT = Mem->getMemoryVT();
2757 switch (MemVT.getSimpleVT().SimpleTy) {
2761 Opc = NVPTX::LoadParamMemI8;
2764 Opc = NVPTX::LoadParamMemI8;
2767 Opc = NVPTX::LoadParamMemI16;
2770 Opc = NVPTX::LoadParamMemI32;
2773 Opc = NVPTX::LoadParamMemI64;
2776 Opc = NVPTX::LoadParamMemF32;
2779 Opc = NVPTX::LoadParamMemF64;
2784 switch (MemVT.getSimpleVT().SimpleTy) {
2788 Opc = NVPTX::LoadParamMemV2I8;
2791 Opc = NVPTX::LoadParamMemV2I8;
2794 Opc = NVPTX::LoadParamMemV2I16;
2797 Opc = NVPTX::LoadParamMemV2I32;
2800 Opc = NVPTX::LoadParamMemV2I64;
2803 Opc = NVPTX::LoadParamMemV2F32;
2806 Opc = NVPTX::LoadParamMemV2F64;
2811 switch (MemVT.getSimpleVT().SimpleTy) {
2815 Opc = NVPTX::LoadParamMemV4I8;
2818 Opc = NVPTX::LoadParamMemV4I8;
2821 Opc = NVPTX::LoadParamMemV4I16;
2824 Opc = NVPTX::LoadParamMemV4I32;
2827 Opc = NVPTX::LoadParamMemV4F32;
2835 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2836 } else if (VecSize == 2) {
2837 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2839 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2840 VTs = CurDAG->getVTList(EVTs);
2843 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2845 SmallVector<SDValue, 2> Ops;
2846 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2847 Ops.push_back(Chain);
2848 Ops.push_back(Flag);
2850 ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VTs, Ops));
2854 bool NVPTXDAGToDAGISel::tryStoreRetval(SDNode *N) {
2856 SDValue Chain = N->getOperand(0);
2857 SDValue Offset = N->getOperand(1);
2858 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2859 MemSDNode *Mem = cast<MemSDNode>(N);
2861 // How many elements do we have?
2862 unsigned NumElts = 1;
2863 switch (N->getOpcode()) {
2866 case NVPTXISD::StoreRetval:
2869 case NVPTXISD::StoreRetvalV2:
2872 case NVPTXISD::StoreRetvalV4:
2877 // Build vector of operands
2878 SmallVector<SDValue, 6> Ops;
2879 for (unsigned i = 0; i < NumElts; ++i)
2880 Ops.push_back(N->getOperand(i + 2));
2881 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2882 Ops.push_back(Chain);
2884 // Determine target opcode
2885 // If we have an i1, use an 8-bit store. The lowering code in
2886 // NVPTXISelLowering will have already emitted an upcast.
2887 unsigned Opcode = 0;
2892 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2896 Opcode = NVPTX::StoreRetvalI8;
2899 Opcode = NVPTX::StoreRetvalI8;
2902 Opcode = NVPTX::StoreRetvalI16;
2905 Opcode = NVPTX::StoreRetvalI32;
2908 Opcode = NVPTX::StoreRetvalI64;
2911 Opcode = NVPTX::StoreRetvalF32;
2914 Opcode = NVPTX::StoreRetvalF64;
2919 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2923 Opcode = NVPTX::StoreRetvalV2I8;
2926 Opcode = NVPTX::StoreRetvalV2I8;
2929 Opcode = NVPTX::StoreRetvalV2I16;
2932 Opcode = NVPTX::StoreRetvalV2I32;
2935 Opcode = NVPTX::StoreRetvalV2I64;
2938 Opcode = NVPTX::StoreRetvalV2F32;
2941 Opcode = NVPTX::StoreRetvalV2F64;
2946 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2950 Opcode = NVPTX::StoreRetvalV4I8;
2953 Opcode = NVPTX::StoreRetvalV4I8;
2956 Opcode = NVPTX::StoreRetvalV4I16;
2959 Opcode = NVPTX::StoreRetvalV4I32;
2962 Opcode = NVPTX::StoreRetvalV4F32;
2969 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2970 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2971 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2972 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2974 ReplaceNode(N, Ret);
2978 bool NVPTXDAGToDAGISel::tryStoreParam(SDNode *N) {
2980 SDValue Chain = N->getOperand(0);
2981 SDValue Param = N->getOperand(1);
2982 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2983 SDValue Offset = N->getOperand(2);
2984 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2985 MemSDNode *Mem = cast<MemSDNode>(N);
2986 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2988 // How many elements do we have?
2989 unsigned NumElts = 1;
2990 switch (N->getOpcode()) {
2993 case NVPTXISD::StoreParamU32:
2994 case NVPTXISD::StoreParamS32:
2995 case NVPTXISD::StoreParam:
2998 case NVPTXISD::StoreParamV2:
3001 case NVPTXISD::StoreParamV4:
3006 // Build vector of operands
3007 SmallVector<SDValue, 8> Ops;
3008 for (unsigned i = 0; i < NumElts; ++i)
3009 Ops.push_back(N->getOperand(i + 3));
3010 Ops.push_back(CurDAG->getTargetConstant(ParamVal, DL, MVT::i32));
3011 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
3012 Ops.push_back(Chain);
3013 Ops.push_back(Flag);
3015 // Determine target opcode
3016 // If we have an i1, use an 8-bit store. The lowering code in
3017 // NVPTXISelLowering will have already emitted an upcast.
3018 unsigned Opcode = 0;
3019 switch (N->getOpcode()) {
3025 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
3029 Opcode = NVPTX::StoreParamI8;
3032 Opcode = NVPTX::StoreParamI8;
3035 Opcode = NVPTX::StoreParamI16;
3038 Opcode = NVPTX::StoreParamI32;
3041 Opcode = NVPTX::StoreParamI64;
3044 Opcode = NVPTX::StoreParamF32;
3047 Opcode = NVPTX::StoreParamF64;
3052 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
3056 Opcode = NVPTX::StoreParamV2I8;
3059 Opcode = NVPTX::StoreParamV2I8;
3062 Opcode = NVPTX::StoreParamV2I16;
3065 Opcode = NVPTX::StoreParamV2I32;
3068 Opcode = NVPTX::StoreParamV2I64;
3071 Opcode = NVPTX::StoreParamV2F32;
3074 Opcode = NVPTX::StoreParamV2F64;
3079 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
3083 Opcode = NVPTX::StoreParamV4I8;
3086 Opcode = NVPTX::StoreParamV4I8;
3089 Opcode = NVPTX::StoreParamV4I16;
3092 Opcode = NVPTX::StoreParamV4I32;
3095 Opcode = NVPTX::StoreParamV4F32;
3101 // Special case: if we have a sign-extend/zero-extend node, insert the
3102 // conversion instruction first, and use that as the value operand to
3103 // the selected StoreParam node.
3104 case NVPTXISD::StoreParamU32: {
3105 Opcode = NVPTX::StoreParamI32;
3106 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
3108 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
3109 MVT::i32, Ops[0], CvtNone);
3110 Ops[0] = SDValue(Cvt, 0);
3113 case NVPTXISD::StoreParamS32: {
3114 Opcode = NVPTX::StoreParamI32;
3115 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
3117 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
3118 MVT::i32, Ops[0], CvtNone);
3119 Ops[0] = SDValue(Cvt, 0);
3124 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
3126 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
3127 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
3128 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
3129 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3131 ReplaceNode(N, Ret);
3135 bool NVPTXDAGToDAGISel::tryTextureIntrinsic(SDNode *N) {
3136 SDValue Chain = N->getOperand(0);
3138 SmallVector<SDValue, 8> Ops;
3140 switch (N->getOpcode()) {
3141 default: return false;
3142 case NVPTXISD::Tex1DFloatS32:
3143 Opc = NVPTX::TEX_1D_F32_S32;
3145 case NVPTXISD::Tex1DFloatFloat:
3146 Opc = NVPTX::TEX_1D_F32_F32;
3148 case NVPTXISD::Tex1DFloatFloatLevel:
3149 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3151 case NVPTXISD::Tex1DFloatFloatGrad:
3152 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3154 case NVPTXISD::Tex1DS32S32:
3155 Opc = NVPTX::TEX_1D_S32_S32;
3157 case NVPTXISD::Tex1DS32Float:
3158 Opc = NVPTX::TEX_1D_S32_F32;
3160 case NVPTXISD::Tex1DS32FloatLevel:
3161 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
3163 case NVPTXISD::Tex1DS32FloatGrad:
3164 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
3166 case NVPTXISD::Tex1DU32S32:
3167 Opc = NVPTX::TEX_1D_U32_S32;
3169 case NVPTXISD::Tex1DU32Float:
3170 Opc = NVPTX::TEX_1D_U32_F32;
3172 case NVPTXISD::Tex1DU32FloatLevel:
3173 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3175 case NVPTXISD::Tex1DU32FloatGrad:
3176 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3178 case NVPTXISD::Tex1DArrayFloatS32:
3179 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
3181 case NVPTXISD::Tex1DArrayFloatFloat:
3182 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3184 case NVPTXISD::Tex1DArrayFloatFloatLevel:
3185 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3187 case NVPTXISD::Tex1DArrayFloatFloatGrad:
3188 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3190 case NVPTXISD::Tex1DArrayS32S32:
3191 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
3193 case NVPTXISD::Tex1DArrayS32Float:
3194 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
3196 case NVPTXISD::Tex1DArrayS32FloatLevel:
3197 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
3199 case NVPTXISD::Tex1DArrayS32FloatGrad:
3200 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
3202 case NVPTXISD::Tex1DArrayU32S32:
3203 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3205 case NVPTXISD::Tex1DArrayU32Float:
3206 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3208 case NVPTXISD::Tex1DArrayU32FloatLevel:
3209 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3211 case NVPTXISD::Tex1DArrayU32FloatGrad:
3212 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3214 case NVPTXISD::Tex2DFloatS32:
3215 Opc = NVPTX::TEX_2D_F32_S32;
3217 case NVPTXISD::Tex2DFloatFloat:
3218 Opc = NVPTX::TEX_2D_F32_F32;
3220 case NVPTXISD::Tex2DFloatFloatLevel:
3221 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3223 case NVPTXISD::Tex2DFloatFloatGrad:
3224 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3226 case NVPTXISD::Tex2DS32S32:
3227 Opc = NVPTX::TEX_2D_S32_S32;
3229 case NVPTXISD::Tex2DS32Float:
3230 Opc = NVPTX::TEX_2D_S32_F32;
3232 case NVPTXISD::Tex2DS32FloatLevel:
3233 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
3235 case NVPTXISD::Tex2DS32FloatGrad:
3236 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
3238 case NVPTXISD::Tex2DU32S32:
3239 Opc = NVPTX::TEX_2D_U32_S32;
3241 case NVPTXISD::Tex2DU32Float:
3242 Opc = NVPTX::TEX_2D_U32_F32;
3244 case NVPTXISD::Tex2DU32FloatLevel:
3245 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3247 case NVPTXISD::Tex2DU32FloatGrad:
3248 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3250 case NVPTXISD::Tex2DArrayFloatS32:
3251 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
3253 case NVPTXISD::Tex2DArrayFloatFloat:
3254 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3256 case NVPTXISD::Tex2DArrayFloatFloatLevel:
3257 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3259 case NVPTXISD::Tex2DArrayFloatFloatGrad:
3260 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3262 case NVPTXISD::Tex2DArrayS32S32:
3263 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
3265 case NVPTXISD::Tex2DArrayS32Float:
3266 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
3268 case NVPTXISD::Tex2DArrayS32FloatLevel:
3269 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
3271 case NVPTXISD::Tex2DArrayS32FloatGrad:
3272 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
3274 case NVPTXISD::Tex2DArrayU32S32:
3275 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3277 case NVPTXISD::Tex2DArrayU32Float:
3278 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3280 case NVPTXISD::Tex2DArrayU32FloatLevel:
3281 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3283 case NVPTXISD::Tex2DArrayU32FloatGrad:
3284 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3286 case NVPTXISD::Tex3DFloatS32:
3287 Opc = NVPTX::TEX_3D_F32_S32;
3289 case NVPTXISD::Tex3DFloatFloat:
3290 Opc = NVPTX::TEX_3D_F32_F32;
3292 case NVPTXISD::Tex3DFloatFloatLevel:
3293 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3295 case NVPTXISD::Tex3DFloatFloatGrad:
3296 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3298 case NVPTXISD::Tex3DS32S32:
3299 Opc = NVPTX::TEX_3D_S32_S32;
3301 case NVPTXISD::Tex3DS32Float:
3302 Opc = NVPTX::TEX_3D_S32_F32;
3304 case NVPTXISD::Tex3DS32FloatLevel:
3305 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
3307 case NVPTXISD::Tex3DS32FloatGrad:
3308 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3310 case NVPTXISD::Tex3DU32S32:
3311 Opc = NVPTX::TEX_3D_U32_S32;
3313 case NVPTXISD::Tex3DU32Float:
3314 Opc = NVPTX::TEX_3D_U32_F32;
3316 case NVPTXISD::Tex3DU32FloatLevel:
3317 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3319 case NVPTXISD::Tex3DU32FloatGrad:
3320 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3322 case NVPTXISD::TexCubeFloatFloat:
3323 Opc = NVPTX::TEX_CUBE_F32_F32;
3325 case NVPTXISD::TexCubeFloatFloatLevel:
3326 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3328 case NVPTXISD::TexCubeS32Float:
3329 Opc = NVPTX::TEX_CUBE_S32_F32;
3331 case NVPTXISD::TexCubeS32FloatLevel:
3332 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3334 case NVPTXISD::TexCubeU32Float:
3335 Opc = NVPTX::TEX_CUBE_U32_F32;
3337 case NVPTXISD::TexCubeU32FloatLevel:
3338 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3340 case NVPTXISD::TexCubeArrayFloatFloat:
3341 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3343 case NVPTXISD::TexCubeArrayFloatFloatLevel:
3344 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3346 case NVPTXISD::TexCubeArrayS32Float:
3347 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3349 case NVPTXISD::TexCubeArrayS32FloatLevel:
3350 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3352 case NVPTXISD::TexCubeArrayU32Float:
3353 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3355 case NVPTXISD::TexCubeArrayU32FloatLevel:
3356 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3358 case NVPTXISD::Tld4R2DFloatFloat:
3359 Opc = NVPTX::TLD4_R_2D_F32_F32;
3361 case NVPTXISD::Tld4G2DFloatFloat:
3362 Opc = NVPTX::TLD4_G_2D_F32_F32;
3364 case NVPTXISD::Tld4B2DFloatFloat:
3365 Opc = NVPTX::TLD4_B_2D_F32_F32;
3367 case NVPTXISD::Tld4A2DFloatFloat:
3368 Opc = NVPTX::TLD4_A_2D_F32_F32;
3370 case NVPTXISD::Tld4R2DS64Float:
3371 Opc = NVPTX::TLD4_R_2D_S32_F32;
3373 case NVPTXISD::Tld4G2DS64Float:
3374 Opc = NVPTX::TLD4_G_2D_S32_F32;
3376 case NVPTXISD::Tld4B2DS64Float:
3377 Opc = NVPTX::TLD4_B_2D_S32_F32;
3379 case NVPTXISD::Tld4A2DS64Float:
3380 Opc = NVPTX::TLD4_A_2D_S32_F32;
3382 case NVPTXISD::Tld4R2DU64Float:
3383 Opc = NVPTX::TLD4_R_2D_U32_F32;
3385 case NVPTXISD::Tld4G2DU64Float:
3386 Opc = NVPTX::TLD4_G_2D_U32_F32;
3388 case NVPTXISD::Tld4B2DU64Float:
3389 Opc = NVPTX::TLD4_B_2D_U32_F32;
3391 case NVPTXISD::Tld4A2DU64Float:
3392 Opc = NVPTX::TLD4_A_2D_U32_F32;
3394 case NVPTXISD::TexUnified1DFloatS32:
3395 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3397 case NVPTXISD::TexUnified1DFloatFloat:
3398 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3400 case NVPTXISD::TexUnified1DFloatFloatLevel:
3401 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3403 case NVPTXISD::TexUnified1DFloatFloatGrad:
3404 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3406 case NVPTXISD::TexUnified1DS32S32:
3407 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3409 case NVPTXISD::TexUnified1DS32Float:
3410 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3412 case NVPTXISD::TexUnified1DS32FloatLevel:
3413 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3415 case NVPTXISD::TexUnified1DS32FloatGrad:
3416 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3418 case NVPTXISD::TexUnified1DU32S32:
3419 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3421 case NVPTXISD::TexUnified1DU32Float:
3422 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3424 case NVPTXISD::TexUnified1DU32FloatLevel:
3425 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3427 case NVPTXISD::TexUnified1DU32FloatGrad:
3428 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3430 case NVPTXISD::TexUnified1DArrayFloatS32:
3431 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3433 case NVPTXISD::TexUnified1DArrayFloatFloat:
3434 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3436 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
3437 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3439 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
3440 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3442 case NVPTXISD::TexUnified1DArrayS32S32:
3443 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3445 case NVPTXISD::TexUnified1DArrayS32Float:
3446 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3448 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
3449 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3451 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
3452 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3454 case NVPTXISD::TexUnified1DArrayU32S32:
3455 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3457 case NVPTXISD::TexUnified1DArrayU32Float:
3458 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3460 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
3461 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3463 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
3464 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3466 case NVPTXISD::TexUnified2DFloatS32:
3467 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3469 case NVPTXISD::TexUnified2DFloatFloat:
3470 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3472 case NVPTXISD::TexUnified2DFloatFloatLevel:
3473 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3475 case NVPTXISD::TexUnified2DFloatFloatGrad:
3476 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3478 case NVPTXISD::TexUnified2DS32S32:
3479 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3481 case NVPTXISD::TexUnified2DS32Float:
3482 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3484 case NVPTXISD::TexUnified2DS32FloatLevel:
3485 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3487 case NVPTXISD::TexUnified2DS32FloatGrad:
3488 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3490 case NVPTXISD::TexUnified2DU32S32:
3491 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3493 case NVPTXISD::TexUnified2DU32Float:
3494 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3496 case NVPTXISD::TexUnified2DU32FloatLevel:
3497 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3499 case NVPTXISD::TexUnified2DU32FloatGrad:
3500 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3502 case NVPTXISD::TexUnified2DArrayFloatS32:
3503 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3505 case NVPTXISD::TexUnified2DArrayFloatFloat:
3506 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3508 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
3509 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3511 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
3512 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3514 case NVPTXISD::TexUnified2DArrayS32S32:
3515 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3517 case NVPTXISD::TexUnified2DArrayS32Float:
3518 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3520 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
3521 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3523 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
3524 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3526 case NVPTXISD::TexUnified2DArrayU32S32:
3527 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3529 case NVPTXISD::TexUnified2DArrayU32Float:
3530 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3532 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
3533 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3535 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
3536 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3538 case NVPTXISD::TexUnified3DFloatS32:
3539 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3541 case NVPTXISD::TexUnified3DFloatFloat:
3542 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3544 case NVPTXISD::TexUnified3DFloatFloatLevel:
3545 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3547 case NVPTXISD::TexUnified3DFloatFloatGrad:
3548 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3550 case NVPTXISD::TexUnified3DS32S32:
3551 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3553 case NVPTXISD::TexUnified3DS32Float:
3554 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3556 case NVPTXISD::TexUnified3DS32FloatLevel:
3557 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3559 case NVPTXISD::TexUnified3DS32FloatGrad:
3560 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3562 case NVPTXISD::TexUnified3DU32S32:
3563 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3565 case NVPTXISD::TexUnified3DU32Float:
3566 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3568 case NVPTXISD::TexUnified3DU32FloatLevel:
3569 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3571 case NVPTXISD::TexUnified3DU32FloatGrad:
3572 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3574 case NVPTXISD::TexUnifiedCubeFloatFloat:
3575 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3577 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
3578 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3580 case NVPTXISD::TexUnifiedCubeS32Float:
3581 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3583 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
3584 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3586 case NVPTXISD::TexUnifiedCubeU32Float:
3587 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3589 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
3590 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3592 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
3593 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3595 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
3596 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3598 case NVPTXISD::TexUnifiedCubeArrayS32Float:
3599 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3601 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
3602 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3604 case NVPTXISD::TexUnifiedCubeArrayU32Float:
3605 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3607 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
3608 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3610 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
3611 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3613 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
3614 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3616 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
3617 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3619 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
3620 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3622 case NVPTXISD::Tld4UnifiedR2DS64Float:
3623 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3625 case NVPTXISD::Tld4UnifiedG2DS64Float:
3626 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3628 case NVPTXISD::Tld4UnifiedB2DS64Float:
3629 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3631 case NVPTXISD::Tld4UnifiedA2DS64Float:
3632 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3634 case NVPTXISD::Tld4UnifiedR2DU64Float:
3635 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3637 case NVPTXISD::Tld4UnifiedG2DU64Float:
3638 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3640 case NVPTXISD::Tld4UnifiedB2DU64Float:
3641 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3643 case NVPTXISD::Tld4UnifiedA2DU64Float:
3644 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
3648 // Copy over operands
3649 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
3650 Ops.push_back(N->getOperand(i));
3653 Ops.push_back(Chain);
3654 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops));
3658 bool NVPTXDAGToDAGISel::trySurfaceIntrinsic(SDNode *N) {
3659 SDValue Chain = N->getOperand(0);
3660 SDValue TexHandle = N->getOperand(1);
3662 SmallVector<SDValue, 8> Ops;
3663 switch (N->getOpcode()) {
3664 default: return false;
3665 case NVPTXISD::Suld1DI8Clamp:
3666 Opc = NVPTX::SULD_1D_I8_CLAMP;
3667 Ops.push_back(TexHandle);
3668 Ops.push_back(N->getOperand(2));
3669 Ops.push_back(Chain);
3671 case NVPTXISD::Suld1DI16Clamp:
3672 Opc = NVPTX::SULD_1D_I16_CLAMP;
3673 Ops.push_back(TexHandle);
3674 Ops.push_back(N->getOperand(2));
3675 Ops.push_back(Chain);
3677 case NVPTXISD::Suld1DI32Clamp:
3678 Opc = NVPTX::SULD_1D_I32_CLAMP;
3679 Ops.push_back(TexHandle);
3680 Ops.push_back(N->getOperand(2));
3681 Ops.push_back(Chain);
3683 case NVPTXISD::Suld1DI64Clamp:
3684 Opc = NVPTX::SULD_1D_I64_CLAMP;
3685 Ops.push_back(TexHandle);
3686 Ops.push_back(N->getOperand(2));
3687 Ops.push_back(Chain);
3689 case NVPTXISD::Suld1DV2I8Clamp:
3690 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3691 Ops.push_back(TexHandle);
3692 Ops.push_back(N->getOperand(2));
3693 Ops.push_back(Chain);
3695 case NVPTXISD::Suld1DV2I16Clamp:
3696 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3697 Ops.push_back(TexHandle);
3698 Ops.push_back(N->getOperand(2));
3699 Ops.push_back(Chain);
3701 case NVPTXISD::Suld1DV2I32Clamp:
3702 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3703 Ops.push_back(TexHandle);
3704 Ops.push_back(N->getOperand(2));
3705 Ops.push_back(Chain);
3707 case NVPTXISD::Suld1DV2I64Clamp:
3708 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3709 Ops.push_back(TexHandle);
3710 Ops.push_back(N->getOperand(2));
3711 Ops.push_back(Chain);
3713 case NVPTXISD::Suld1DV4I8Clamp:
3714 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3715 Ops.push_back(TexHandle);
3716 Ops.push_back(N->getOperand(2));
3717 Ops.push_back(Chain);
3719 case NVPTXISD::Suld1DV4I16Clamp:
3720 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3721 Ops.push_back(TexHandle);
3722 Ops.push_back(N->getOperand(2));
3723 Ops.push_back(Chain);
3725 case NVPTXISD::Suld1DV4I32Clamp:
3726 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3727 Ops.push_back(TexHandle);
3728 Ops.push_back(N->getOperand(2));
3729 Ops.push_back(Chain);
3731 case NVPTXISD::Suld1DArrayI8Clamp:
3732 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3733 Ops.push_back(TexHandle);
3734 Ops.push_back(N->getOperand(2));
3735 Ops.push_back(N->getOperand(3));
3736 Ops.push_back(Chain);
3738 case NVPTXISD::Suld1DArrayI16Clamp:
3739 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3740 Ops.push_back(TexHandle);
3741 Ops.push_back(N->getOperand(2));
3742 Ops.push_back(N->getOperand(3));
3743 Ops.push_back(Chain);
3745 case NVPTXISD::Suld1DArrayI32Clamp:
3746 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3747 Ops.push_back(TexHandle);
3748 Ops.push_back(N->getOperand(2));
3749 Ops.push_back(N->getOperand(3));
3750 Ops.push_back(Chain);
3752 case NVPTXISD::Suld1DArrayI64Clamp:
3753 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3754 Ops.push_back(TexHandle);
3755 Ops.push_back(N->getOperand(2));
3756 Ops.push_back(N->getOperand(3));
3757 Ops.push_back(Chain);
3759 case NVPTXISD::Suld1DArrayV2I8Clamp:
3760 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3761 Ops.push_back(TexHandle);
3762 Ops.push_back(N->getOperand(2));
3763 Ops.push_back(N->getOperand(3));
3764 Ops.push_back(Chain);
3766 case NVPTXISD::Suld1DArrayV2I16Clamp:
3767 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3768 Ops.push_back(TexHandle);
3769 Ops.push_back(N->getOperand(2));
3770 Ops.push_back(N->getOperand(3));
3771 Ops.push_back(Chain);
3773 case NVPTXISD::Suld1DArrayV2I32Clamp:
3774 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3775 Ops.push_back(TexHandle);
3776 Ops.push_back(N->getOperand(2));
3777 Ops.push_back(N->getOperand(3));
3778 Ops.push_back(Chain);
3780 case NVPTXISD::Suld1DArrayV2I64Clamp:
3781 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3782 Ops.push_back(TexHandle);
3783 Ops.push_back(N->getOperand(2));
3784 Ops.push_back(N->getOperand(3));
3785 Ops.push_back(Chain);
3787 case NVPTXISD::Suld1DArrayV4I8Clamp:
3788 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3789 Ops.push_back(TexHandle);
3790 Ops.push_back(N->getOperand(2));
3791 Ops.push_back(N->getOperand(3));
3792 Ops.push_back(Chain);
3794 case NVPTXISD::Suld1DArrayV4I16Clamp:
3795 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3796 Ops.push_back(TexHandle);
3797 Ops.push_back(N->getOperand(2));
3798 Ops.push_back(N->getOperand(3));
3799 Ops.push_back(Chain);
3801 case NVPTXISD::Suld1DArrayV4I32Clamp:
3802 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3803 Ops.push_back(TexHandle);
3804 Ops.push_back(N->getOperand(2));
3805 Ops.push_back(N->getOperand(3));
3806 Ops.push_back(Chain);
3808 case NVPTXISD::Suld2DI8Clamp:
3809 Opc = NVPTX::SULD_2D_I8_CLAMP;
3810 Ops.push_back(TexHandle);
3811 Ops.push_back(N->getOperand(2));
3812 Ops.push_back(N->getOperand(3));
3813 Ops.push_back(Chain);
3815 case NVPTXISD::Suld2DI16Clamp:
3816 Opc = NVPTX::SULD_2D_I16_CLAMP;
3817 Ops.push_back(TexHandle);
3818 Ops.push_back(N->getOperand(2));
3819 Ops.push_back(N->getOperand(3));
3820 Ops.push_back(Chain);
3822 case NVPTXISD::Suld2DI32Clamp:
3823 Opc = NVPTX::SULD_2D_I32_CLAMP;
3824 Ops.push_back(TexHandle);
3825 Ops.push_back(N->getOperand(2));
3826 Ops.push_back(N->getOperand(3));
3827 Ops.push_back(Chain);
3829 case NVPTXISD::Suld2DI64Clamp:
3830 Opc = NVPTX::SULD_2D_I64_CLAMP;
3831 Ops.push_back(TexHandle);
3832 Ops.push_back(N->getOperand(2));
3833 Ops.push_back(N->getOperand(3));
3834 Ops.push_back(Chain);
3836 case NVPTXISD::Suld2DV2I8Clamp:
3837 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3838 Ops.push_back(TexHandle);
3839 Ops.push_back(N->getOperand(2));
3840 Ops.push_back(N->getOperand(3));
3841 Ops.push_back(Chain);
3843 case NVPTXISD::Suld2DV2I16Clamp:
3844 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3845 Ops.push_back(TexHandle);
3846 Ops.push_back(N->getOperand(2));
3847 Ops.push_back(N->getOperand(3));
3848 Ops.push_back(Chain);
3850 case NVPTXISD::Suld2DV2I32Clamp:
3851 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3852 Ops.push_back(TexHandle);
3853 Ops.push_back(N->getOperand(2));
3854 Ops.push_back(N->getOperand(3));
3855 Ops.push_back(Chain);
3857 case NVPTXISD::Suld2DV2I64Clamp:
3858 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3859 Ops.push_back(TexHandle);
3860 Ops.push_back(N->getOperand(2));
3861 Ops.push_back(N->getOperand(3));
3862 Ops.push_back(Chain);
3864 case NVPTXISD::Suld2DV4I8Clamp:
3865 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3866 Ops.push_back(TexHandle);
3867 Ops.push_back(N->getOperand(2));
3868 Ops.push_back(N->getOperand(3));
3869 Ops.push_back(Chain);
3871 case NVPTXISD::Suld2DV4I16Clamp:
3872 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3873 Ops.push_back(TexHandle);
3874 Ops.push_back(N->getOperand(2));
3875 Ops.push_back(N->getOperand(3));
3876 Ops.push_back(Chain);
3878 case NVPTXISD::Suld2DV4I32Clamp:
3879 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3880 Ops.push_back(TexHandle);
3881 Ops.push_back(N->getOperand(2));
3882 Ops.push_back(N->getOperand(3));
3883 Ops.push_back(Chain);
3885 case NVPTXISD::Suld2DArrayI8Clamp:
3886 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3887 Ops.push_back(TexHandle);
3888 Ops.push_back(N->getOperand(2));
3889 Ops.push_back(N->getOperand(3));
3890 Ops.push_back(N->getOperand(4));
3891 Ops.push_back(Chain);
3893 case NVPTXISD::Suld2DArrayI16Clamp:
3894 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3895 Ops.push_back(TexHandle);
3896 Ops.push_back(N->getOperand(2));
3897 Ops.push_back(N->getOperand(3));
3898 Ops.push_back(N->getOperand(4));
3899 Ops.push_back(Chain);
3901 case NVPTXISD::Suld2DArrayI32Clamp:
3902 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3903 Ops.push_back(TexHandle);
3904 Ops.push_back(N->getOperand(2));
3905 Ops.push_back(N->getOperand(3));
3906 Ops.push_back(N->getOperand(4));
3907 Ops.push_back(Chain);
3909 case NVPTXISD::Suld2DArrayI64Clamp:
3910 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3911 Ops.push_back(TexHandle);
3912 Ops.push_back(N->getOperand(2));
3913 Ops.push_back(N->getOperand(3));
3914 Ops.push_back(N->getOperand(4));
3915 Ops.push_back(Chain);
3917 case NVPTXISD::Suld2DArrayV2I8Clamp:
3918 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3919 Ops.push_back(TexHandle);
3920 Ops.push_back(N->getOperand(2));
3921 Ops.push_back(N->getOperand(3));
3922 Ops.push_back(N->getOperand(4));
3923 Ops.push_back(Chain);
3925 case NVPTXISD::Suld2DArrayV2I16Clamp:
3926 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3927 Ops.push_back(TexHandle);
3928 Ops.push_back(N->getOperand(2));
3929 Ops.push_back(N->getOperand(3));
3930 Ops.push_back(N->getOperand(4));
3931 Ops.push_back(Chain);
3933 case NVPTXISD::Suld2DArrayV2I32Clamp:
3934 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3935 Ops.push_back(TexHandle);
3936 Ops.push_back(N->getOperand(2));
3937 Ops.push_back(N->getOperand(3));
3938 Ops.push_back(N->getOperand(4));
3939 Ops.push_back(Chain);
3941 case NVPTXISD::Suld2DArrayV2I64Clamp:
3942 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3943 Ops.push_back(TexHandle);
3944 Ops.push_back(N->getOperand(2));
3945 Ops.push_back(N->getOperand(3));
3946 Ops.push_back(N->getOperand(4));
3947 Ops.push_back(Chain);
3949 case NVPTXISD::Suld2DArrayV4I8Clamp:
3950 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3951 Ops.push_back(TexHandle);
3952 Ops.push_back(N->getOperand(2));
3953 Ops.push_back(N->getOperand(3));
3954 Ops.push_back(N->getOperand(4));
3955 Ops.push_back(Chain);
3957 case NVPTXISD::Suld2DArrayV4I16Clamp:
3958 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3959 Ops.push_back(TexHandle);
3960 Ops.push_back(N->getOperand(2));
3961 Ops.push_back(N->getOperand(3));
3962 Ops.push_back(N->getOperand(4));
3963 Ops.push_back(Chain);
3965 case NVPTXISD::Suld2DArrayV4I32Clamp:
3966 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3967 Ops.push_back(TexHandle);
3968 Ops.push_back(N->getOperand(2));
3969 Ops.push_back(N->getOperand(3));
3970 Ops.push_back(N->getOperand(4));
3971 Ops.push_back(Chain);
3973 case NVPTXISD::Suld3DI8Clamp:
3974 Opc = NVPTX::SULD_3D_I8_CLAMP;
3975 Ops.push_back(TexHandle);
3976 Ops.push_back(N->getOperand(2));
3977 Ops.push_back(N->getOperand(3));
3978 Ops.push_back(N->getOperand(4));
3979 Ops.push_back(Chain);
3981 case NVPTXISD::Suld3DI16Clamp:
3982 Opc = NVPTX::SULD_3D_I16_CLAMP;
3983 Ops.push_back(TexHandle);
3984 Ops.push_back(N->getOperand(2));
3985 Ops.push_back(N->getOperand(3));
3986 Ops.push_back(N->getOperand(4));
3987 Ops.push_back(Chain);
3989 case NVPTXISD::Suld3DI32Clamp:
3990 Opc = NVPTX::SULD_3D_I32_CLAMP;
3991 Ops.push_back(TexHandle);
3992 Ops.push_back(N->getOperand(2));
3993 Ops.push_back(N->getOperand(3));
3994 Ops.push_back(N->getOperand(4));
3995 Ops.push_back(Chain);
3997 case NVPTXISD::Suld3DI64Clamp:
3998 Opc = NVPTX::SULD_3D_I64_CLAMP;
3999 Ops.push_back(TexHandle);
4000 Ops.push_back(N->getOperand(2));
4001 Ops.push_back(N->getOperand(3));
4002 Ops.push_back(N->getOperand(4));
4003 Ops.push_back(Chain);
4005 case NVPTXISD::Suld3DV2I8Clamp:
4006 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
4007 Ops.push_back(TexHandle);
4008 Ops.push_back(N->getOperand(2));
4009 Ops.push_back(N->getOperand(3));
4010 Ops.push_back(N->getOperand(4));
4011 Ops.push_back(Chain);
4013 case NVPTXISD::Suld3DV2I16Clamp:
4014 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
4015 Ops.push_back(TexHandle);
4016 Ops.push_back(N->getOperand(2));
4017 Ops.push_back(N->getOperand(3));
4018 Ops.push_back(N->getOperand(4));
4019 Ops.push_back(Chain);
4021 case NVPTXISD::Suld3DV2I32Clamp:
4022 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
4023 Ops.push_back(TexHandle);
4024 Ops.push_back(N->getOperand(2));
4025 Ops.push_back(N->getOperand(3));
4026 Ops.push_back(N->getOperand(4));
4027 Ops.push_back(Chain);
4029 case NVPTXISD::Suld3DV2I64Clamp:
4030 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
4031 Ops.push_back(TexHandle);
4032 Ops.push_back(N->getOperand(2));
4033 Ops.push_back(N->getOperand(3));
4034 Ops.push_back(N->getOperand(4));
4035 Ops.push_back(Chain);
4037 case NVPTXISD::Suld3DV4I8Clamp:
4038 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
4039 Ops.push_back(TexHandle);
4040 Ops.push_back(N->getOperand(2));
4041 Ops.push_back(N->getOperand(3));
4042 Ops.push_back(N->getOperand(4));
4043 Ops.push_back(Chain);
4045 case NVPTXISD::Suld3DV4I16Clamp:
4046 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
4047 Ops.push_back(TexHandle);
4048 Ops.push_back(N->getOperand(2));
4049 Ops.push_back(N->getOperand(3));
4050 Ops.push_back(N->getOperand(4));
4051 Ops.push_back(Chain);
4053 case NVPTXISD::Suld3DV4I32Clamp:
4054 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
4055 Ops.push_back(TexHandle);
4056 Ops.push_back(N->getOperand(2));
4057 Ops.push_back(N->getOperand(3));
4058 Ops.push_back(N->getOperand(4));
4059 Ops.push_back(Chain);
4061 case NVPTXISD::Suld1DI8Trap:
4062 Opc = NVPTX::SULD_1D_I8_TRAP;
4063 Ops.push_back(TexHandle);
4064 Ops.push_back(N->getOperand(2));
4065 Ops.push_back(Chain);
4067 case NVPTXISD::Suld1DI16Trap:
4068 Opc = NVPTX::SULD_1D_I16_TRAP;
4069 Ops.push_back(TexHandle);
4070 Ops.push_back(N->getOperand(2));
4071 Ops.push_back(Chain);
4073 case NVPTXISD::Suld1DI32Trap:
4074 Opc = NVPTX::SULD_1D_I32_TRAP;
4075 Ops.push_back(TexHandle);
4076 Ops.push_back(N->getOperand(2));
4077 Ops.push_back(Chain);
4079 case NVPTXISD::Suld1DI64Trap:
4080 Opc = NVPTX::SULD_1D_I64_TRAP;
4081 Ops.push_back(TexHandle);
4082 Ops.push_back(N->getOperand(2));
4083 Ops.push_back(Chain);
4085 case NVPTXISD::Suld1DV2I8Trap:
4086 Opc = NVPTX::SULD_1D_V2I8_TRAP;
4087 Ops.push_back(TexHandle);
4088 Ops.push_back(N->getOperand(2));
4089 Ops.push_back(Chain);
4091 case NVPTXISD::Suld1DV2I16Trap:
4092 Opc = NVPTX::SULD_1D_V2I16_TRAP;
4093 Ops.push_back(TexHandle);
4094 Ops.push_back(N->getOperand(2));
4095 Ops.push_back(Chain);
4097 case NVPTXISD::Suld1DV2I32Trap:
4098 Opc = NVPTX::SULD_1D_V2I32_TRAP;
4099 Ops.push_back(TexHandle);
4100 Ops.push_back(N->getOperand(2));
4101 Ops.push_back(Chain);
4103 case NVPTXISD::Suld1DV2I64Trap:
4104 Opc = NVPTX::SULD_1D_V2I64_TRAP;
4105 Ops.push_back(TexHandle);
4106 Ops.push_back(N->getOperand(2));
4107 Ops.push_back(Chain);
4109 case NVPTXISD::Suld1DV4I8Trap:
4110 Opc = NVPTX::SULD_1D_V4I8_TRAP;
4111 Ops.push_back(TexHandle);
4112 Ops.push_back(N->getOperand(2));
4113 Ops.push_back(Chain);
4115 case NVPTXISD::Suld1DV4I16Trap:
4116 Opc = NVPTX::SULD_1D_V4I16_TRAP;
4117 Ops.push_back(TexHandle);
4118 Ops.push_back(N->getOperand(2));
4119 Ops.push_back(Chain);
4121 case NVPTXISD::Suld1DV4I32Trap:
4122 Opc = NVPTX::SULD_1D_V4I32_TRAP;
4123 Ops.push_back(TexHandle);
4124 Ops.push_back(N->getOperand(2));
4125 Ops.push_back(Chain);
4127 case NVPTXISD::Suld1DArrayI8Trap:
4128 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4129 Ops.push_back(TexHandle);
4130 Ops.push_back(N->getOperand(2));
4131 Ops.push_back(N->getOperand(3));
4132 Ops.push_back(Chain);
4134 case NVPTXISD::Suld1DArrayI16Trap:
4135 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4136 Ops.push_back(TexHandle);
4137 Ops.push_back(N->getOperand(2));
4138 Ops.push_back(N->getOperand(3));
4139 Ops.push_back(Chain);
4141 case NVPTXISD::Suld1DArrayI32Trap:
4142 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4143 Ops.push_back(TexHandle);
4144 Ops.push_back(N->getOperand(2));
4145 Ops.push_back(N->getOperand(3));
4146 Ops.push_back(Chain);
4148 case NVPTXISD::Suld1DArrayI64Trap:
4149 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4150 Ops.push_back(TexHandle);
4151 Ops.push_back(N->getOperand(2));
4152 Ops.push_back(N->getOperand(3));
4153 Ops.push_back(Chain);
4155 case NVPTXISD::Suld1DArrayV2I8Trap:
4156 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4157 Ops.push_back(TexHandle);
4158 Ops.push_back(N->getOperand(2));
4159 Ops.push_back(N->getOperand(3));
4160 Ops.push_back(Chain);
4162 case NVPTXISD::Suld1DArrayV2I16Trap:
4163 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4164 Ops.push_back(TexHandle);
4165 Ops.push_back(N->getOperand(2));
4166 Ops.push_back(N->getOperand(3));
4167 Ops.push_back(Chain);
4169 case NVPTXISD::Suld1DArrayV2I32Trap:
4170 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4171 Ops.push_back(TexHandle);
4172 Ops.push_back(N->getOperand(2));
4173 Ops.push_back(N->getOperand(3));
4174 Ops.push_back(Chain);
4176 case NVPTXISD::Suld1DArrayV2I64Trap:
4177 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4178 Ops.push_back(TexHandle);
4179 Ops.push_back(N->getOperand(2));
4180 Ops.push_back(N->getOperand(3));
4181 Ops.push_back(Chain);
4183 case NVPTXISD::Suld1DArrayV4I8Trap:
4184 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4185 Ops.push_back(TexHandle);
4186 Ops.push_back(N->getOperand(2));
4187 Ops.push_back(N->getOperand(3));
4188 Ops.push_back(Chain);
4190 case NVPTXISD::Suld1DArrayV4I16Trap:
4191 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4192 Ops.push_back(TexHandle);
4193 Ops.push_back(N->getOperand(2));
4194 Ops.push_back(N->getOperand(3));
4195 Ops.push_back(Chain);
4197 case NVPTXISD::Suld1DArrayV4I32Trap:
4198 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4199 Ops.push_back(TexHandle);
4200 Ops.push_back(N->getOperand(2));
4201 Ops.push_back(N->getOperand(3));
4202 Ops.push_back(Chain);
4204 case NVPTXISD::Suld2DI8Trap:
4205 Opc = NVPTX::SULD_2D_I8_TRAP;
4206 Ops.push_back(TexHandle);
4207 Ops.push_back(N->getOperand(2));
4208 Ops.push_back(N->getOperand(3));
4209 Ops.push_back(Chain);
4211 case NVPTXISD::Suld2DI16Trap:
4212 Opc = NVPTX::SULD_2D_I16_TRAP;
4213 Ops.push_back(TexHandle);
4214 Ops.push_back(N->getOperand(2));
4215 Ops.push_back(N->getOperand(3));
4216 Ops.push_back(Chain);
4218 case NVPTXISD::Suld2DI32Trap:
4219 Opc = NVPTX::SULD_2D_I32_TRAP;
4220 Ops.push_back(TexHandle);
4221 Ops.push_back(N->getOperand(2));
4222 Ops.push_back(N->getOperand(3));
4223 Ops.push_back(Chain);
4225 case NVPTXISD::Suld2DI64Trap:
4226 Opc = NVPTX::SULD_2D_I64_TRAP;
4227 Ops.push_back(TexHandle);
4228 Ops.push_back(N->getOperand(2));
4229 Ops.push_back(N->getOperand(3));
4230 Ops.push_back(Chain);
4232 case NVPTXISD::Suld2DV2I8Trap:
4233 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4234 Ops.push_back(TexHandle);
4235 Ops.push_back(N->getOperand(2));
4236 Ops.push_back(N->getOperand(3));
4237 Ops.push_back(Chain);
4239 case NVPTXISD::Suld2DV2I16Trap:
4240 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4241 Ops.push_back(TexHandle);
4242 Ops.push_back(N->getOperand(2));
4243 Ops.push_back(N->getOperand(3));
4244 Ops.push_back(Chain);
4246 case NVPTXISD::Suld2DV2I32Trap:
4247 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4248 Ops.push_back(TexHandle);
4249 Ops.push_back(N->getOperand(2));
4250 Ops.push_back(N->getOperand(3));
4251 Ops.push_back(Chain);
4253 case NVPTXISD::Suld2DV2I64Trap:
4254 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4255 Ops.push_back(TexHandle);
4256 Ops.push_back(N->getOperand(2));
4257 Ops.push_back(N->getOperand(3));
4258 Ops.push_back(Chain);
4260 case NVPTXISD::Suld2DV4I8Trap:
4261 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4262 Ops.push_back(TexHandle);
4263 Ops.push_back(N->getOperand(2));
4264 Ops.push_back(N->getOperand(3));
4265 Ops.push_back(Chain);
4267 case NVPTXISD::Suld2DV4I16Trap:
4268 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4269 Ops.push_back(TexHandle);
4270 Ops.push_back(N->getOperand(2));
4271 Ops.push_back(N->getOperand(3));
4272 Ops.push_back(Chain);
4274 case NVPTXISD::Suld2DV4I32Trap:
4275 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4276 Ops.push_back(TexHandle);
4277 Ops.push_back(N->getOperand(2));
4278 Ops.push_back(N->getOperand(3));
4279 Ops.push_back(Chain);
4281 case NVPTXISD::Suld2DArrayI8Trap:
4282 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4283 Ops.push_back(TexHandle);
4284 Ops.push_back(N->getOperand(2));
4285 Ops.push_back(N->getOperand(3));
4286 Ops.push_back(N->getOperand(4));
4287 Ops.push_back(Chain);
4289 case NVPTXISD::Suld2DArrayI16Trap:
4290 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4291 Ops.push_back(TexHandle);
4292 Ops.push_back(N->getOperand(2));
4293 Ops.push_back(N->getOperand(3));
4294 Ops.push_back(N->getOperand(4));
4295 Ops.push_back(Chain);
4297 case NVPTXISD::Suld2DArrayI32Trap:
4298 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4299 Ops.push_back(TexHandle);
4300 Ops.push_back(N->getOperand(2));
4301 Ops.push_back(N->getOperand(3));
4302 Ops.push_back(N->getOperand(4));
4303 Ops.push_back(Chain);
4305 case NVPTXISD::Suld2DArrayI64Trap:
4306 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4307 Ops.push_back(TexHandle);
4308 Ops.push_back(N->getOperand(2));
4309 Ops.push_back(N->getOperand(3));
4310 Ops.push_back(N->getOperand(4));
4311 Ops.push_back(Chain);
4313 case NVPTXISD::Suld2DArrayV2I8Trap:
4314 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4315 Ops.push_back(TexHandle);
4316 Ops.push_back(N->getOperand(2));
4317 Ops.push_back(N->getOperand(3));
4318 Ops.push_back(N->getOperand(4));
4319 Ops.push_back(Chain);
4321 case NVPTXISD::Suld2DArrayV2I16Trap:
4322 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4323 Ops.push_back(TexHandle);
4324 Ops.push_back(N->getOperand(2));
4325 Ops.push_back(N->getOperand(3));
4326 Ops.push_back(N->getOperand(4));
4327 Ops.push_back(Chain);
4329 case NVPTXISD::Suld2DArrayV2I32Trap:
4330 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4331 Ops.push_back(TexHandle);
4332 Ops.push_back(N->getOperand(2));
4333 Ops.push_back(N->getOperand(3));
4334 Ops.push_back(N->getOperand(4));
4335 Ops.push_back(Chain);
4337 case NVPTXISD::Suld2DArrayV2I64Trap:
4338 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4339 Ops.push_back(TexHandle);
4340 Ops.push_back(N->getOperand(2));
4341 Ops.push_back(N->getOperand(3));
4342 Ops.push_back(N->getOperand(4));
4343 Ops.push_back(Chain);
4345 case NVPTXISD::Suld2DArrayV4I8Trap:
4346 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4347 Ops.push_back(TexHandle);
4348 Ops.push_back(N->getOperand(2));
4349 Ops.push_back(N->getOperand(3));
4350 Ops.push_back(N->getOperand(4));
4351 Ops.push_back(Chain);
4353 case NVPTXISD::Suld2DArrayV4I16Trap:
4354 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4355 Ops.push_back(TexHandle);
4356 Ops.push_back(N->getOperand(2));
4357 Ops.push_back(N->getOperand(3));
4358 Ops.push_back(N->getOperand(4));
4359 Ops.push_back(Chain);
4361 case NVPTXISD::Suld2DArrayV4I32Trap:
4362 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4363 Ops.push_back(TexHandle);
4364 Ops.push_back(N->getOperand(2));
4365 Ops.push_back(N->getOperand(3));
4366 Ops.push_back(N->getOperand(4));
4367 Ops.push_back(Chain);
4369 case NVPTXISD::Suld3DI8Trap:
4370 Opc = NVPTX::SULD_3D_I8_TRAP;
4371 Ops.push_back(TexHandle);
4372 Ops.push_back(N->getOperand(2));
4373 Ops.push_back(N->getOperand(3));
4374 Ops.push_back(N->getOperand(4));
4375 Ops.push_back(Chain);
4377 case NVPTXISD::Suld3DI16Trap:
4378 Opc = NVPTX::SULD_3D_I16_TRAP;
4379 Ops.push_back(TexHandle);
4380 Ops.push_back(N->getOperand(2));
4381 Ops.push_back(N->getOperand(3));
4382 Ops.push_back(N->getOperand(4));
4383 Ops.push_back(Chain);
4385 case NVPTXISD::Suld3DI32Trap:
4386 Opc = NVPTX::SULD_3D_I32_TRAP;
4387 Ops.push_back(TexHandle);
4388 Ops.push_back(N->getOperand(2));
4389 Ops.push_back(N->getOperand(3));
4390 Ops.push_back(N->getOperand(4));
4391 Ops.push_back(Chain);
4393 case NVPTXISD::Suld3DI64Trap:
4394 Opc = NVPTX::SULD_3D_I64_TRAP;
4395 Ops.push_back(TexHandle);
4396 Ops.push_back(N->getOperand(2));
4397 Ops.push_back(N->getOperand(3));
4398 Ops.push_back(N->getOperand(4));
4399 Ops.push_back(Chain);
4401 case NVPTXISD::Suld3DV2I8Trap:
4402 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4403 Ops.push_back(TexHandle);
4404 Ops.push_back(N->getOperand(2));
4405 Ops.push_back(N->getOperand(3));
4406 Ops.push_back(N->getOperand(4));
4407 Ops.push_back(Chain);
4409 case NVPTXISD::Suld3DV2I16Trap:
4410 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4411 Ops.push_back(TexHandle);
4412 Ops.push_back(N->getOperand(2));
4413 Ops.push_back(N->getOperand(3));
4414 Ops.push_back(N->getOperand(4));
4415 Ops.push_back(Chain);
4417 case NVPTXISD::Suld3DV2I32Trap:
4418 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4419 Ops.push_back(TexHandle);
4420 Ops.push_back(N->getOperand(2));
4421 Ops.push_back(N->getOperand(3));
4422 Ops.push_back(N->getOperand(4));
4423 Ops.push_back(Chain);
4425 case NVPTXISD::Suld3DV2I64Trap:
4426 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4427 Ops.push_back(TexHandle);
4428 Ops.push_back(N->getOperand(2));
4429 Ops.push_back(N->getOperand(3));
4430 Ops.push_back(N->getOperand(4));
4431 Ops.push_back(Chain);
4433 case NVPTXISD::Suld3DV4I8Trap:
4434 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4435 Ops.push_back(TexHandle);
4436 Ops.push_back(N->getOperand(2));
4437 Ops.push_back(N->getOperand(3));
4438 Ops.push_back(N->getOperand(4));
4439 Ops.push_back(Chain);
4441 case NVPTXISD::Suld3DV4I16Trap:
4442 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4443 Ops.push_back(TexHandle);
4444 Ops.push_back(N->getOperand(2));
4445 Ops.push_back(N->getOperand(3));
4446 Ops.push_back(N->getOperand(4));
4447 Ops.push_back(Chain);
4449 case NVPTXISD::Suld3DV4I32Trap:
4450 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4451 Ops.push_back(TexHandle);
4452 Ops.push_back(N->getOperand(2));
4453 Ops.push_back(N->getOperand(3));
4454 Ops.push_back(N->getOperand(4));
4455 Ops.push_back(Chain);
4457 case NVPTXISD::Suld1DI8Zero:
4458 Opc = NVPTX::SULD_1D_I8_ZERO;
4459 Ops.push_back(TexHandle);
4460 Ops.push_back(N->getOperand(2));
4461 Ops.push_back(Chain);
4463 case NVPTXISD::Suld1DI16Zero:
4464 Opc = NVPTX::SULD_1D_I16_ZERO;
4465 Ops.push_back(TexHandle);
4466 Ops.push_back(N->getOperand(2));
4467 Ops.push_back(Chain);
4469 case NVPTXISD::Suld1DI32Zero:
4470 Opc = NVPTX::SULD_1D_I32_ZERO;
4471 Ops.push_back(TexHandle);
4472 Ops.push_back(N->getOperand(2));
4473 Ops.push_back(Chain);
4475 case NVPTXISD::Suld1DI64Zero:
4476 Opc = NVPTX::SULD_1D_I64_ZERO;
4477 Ops.push_back(TexHandle);
4478 Ops.push_back(N->getOperand(2));
4479 Ops.push_back(Chain);
4481 case NVPTXISD::Suld1DV2I8Zero:
4482 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4483 Ops.push_back(TexHandle);
4484 Ops.push_back(N->getOperand(2));
4485 Ops.push_back(Chain);
4487 case NVPTXISD::Suld1DV2I16Zero:
4488 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4489 Ops.push_back(TexHandle);
4490 Ops.push_back(N->getOperand(2));
4491 Ops.push_back(Chain);
4493 case NVPTXISD::Suld1DV2I32Zero:
4494 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4495 Ops.push_back(TexHandle);
4496 Ops.push_back(N->getOperand(2));
4497 Ops.push_back(Chain);
4499 case NVPTXISD::Suld1DV2I64Zero:
4500 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4501 Ops.push_back(TexHandle);
4502 Ops.push_back(N->getOperand(2));
4503 Ops.push_back(Chain);
4505 case NVPTXISD::Suld1DV4I8Zero:
4506 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4507 Ops.push_back(TexHandle);
4508 Ops.push_back(N->getOperand(2));
4509 Ops.push_back(Chain);
4511 case NVPTXISD::Suld1DV4I16Zero:
4512 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4513 Ops.push_back(TexHandle);
4514 Ops.push_back(N->getOperand(2));
4515 Ops.push_back(Chain);
4517 case NVPTXISD::Suld1DV4I32Zero:
4518 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4519 Ops.push_back(TexHandle);
4520 Ops.push_back(N->getOperand(2));
4521 Ops.push_back(Chain);
4523 case NVPTXISD::Suld1DArrayI8Zero:
4524 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4525 Ops.push_back(TexHandle);
4526 Ops.push_back(N->getOperand(2));
4527 Ops.push_back(N->getOperand(3));
4528 Ops.push_back(Chain);
4530 case NVPTXISD::Suld1DArrayI16Zero:
4531 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4532 Ops.push_back(TexHandle);
4533 Ops.push_back(N->getOperand(2));
4534 Ops.push_back(N->getOperand(3));
4535 Ops.push_back(Chain);
4537 case NVPTXISD::Suld1DArrayI32Zero:
4538 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4539 Ops.push_back(TexHandle);
4540 Ops.push_back(N->getOperand(2));
4541 Ops.push_back(N->getOperand(3));
4542 Ops.push_back(Chain);
4544 case NVPTXISD::Suld1DArrayI64Zero:
4545 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4546 Ops.push_back(TexHandle);
4547 Ops.push_back(N->getOperand(2));
4548 Ops.push_back(N->getOperand(3));
4549 Ops.push_back(Chain);
4551 case NVPTXISD::Suld1DArrayV2I8Zero:
4552 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4553 Ops.push_back(TexHandle);
4554 Ops.push_back(N->getOperand(2));
4555 Ops.push_back(N->getOperand(3));
4556 Ops.push_back(Chain);
4558 case NVPTXISD::Suld1DArrayV2I16Zero:
4559 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4560 Ops.push_back(TexHandle);
4561 Ops.push_back(N->getOperand(2));
4562 Ops.push_back(N->getOperand(3));
4563 Ops.push_back(Chain);
4565 case NVPTXISD::Suld1DArrayV2I32Zero:
4566 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4567 Ops.push_back(TexHandle);
4568 Ops.push_back(N->getOperand(2));
4569 Ops.push_back(N->getOperand(3));
4570 Ops.push_back(Chain);
4572 case NVPTXISD::Suld1DArrayV2I64Zero:
4573 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4574 Ops.push_back(TexHandle);
4575 Ops.push_back(N->getOperand(2));
4576 Ops.push_back(N->getOperand(3));
4577 Ops.push_back(Chain);
4579 case NVPTXISD::Suld1DArrayV4I8Zero:
4580 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4581 Ops.push_back(TexHandle);
4582 Ops.push_back(N->getOperand(2));
4583 Ops.push_back(N->getOperand(3));
4584 Ops.push_back(Chain);
4586 case NVPTXISD::Suld1DArrayV4I16Zero:
4587 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4588 Ops.push_back(TexHandle);
4589 Ops.push_back(N->getOperand(2));
4590 Ops.push_back(N->getOperand(3));
4591 Ops.push_back(Chain);
4593 case NVPTXISD::Suld1DArrayV4I32Zero:
4594 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4595 Ops.push_back(TexHandle);
4596 Ops.push_back(N->getOperand(2));
4597 Ops.push_back(N->getOperand(3));
4598 Ops.push_back(Chain);
4600 case NVPTXISD::Suld2DI8Zero:
4601 Opc = NVPTX::SULD_2D_I8_ZERO;
4602 Ops.push_back(TexHandle);
4603 Ops.push_back(N->getOperand(2));
4604 Ops.push_back(N->getOperand(3));
4605 Ops.push_back(Chain);
4607 case NVPTXISD::Suld2DI16Zero:
4608 Opc = NVPTX::SULD_2D_I16_ZERO;
4609 Ops.push_back(TexHandle);
4610 Ops.push_back(N->getOperand(2));
4611 Ops.push_back(N->getOperand(3));
4612 Ops.push_back(Chain);
4614 case NVPTXISD::Suld2DI32Zero:
4615 Opc = NVPTX::SULD_2D_I32_ZERO;
4616 Ops.push_back(TexHandle);
4617 Ops.push_back(N->getOperand(2));
4618 Ops.push_back(N->getOperand(3));
4619 Ops.push_back(Chain);
4621 case NVPTXISD::Suld2DI64Zero:
4622 Opc = NVPTX::SULD_2D_I64_ZERO;
4623 Ops.push_back(TexHandle);
4624 Ops.push_back(N->getOperand(2));
4625 Ops.push_back(N->getOperand(3));
4626 Ops.push_back(Chain);
4628 case NVPTXISD::Suld2DV2I8Zero:
4629 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4630 Ops.push_back(TexHandle);
4631 Ops.push_back(N->getOperand(2));
4632 Ops.push_back(N->getOperand(3));
4633 Ops.push_back(Chain);
4635 case NVPTXISD::Suld2DV2I16Zero:
4636 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4637 Ops.push_back(TexHandle);
4638 Ops.push_back(N->getOperand(2));
4639 Ops.push_back(N->getOperand(3));
4640 Ops.push_back(Chain);
4642 case NVPTXISD::Suld2DV2I32Zero:
4643 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4644 Ops.push_back(TexHandle);
4645 Ops.push_back(N->getOperand(2));
4646 Ops.push_back(N->getOperand(3));
4647 Ops.push_back(Chain);
4649 case NVPTXISD::Suld2DV2I64Zero:
4650 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4651 Ops.push_back(TexHandle);
4652 Ops.push_back(N->getOperand(2));
4653 Ops.push_back(N->getOperand(3));
4654 Ops.push_back(Chain);
4656 case NVPTXISD::Suld2DV4I8Zero:
4657 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4658 Ops.push_back(TexHandle);
4659 Ops.push_back(N->getOperand(2));
4660 Ops.push_back(N->getOperand(3));
4661 Ops.push_back(Chain);
4663 case NVPTXISD::Suld2DV4I16Zero:
4664 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4665 Ops.push_back(TexHandle);
4666 Ops.push_back(N->getOperand(2));
4667 Ops.push_back(N->getOperand(3));
4668 Ops.push_back(Chain);
4670 case NVPTXISD::Suld2DV4I32Zero:
4671 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4672 Ops.push_back(TexHandle);
4673 Ops.push_back(N->getOperand(2));
4674 Ops.push_back(N->getOperand(3));
4675 Ops.push_back(Chain);
4677 case NVPTXISD::Suld2DArrayI8Zero:
4678 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4679 Ops.push_back(TexHandle);
4680 Ops.push_back(N->getOperand(2));
4681 Ops.push_back(N->getOperand(3));
4682 Ops.push_back(N->getOperand(4));
4683 Ops.push_back(Chain);
4685 case NVPTXISD::Suld2DArrayI16Zero:
4686 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4687 Ops.push_back(TexHandle);
4688 Ops.push_back(N->getOperand(2));
4689 Ops.push_back(N->getOperand(3));
4690 Ops.push_back(N->getOperand(4));
4691 Ops.push_back(Chain);
4693 case NVPTXISD::Suld2DArrayI32Zero:
4694 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4695 Ops.push_back(TexHandle);
4696 Ops.push_back(N->getOperand(2));
4697 Ops.push_back(N->getOperand(3));
4698 Ops.push_back(N->getOperand(4));
4699 Ops.push_back(Chain);
4701 case NVPTXISD::Suld2DArrayI64Zero:
4702 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4703 Ops.push_back(TexHandle);
4704 Ops.push_back(N->getOperand(2));
4705 Ops.push_back(N->getOperand(3));
4706 Ops.push_back(N->getOperand(4));
4707 Ops.push_back(Chain);
4709 case NVPTXISD::Suld2DArrayV2I8Zero:
4710 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4711 Ops.push_back(TexHandle);
4712 Ops.push_back(N->getOperand(2));
4713 Ops.push_back(N->getOperand(3));
4714 Ops.push_back(N->getOperand(4));
4715 Ops.push_back(Chain);
4717 case NVPTXISD::Suld2DArrayV2I16Zero:
4718 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4719 Ops.push_back(TexHandle);
4720 Ops.push_back(N->getOperand(2));
4721 Ops.push_back(N->getOperand(3));
4722 Ops.push_back(N->getOperand(4));
4723 Ops.push_back(Chain);
4725 case NVPTXISD::Suld2DArrayV2I32Zero:
4726 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4727 Ops.push_back(TexHandle);
4728 Ops.push_back(N->getOperand(2));
4729 Ops.push_back(N->getOperand(3));
4730 Ops.push_back(N->getOperand(4));
4731 Ops.push_back(Chain);
4733 case NVPTXISD::Suld2DArrayV2I64Zero:
4734 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4735 Ops.push_back(TexHandle);
4736 Ops.push_back(N->getOperand(2));
4737 Ops.push_back(N->getOperand(3));
4738 Ops.push_back(N->getOperand(4));
4739 Ops.push_back(Chain);
4741 case NVPTXISD::Suld2DArrayV4I8Zero:
4742 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4743 Ops.push_back(TexHandle);
4744 Ops.push_back(N->getOperand(2));
4745 Ops.push_back(N->getOperand(3));
4746 Ops.push_back(N->getOperand(4));
4747 Ops.push_back(Chain);
4749 case NVPTXISD::Suld2DArrayV4I16Zero:
4750 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4751 Ops.push_back(TexHandle);
4752 Ops.push_back(N->getOperand(2));
4753 Ops.push_back(N->getOperand(3));
4754 Ops.push_back(N->getOperand(4));
4755 Ops.push_back(Chain);
4757 case NVPTXISD::Suld2DArrayV4I32Zero:
4758 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4759 Ops.push_back(TexHandle);
4760 Ops.push_back(N->getOperand(2));
4761 Ops.push_back(N->getOperand(3));
4762 Ops.push_back(N->getOperand(4));
4763 Ops.push_back(Chain);
4765 case NVPTXISD::Suld3DI8Zero:
4766 Opc = NVPTX::SULD_3D_I8_ZERO;
4767 Ops.push_back(TexHandle);
4768 Ops.push_back(N->getOperand(2));
4769 Ops.push_back(N->getOperand(3));
4770 Ops.push_back(N->getOperand(4));
4771 Ops.push_back(Chain);
4773 case NVPTXISD::Suld3DI16Zero:
4774 Opc = NVPTX::SULD_3D_I16_ZERO;
4775 Ops.push_back(TexHandle);
4776 Ops.push_back(N->getOperand(2));
4777 Ops.push_back(N->getOperand(3));
4778 Ops.push_back(N->getOperand(4));
4779 Ops.push_back(Chain);
4781 case NVPTXISD::Suld3DI32Zero:
4782 Opc = NVPTX::SULD_3D_I32_ZERO;
4783 Ops.push_back(TexHandle);
4784 Ops.push_back(N->getOperand(2));
4785 Ops.push_back(N->getOperand(3));
4786 Ops.push_back(N->getOperand(4));
4787 Ops.push_back(Chain);
4789 case NVPTXISD::Suld3DI64Zero:
4790 Opc = NVPTX::SULD_3D_I64_ZERO;
4791 Ops.push_back(TexHandle);
4792 Ops.push_back(N->getOperand(2));
4793 Ops.push_back(N->getOperand(3));
4794 Ops.push_back(N->getOperand(4));
4795 Ops.push_back(Chain);
4797 case NVPTXISD::Suld3DV2I8Zero:
4798 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4799 Ops.push_back(TexHandle);
4800 Ops.push_back(N->getOperand(2));
4801 Ops.push_back(N->getOperand(3));
4802 Ops.push_back(N->getOperand(4));
4803 Ops.push_back(Chain);
4805 case NVPTXISD::Suld3DV2I16Zero:
4806 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4807 Ops.push_back(TexHandle);
4808 Ops.push_back(N->getOperand(2));
4809 Ops.push_back(N->getOperand(3));
4810 Ops.push_back(N->getOperand(4));
4811 Ops.push_back(Chain);
4813 case NVPTXISD::Suld3DV2I32Zero:
4814 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4815 Ops.push_back(TexHandle);
4816 Ops.push_back(N->getOperand(2));
4817 Ops.push_back(N->getOperand(3));
4818 Ops.push_back(N->getOperand(4));
4819 Ops.push_back(Chain);
4821 case NVPTXISD::Suld3DV2I64Zero:
4822 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4823 Ops.push_back(TexHandle);
4824 Ops.push_back(N->getOperand(2));
4825 Ops.push_back(N->getOperand(3));
4826 Ops.push_back(N->getOperand(4));
4827 Ops.push_back(Chain);
4829 case NVPTXISD::Suld3DV4I8Zero:
4830 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4831 Ops.push_back(TexHandle);
4832 Ops.push_back(N->getOperand(2));
4833 Ops.push_back(N->getOperand(3));
4834 Ops.push_back(N->getOperand(4));
4835 Ops.push_back(Chain);
4837 case NVPTXISD::Suld3DV4I16Zero:
4838 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4839 Ops.push_back(TexHandle);
4840 Ops.push_back(N->getOperand(2));
4841 Ops.push_back(N->getOperand(3));
4842 Ops.push_back(N->getOperand(4));
4843 Ops.push_back(Chain);
4845 case NVPTXISD::Suld3DV4I32Zero:
4846 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4847 Ops.push_back(TexHandle);
4848 Ops.push_back(N->getOperand(2));
4849 Ops.push_back(N->getOperand(3));
4850 Ops.push_back(N->getOperand(4));
4851 Ops.push_back(Chain);
4854 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops));
4859 /// SelectBFE - Look for instruction sequences that can be made more efficient
4860 /// by using the 'bfe' (bit-field extract) PTX instruction
4861 bool NVPTXDAGToDAGISel::tryBFE(SDNode *N) {
4863 SDValue LHS = N->getOperand(0);
4864 SDValue RHS = N->getOperand(1);
4868 bool IsSigned = false;
4870 if (N->getOpcode() == ISD::AND) {
4871 // Canonicalize the operands
4872 // We want 'and %val, %mask'
4873 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4874 std::swap(LHS, RHS);
4877 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
4879 // We need a constant mask on the RHS of the AND
4883 // Extract the mask bits
4884 uint64_t MaskVal = Mask->getZExtValue();
4885 if (!isMask_64(MaskVal)) {
4886 // We *could* handle shifted masks here, but doing so would require an
4887 // 'and' operation to fix up the low-order bits so we would trade
4888 // shr+and for bfe+and, which has the same throughput
4892 // How many bits are in our mask?
4893 uint64_t NumBits = countTrailingOnes(MaskVal);
4894 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4896 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
4897 // We have a 'srl/and' pair, extract the effective start bit and length
4898 Val = LHS.getNode()->getOperand(0);
4899 Start = LHS.getNode()->getOperand(1);
4900 ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
4902 uint64_t StartVal = StartConst->getZExtValue();
4903 // How many "good" bits do we have left? "good" is defined here as bits
4904 // that exist in the original value, not shifted in.
4905 uint64_t GoodBits = Start.getValueType().getSizeInBits() - StartVal;
4906 if (NumBits > GoodBits) {
4907 // Do not handle the case where bits have been shifted in. In theory
4908 // we could handle this, but the cost is likely higher than just
4909 // emitting the srl/and pair.
4912 Start = CurDAG->getTargetConstant(StartVal, DL, MVT::i32);
4914 // Do not handle the case where the shift amount (can be zero if no srl
4915 // was found) is not constant. We could handle this case, but it would
4916 // require run-time logic that would be more expensive than just
4917 // emitting the srl/and pair.
4921 // Do not handle the case where the LHS of the and is not a shift. While
4922 // it would be trivial to handle this case, it would just transform
4923 // 'and' -> 'bfe', but 'and' has higher-throughput.
4926 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
4927 if (LHS->getOpcode() == ISD::AND) {
4928 ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
4930 // Shift amount must be constant
4934 uint64_t ShiftAmt = ShiftCnst->getZExtValue();
4936 SDValue AndLHS = LHS->getOperand(0);
4937 SDValue AndRHS = LHS->getOperand(1);
4939 // Canonicalize the AND to have the mask on the RHS
4940 if (isa<ConstantSDNode>(AndLHS)) {
4941 std::swap(AndLHS, AndRHS);
4944 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
4946 // Mask must be constant
4950 uint64_t MaskVal = MaskCnst->getZExtValue();
4953 if (isMask_64(MaskVal)) {
4955 // The number of bits in the result bitfield will be the number of
4956 // trailing ones (the AND) minus the number of bits we shift off
4957 NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
4958 } else if (isShiftedMask_64(MaskVal)) {
4959 NumZeros = countTrailingZeros(MaskVal);
4960 unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros);
4961 // The number of bits in the result bitfield will be the number of
4962 // trailing zeros plus the number of set bits in the mask minus the
4963 // number of bits we shift off
4964 NumBits = NumZeros + NumOnes - ShiftAmt;
4966 // This is not a mask we can handle
4970 if (ShiftAmt < NumZeros) {
4971 // Handling this case would require extra logic that would make this
4972 // transformation non-profitable
4977 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32);
4978 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4979 } else if (LHS->getOpcode() == ISD::SHL) {
4980 // Here, we have a pattern like:
4982 // (sra (shl val, NN), MM)
4984 // (srl (shl val, NN), MM)
4986 // If MM >= NN, we can efficiently optimize this with bfe
4987 Val = LHS->getOperand(0);
4989 SDValue ShlRHS = LHS->getOperand(1);
4990 ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
4992 // Shift amount must be constant
4995 uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
4997 SDValue ShrRHS = RHS;
4998 ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
5000 // Shift amount must be constant
5003 uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
5005 // To avoid extra codegen and be profitable, we need Outer >= Inner
5006 if (OuterShiftAmt < InnerShiftAmt) {
5010 // If the outer shift is more than the type size, we have no bitfield to
5011 // extract (since we also check that the inner shift is <= the outer shift
5012 // then this also implies that the inner shift is < the type size)
5013 if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
5018 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, DL, MVT::i32);
5020 CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
5021 OuterShiftAmt, DL, MVT::i32);
5023 if (N->getOpcode() == ISD::SRA) {
5024 // If we have a arithmetic right shift, we need to use the signed bfe
5039 // For the BFE operations we form here from "and" and "srl", always use the
5040 // unsigned variants.
5041 if (Val.getValueType() == MVT::i32) {
5043 Opc = NVPTX::BFE_S32rii;
5045 Opc = NVPTX::BFE_U32rii;
5047 } else if (Val.getValueType() == MVT::i64) {
5049 Opc = NVPTX::BFE_S64rii;
5051 Opc = NVPTX::BFE_U64rii;
5054 // We cannot handle this type
5062 ReplaceNode(N, CurDAG->getMachineNode(Opc, DL, N->getVTList(), Ops));
5066 // SelectDirectAddr - Match a direct address for DAG.
5067 // A direct address could be a globaladdress or externalsymbol.
5068 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
5069 // Return true if TGA or ES.
5070 if (N.getOpcode() == ISD::TargetGlobalAddress ||
5071 N.getOpcode() == ISD::TargetExternalSymbol) {
5075 if (N.getOpcode() == NVPTXISD::Wrapper) {
5076 Address = N.getOperand(0);
5079 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
5080 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
5081 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
5082 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
5083 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
5089 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
5090 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
5091 if (Addr.getOpcode() == ISD::ADD) {
5092 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5093 SDValue base = Addr.getOperand(0);
5094 if (SelectDirectAddr(base, Base)) {
5095 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
5105 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
5106 SDValue &Base, SDValue &Offset) {
5107 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
5111 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
5112 SDValue &Base, SDValue &Offset) {
5113 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
5117 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
5118 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
5119 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
5120 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5121 Offset = CurDAG->getTargetConstant(0, SDLoc(OpNode), mvt);
5124 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
5125 Addr.getOpcode() == ISD::TargetGlobalAddress)
5126 return false; // direct calls.
5128 if (Addr.getOpcode() == ISD::ADD) {
5129 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
5132 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5133 if (FrameIndexSDNode *FIN =
5134 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
5135 // Constant offset from frame ref.
5136 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5138 Base = Addr.getOperand(0);
5139 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
5148 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
5149 SDValue &Base, SDValue &Offset) {
5150 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5154 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
5155 SDValue &Base, SDValue &Offset) {
5156 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5159 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
5160 unsigned int spN) const {
5161 const Value *Src = nullptr;
5162 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
5163 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5165 Src = mN->getMemOperand()->getValue();
5169 if (auto *PT = dyn_cast<PointerType>(Src->getType()))
5170 return (PT->getAddressSpace() == spN);
5174 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
5175 /// inline asm expressions.
5176 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
5177 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
5179 switch (ConstraintID) {
5182 case InlineAsm::Constraint_m: // memory
5183 if (SelectDirectAddr(Op, Op0)) {
5184 OutOps.push_back(Op0);
5185 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
5188 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
5189 OutOps.push_back(Op0);
5190 OutOps.push_back(Op1);
5198 /// GetConvertOpcode - Returns the CVT_ instruction opcode that implements a
5199 /// conversion from \p SrcTy to \p DestTy.
5200 unsigned NVPTXDAGToDAGISel::GetConvertOpcode(MVT DestTy, MVT SrcTy,
5202 switch (SrcTy.SimpleTy) {
5204 llvm_unreachable("Unhandled source type");
5206 switch (DestTy.SimpleTy) {
5208 llvm_unreachable("Unhandled dest type");
5210 return IsSigned ? NVPTX::CVT_s16_s8 : NVPTX::CVT_u16_u8;
5212 return IsSigned ? NVPTX::CVT_s32_s8 : NVPTX::CVT_u32_u8;
5214 return IsSigned ? NVPTX::CVT_s64_s8 : NVPTX::CVT_u64_u8;
5217 switch (DestTy.SimpleTy) {
5219 llvm_unreachable("Unhandled dest type");
5221 return IsSigned ? NVPTX::CVT_s8_s16 : NVPTX::CVT_u8_u16;
5223 return IsSigned ? NVPTX::CVT_s32_s16 : NVPTX::CVT_u32_u16;
5225 return IsSigned ? NVPTX::CVT_s64_s16 : NVPTX::CVT_u64_u16;
5228 switch (DestTy.SimpleTy) {
5230 llvm_unreachable("Unhandled dest type");
5232 return IsSigned ? NVPTX::CVT_s8_s32 : NVPTX::CVT_u8_u32;
5234 return IsSigned ? NVPTX::CVT_s16_s32 : NVPTX::CVT_u16_u32;
5236 return IsSigned ? NVPTX::CVT_s64_s32 : NVPTX::CVT_u64_u32;
5239 switch (DestTy.SimpleTy) {
5241 llvm_unreachable("Unhandled dest type");
5243 return IsSigned ? NVPTX::CVT_s8_s64 : NVPTX::CVT_u8_u64;
5245 return IsSigned ? NVPTX::CVT_s16_s64 : NVPTX::CVT_u16_u64;
5247 return IsSigned ? NVPTX::CVT_s32_s64 : NVPTX::CVT_u32_u64;