2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelLowering.h"
16 #include "NVPTXTargetMachine.h"
17 #include "NVPTXTargetObjectFile.h"
18 #include "NVPTXUtilities.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/CallSite.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/MC/MCSectionELF.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 #define DEBUG_TYPE "nvptx-lower"
45 static unsigned int uniqueCallSite = 0;
47 static cl::opt<bool> sched4reg(
49 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
51 static cl::opt<unsigned>
52 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
53 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
54 " 1: do it 2: do it aggressively"),
57 static bool IsPTXVectorType(MVT VT) {
58 switch (VT.SimpleTy) {
77 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
78 /// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
79 /// into their primitive components.
80 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
82 /// LowerCall, and LowerReturn.
83 static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
84 SmallVectorImpl<EVT> &ValueVTs,
85 SmallVectorImpl<uint64_t> *Offsets = nullptr,
86 uint64_t StartingOffset = 0) {
87 SmallVector<EVT, 16> TempVTs;
88 SmallVector<uint64_t, 16> TempOffsets;
90 ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
91 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
93 uint64_t Off = TempOffsets[i];
95 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
96 ValueVTs.push_back(VT.getVectorElementType());
98 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
101 ValueVTs.push_back(VT);
103 Offsets->push_back(Off);
108 // NVPTXTargetLowering Constructor.
109 NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
110 : TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM),
111 nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
113 // always lower memset, memcpy, and memmove intrinsics to load/store
114 // instructions, rather
115 // then generating calls to memset, mempcy or memmove.
116 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
117 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
118 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
120 setBooleanContents(ZeroOrNegativeOneBooleanContent);
121 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
123 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
124 // condition branches.
125 setJumpIsExpensive(true);
127 // By default, use the Source scheduling
129 setSchedulingPreference(Sched::RegPressure);
131 setSchedulingPreference(Sched::Source);
133 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
134 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
135 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
136 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
137 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
138 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
140 // Operations not directly supported by NVPTX.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
143 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
144 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
145 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
146 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
147 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
148 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
149 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
150 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
151 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
152 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
153 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
154 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
155 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
156 // For others we will expand to a SHL/SRA pair.
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
163 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
164 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
165 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
166 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
167 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
168 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
170 if (nvptxSubtarget.hasROT64()) {
171 setOperationAction(ISD::ROTL, MVT::i64, Legal);
172 setOperationAction(ISD::ROTR, MVT::i64, Legal);
174 setOperationAction(ISD::ROTL, MVT::i64, Expand);
175 setOperationAction(ISD::ROTR, MVT::i64, Expand);
177 if (nvptxSubtarget.hasROT32()) {
178 setOperationAction(ISD::ROTL, MVT::i32, Legal);
179 setOperationAction(ISD::ROTR, MVT::i32, Legal);
181 setOperationAction(ISD::ROTL, MVT::i32, Expand);
182 setOperationAction(ISD::ROTR, MVT::i32, Expand);
185 setOperationAction(ISD::ROTL, MVT::i16, Expand);
186 setOperationAction(ISD::ROTR, MVT::i16, Expand);
187 setOperationAction(ISD::ROTL, MVT::i8, Expand);
188 setOperationAction(ISD::ROTR, MVT::i8, Expand);
189 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
190 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
191 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
193 // Indirect branch is not supported.
194 // This also disables Jump Table creation.
195 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
196 setOperationAction(ISD::BRIND, MVT::Other, Expand);
198 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
199 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
201 // We want to legalize constant related memmove and memcopy
203 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
205 // Turn FP extload into load/fextend
206 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
207 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
208 // Turn FP truncstore into trunc + store.
209 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
210 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
211 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
213 // PTX does not support load / store predicate registers
214 setOperationAction(ISD::LOAD, MVT::i1, Custom);
215 setOperationAction(ISD::STORE, MVT::i1, Custom);
217 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
218 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
219 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
220 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
221 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
222 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
224 // This is legal in NVPTX
225 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
226 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
228 // TRAP can be lowered to PTX trap
229 setOperationAction(ISD::TRAP, MVT::Other, Legal);
231 setOperationAction(ISD::ADDC, MVT::i64, Expand);
232 setOperationAction(ISD::ADDE, MVT::i64, Expand);
234 // Register custom handling for vector loads/stores
235 for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE;
237 MVT VT = (MVT::SimpleValueType) i;
238 if (IsPTXVectorType(VT)) {
239 setOperationAction(ISD::LOAD, VT, Custom);
240 setOperationAction(ISD::STORE, VT, Custom);
241 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
245 // Custom handling for i8 intrinsics
246 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
248 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
249 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
250 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
251 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
252 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
253 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
254 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
255 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
256 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
257 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
258 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
259 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
260 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
261 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
262 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
264 // We have some custom DAG combine patterns for these nodes
265 setTargetDAGCombine(ISD::ADD);
266 setTargetDAGCombine(ISD::AND);
267 setTargetDAGCombine(ISD::FADD);
268 setTargetDAGCombine(ISD::MUL);
269 setTargetDAGCombine(ISD::SHL);
271 // Now deduce the information based on the above mentioned
273 computeRegisterProperties();
276 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
281 return "NVPTXISD::CALL";
282 case NVPTXISD::RET_FLAG:
283 return "NVPTXISD::RET_FLAG";
284 case NVPTXISD::Wrapper:
285 return "NVPTXISD::Wrapper";
286 case NVPTXISD::DeclareParam:
287 return "NVPTXISD::DeclareParam";
288 case NVPTXISD::DeclareScalarParam:
289 return "NVPTXISD::DeclareScalarParam";
290 case NVPTXISD::DeclareRet:
291 return "NVPTXISD::DeclareRet";
292 case NVPTXISD::DeclareRetParam:
293 return "NVPTXISD::DeclareRetParam";
294 case NVPTXISD::PrintCall:
295 return "NVPTXISD::PrintCall";
296 case NVPTXISD::LoadParam:
297 return "NVPTXISD::LoadParam";
298 case NVPTXISD::LoadParamV2:
299 return "NVPTXISD::LoadParamV2";
300 case NVPTXISD::LoadParamV4:
301 return "NVPTXISD::LoadParamV4";
302 case NVPTXISD::StoreParam:
303 return "NVPTXISD::StoreParam";
304 case NVPTXISD::StoreParamV2:
305 return "NVPTXISD::StoreParamV2";
306 case NVPTXISD::StoreParamV4:
307 return "NVPTXISD::StoreParamV4";
308 case NVPTXISD::StoreParamS32:
309 return "NVPTXISD::StoreParamS32";
310 case NVPTXISD::StoreParamU32:
311 return "NVPTXISD::StoreParamU32";
312 case NVPTXISD::CallArgBegin:
313 return "NVPTXISD::CallArgBegin";
314 case NVPTXISD::CallArg:
315 return "NVPTXISD::CallArg";
316 case NVPTXISD::LastCallArg:
317 return "NVPTXISD::LastCallArg";
318 case NVPTXISD::CallArgEnd:
319 return "NVPTXISD::CallArgEnd";
320 case NVPTXISD::CallVoid:
321 return "NVPTXISD::CallVoid";
322 case NVPTXISD::CallVal:
323 return "NVPTXISD::CallVal";
324 case NVPTXISD::CallSymbol:
325 return "NVPTXISD::CallSymbol";
326 case NVPTXISD::Prototype:
327 return "NVPTXISD::Prototype";
328 case NVPTXISD::MoveParam:
329 return "NVPTXISD::MoveParam";
330 case NVPTXISD::StoreRetval:
331 return "NVPTXISD::StoreRetval";
332 case NVPTXISD::StoreRetvalV2:
333 return "NVPTXISD::StoreRetvalV2";
334 case NVPTXISD::StoreRetvalV4:
335 return "NVPTXISD::StoreRetvalV4";
336 case NVPTXISD::PseudoUseParam:
337 return "NVPTXISD::PseudoUseParam";
338 case NVPTXISD::RETURN:
339 return "NVPTXISD::RETURN";
340 case NVPTXISD::CallSeqBegin:
341 return "NVPTXISD::CallSeqBegin";
342 case NVPTXISD::CallSeqEnd:
343 return "NVPTXISD::CallSeqEnd";
344 case NVPTXISD::CallPrototype:
345 return "NVPTXISD::CallPrototype";
346 case NVPTXISD::LoadV2:
347 return "NVPTXISD::LoadV2";
348 case NVPTXISD::LoadV4:
349 return "NVPTXISD::LoadV4";
350 case NVPTXISD::LDGV2:
351 return "NVPTXISD::LDGV2";
352 case NVPTXISD::LDGV4:
353 return "NVPTXISD::LDGV4";
354 case NVPTXISD::LDUV2:
355 return "NVPTXISD::LDUV2";
356 case NVPTXISD::LDUV4:
357 return "NVPTXISD::LDUV4";
358 case NVPTXISD::StoreV2:
359 return "NVPTXISD::StoreV2";
360 case NVPTXISD::StoreV4:
361 return "NVPTXISD::StoreV4";
362 case NVPTXISD::FUN_SHFL_CLAMP:
363 return "NVPTXISD::FUN_SHFL_CLAMP";
364 case NVPTXISD::FUN_SHFR_CLAMP:
365 return "NVPTXISD::FUN_SHFR_CLAMP";
367 return "NVPTXISD::IMAD";
368 case NVPTXISD::MUL_WIDE_SIGNED:
369 return "NVPTXISD::MUL_WIDE_SIGNED";
370 case NVPTXISD::MUL_WIDE_UNSIGNED:
371 return "NVPTXISD::MUL_WIDE_UNSIGNED";
372 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
373 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
374 case NVPTXISD::Tex1DFloatFloatLevel:
375 return "NVPTXISD::Tex1DFloatFloatLevel";
376 case NVPTXISD::Tex1DFloatFloatGrad:
377 return "NVPTXISD::Tex1DFloatFloatGrad";
378 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
379 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
380 case NVPTXISD::Tex1DS32FloatLevel:
381 return "NVPTXISD::Tex1DS32FloatLevel";
382 case NVPTXISD::Tex1DS32FloatGrad:
383 return "NVPTXISD::Tex1DS32FloatGrad";
384 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
385 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
386 case NVPTXISD::Tex1DU32FloatLevel:
387 return "NVPTXISD::Tex1DU32FloatLevel";
388 case NVPTXISD::Tex1DU32FloatGrad:
389 return "NVPTXISD::Tex1DU32FloatGrad";
390 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
391 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
392 case NVPTXISD::Tex1DArrayFloatFloatLevel:
393 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
394 case NVPTXISD::Tex1DArrayFloatFloatGrad:
395 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
396 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
397 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
398 case NVPTXISD::Tex1DArrayS32FloatLevel:
399 return "NVPTXISD::Tex1DArrayS32FloatLevel";
400 case NVPTXISD::Tex1DArrayS32FloatGrad:
401 return "NVPTXISD::Tex1DArrayS32FloatGrad";
402 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
403 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
404 case NVPTXISD::Tex1DArrayU32FloatLevel:
405 return "NVPTXISD::Tex1DArrayU32FloatLevel";
406 case NVPTXISD::Tex1DArrayU32FloatGrad:
407 return "NVPTXISD::Tex1DArrayU32FloatGrad";
408 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
409 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
410 case NVPTXISD::Tex2DFloatFloatLevel:
411 return "NVPTXISD::Tex2DFloatFloatLevel";
412 case NVPTXISD::Tex2DFloatFloatGrad:
413 return "NVPTXISD::Tex2DFloatFloatGrad";
414 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
415 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
416 case NVPTXISD::Tex2DS32FloatLevel:
417 return "NVPTXISD::Tex2DS32FloatLevel";
418 case NVPTXISD::Tex2DS32FloatGrad:
419 return "NVPTXISD::Tex2DS32FloatGrad";
420 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
421 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
422 case NVPTXISD::Tex2DU32FloatLevel:
423 return "NVPTXISD::Tex2DU32FloatLevel";
424 case NVPTXISD::Tex2DU32FloatGrad:
425 return "NVPTXISD::Tex2DU32FloatGrad";
426 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
427 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
428 case NVPTXISD::Tex2DArrayFloatFloatLevel:
429 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
430 case NVPTXISD::Tex2DArrayFloatFloatGrad:
431 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
432 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
433 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
434 case NVPTXISD::Tex2DArrayS32FloatLevel:
435 return "NVPTXISD::Tex2DArrayS32FloatLevel";
436 case NVPTXISD::Tex2DArrayS32FloatGrad:
437 return "NVPTXISD::Tex2DArrayS32FloatGrad";
438 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
439 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
440 case NVPTXISD::Tex2DArrayU32FloatLevel:
441 return "NVPTXISD::Tex2DArrayU32FloatLevel";
442 case NVPTXISD::Tex2DArrayU32FloatGrad:
443 return "NVPTXISD::Tex2DArrayU32FloatGrad";
444 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
445 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
446 case NVPTXISD::Tex3DFloatFloatLevel:
447 return "NVPTXISD::Tex3DFloatFloatLevel";
448 case NVPTXISD::Tex3DFloatFloatGrad:
449 return "NVPTXISD::Tex3DFloatFloatGrad";
450 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
451 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
452 case NVPTXISD::Tex3DS32FloatLevel:
453 return "NVPTXISD::Tex3DS32FloatLevel";
454 case NVPTXISD::Tex3DS32FloatGrad:
455 return "NVPTXISD::Tex3DS32FloatGrad";
456 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
457 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
458 case NVPTXISD::Tex3DU32FloatLevel:
459 return "NVPTXISD::Tex3DU32FloatLevel";
460 case NVPTXISD::Tex3DU32FloatGrad:
461 return "NVPTXISD::Tex3DU32FloatGrad";
462 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
463 case NVPTXISD::TexCubeFloatFloatLevel:
464 return "NVPTXISD::TexCubeFloatFloatLevel";
465 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
466 case NVPTXISD::TexCubeS32FloatLevel:
467 return "NVPTXISD::TexCubeS32FloatLevel";
468 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
469 case NVPTXISD::TexCubeU32FloatLevel:
470 return "NVPTXISD::TexCubeU32FloatLevel";
471 case NVPTXISD::TexCubeArrayFloatFloat:
472 return "NVPTXISD::TexCubeArrayFloatFloat";
473 case NVPTXISD::TexCubeArrayFloatFloatLevel:
474 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
475 case NVPTXISD::TexCubeArrayS32Float:
476 return "NVPTXISD::TexCubeArrayS32Float";
477 case NVPTXISD::TexCubeArrayS32FloatLevel:
478 return "NVPTXISD::TexCubeArrayS32FloatLevel";
479 case NVPTXISD::TexCubeArrayU32Float:
480 return "NVPTXISD::TexCubeArrayU32Float";
481 case NVPTXISD::TexCubeArrayU32FloatLevel:
482 return "NVPTXISD::TexCubeArrayU32FloatLevel";
483 case NVPTXISD::Tld4R2DFloatFloat:
484 return "NVPTXISD::Tld4R2DFloatFloat";
485 case NVPTXISD::Tld4G2DFloatFloat:
486 return "NVPTXISD::Tld4G2DFloatFloat";
487 case NVPTXISD::Tld4B2DFloatFloat:
488 return "NVPTXISD::Tld4B2DFloatFloat";
489 case NVPTXISD::Tld4A2DFloatFloat:
490 return "NVPTXISD::Tld4A2DFloatFloat";
491 case NVPTXISD::Tld4R2DS64Float:
492 return "NVPTXISD::Tld4R2DS64Float";
493 case NVPTXISD::Tld4G2DS64Float:
494 return "NVPTXISD::Tld4G2DS64Float";
495 case NVPTXISD::Tld4B2DS64Float:
496 return "NVPTXISD::Tld4B2DS64Float";
497 case NVPTXISD::Tld4A2DS64Float:
498 return "NVPTXISD::Tld4A2DS64Float";
499 case NVPTXISD::Tld4R2DU64Float:
500 return "NVPTXISD::Tld4R2DU64Float";
501 case NVPTXISD::Tld4G2DU64Float:
502 return "NVPTXISD::Tld4G2DU64Float";
503 case NVPTXISD::Tld4B2DU64Float:
504 return "NVPTXISD::Tld4B2DU64Float";
505 case NVPTXISD::Tld4A2DU64Float:
506 return "NVPTXISD::Tld4A2DU64Float";
508 case NVPTXISD::TexUnified1DFloatS32:
509 return "NVPTXISD::TexUnified1DFloatS32";
510 case NVPTXISD::TexUnified1DFloatFloat:
511 return "NVPTXISD::TexUnified1DFloatFloat";
512 case NVPTXISD::TexUnified1DFloatFloatLevel:
513 return "NVPTXISD::TexUnified1DFloatFloatLevel";
514 case NVPTXISD::TexUnified1DFloatFloatGrad:
515 return "NVPTXISD::TexUnified1DFloatFloatGrad";
516 case NVPTXISD::TexUnified1DS32S32:
517 return "NVPTXISD::TexUnified1DS32S32";
518 case NVPTXISD::TexUnified1DS32Float:
519 return "NVPTXISD::TexUnified1DS32Float";
520 case NVPTXISD::TexUnified1DS32FloatLevel:
521 return "NVPTXISD::TexUnified1DS32FloatLevel";
522 case NVPTXISD::TexUnified1DS32FloatGrad:
523 return "NVPTXISD::TexUnified1DS32FloatGrad";
524 case NVPTXISD::TexUnified1DU32S32:
525 return "NVPTXISD::TexUnified1DU32S32";
526 case NVPTXISD::TexUnified1DU32Float:
527 return "NVPTXISD::TexUnified1DU32Float";
528 case NVPTXISD::TexUnified1DU32FloatLevel:
529 return "NVPTXISD::TexUnified1DU32FloatLevel";
530 case NVPTXISD::TexUnified1DU32FloatGrad:
531 return "NVPTXISD::TexUnified1DU32FloatGrad";
532 case NVPTXISD::TexUnified1DArrayFloatS32:
533 return "NVPTXISD::TexUnified1DArrayFloatS32";
534 case NVPTXISD::TexUnified1DArrayFloatFloat:
535 return "NVPTXISD::TexUnified1DArrayFloatFloat";
536 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
537 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
538 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
539 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
540 case NVPTXISD::TexUnified1DArrayS32S32:
541 return "NVPTXISD::TexUnified1DArrayS32S32";
542 case NVPTXISD::TexUnified1DArrayS32Float:
543 return "NVPTXISD::TexUnified1DArrayS32Float";
544 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
545 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
546 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
547 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
548 case NVPTXISD::TexUnified1DArrayU32S32:
549 return "NVPTXISD::TexUnified1DArrayU32S32";
550 case NVPTXISD::TexUnified1DArrayU32Float:
551 return "NVPTXISD::TexUnified1DArrayU32Float";
552 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
553 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
554 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
555 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
556 case NVPTXISD::TexUnified2DFloatS32:
557 return "NVPTXISD::TexUnified2DFloatS32";
558 case NVPTXISD::TexUnified2DFloatFloat:
559 return "NVPTXISD::TexUnified2DFloatFloat";
560 case NVPTXISD::TexUnified2DFloatFloatLevel:
561 return "NVPTXISD::TexUnified2DFloatFloatLevel";
562 case NVPTXISD::TexUnified2DFloatFloatGrad:
563 return "NVPTXISD::TexUnified2DFloatFloatGrad";
564 case NVPTXISD::TexUnified2DS32S32:
565 return "NVPTXISD::TexUnified2DS32S32";
566 case NVPTXISD::TexUnified2DS32Float:
567 return "NVPTXISD::TexUnified2DS32Float";
568 case NVPTXISD::TexUnified2DS32FloatLevel:
569 return "NVPTXISD::TexUnified2DS32FloatLevel";
570 case NVPTXISD::TexUnified2DS32FloatGrad:
571 return "NVPTXISD::TexUnified2DS32FloatGrad";
572 case NVPTXISD::TexUnified2DU32S32:
573 return "NVPTXISD::TexUnified2DU32S32";
574 case NVPTXISD::TexUnified2DU32Float:
575 return "NVPTXISD::TexUnified2DU32Float";
576 case NVPTXISD::TexUnified2DU32FloatLevel:
577 return "NVPTXISD::TexUnified2DU32FloatLevel";
578 case NVPTXISD::TexUnified2DU32FloatGrad:
579 return "NVPTXISD::TexUnified2DU32FloatGrad";
580 case NVPTXISD::TexUnified2DArrayFloatS32:
581 return "NVPTXISD::TexUnified2DArrayFloatS32";
582 case NVPTXISD::TexUnified2DArrayFloatFloat:
583 return "NVPTXISD::TexUnified2DArrayFloatFloat";
584 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
585 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
586 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
587 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
588 case NVPTXISD::TexUnified2DArrayS32S32:
589 return "NVPTXISD::TexUnified2DArrayS32S32";
590 case NVPTXISD::TexUnified2DArrayS32Float:
591 return "NVPTXISD::TexUnified2DArrayS32Float";
592 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
593 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
594 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
595 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
596 case NVPTXISD::TexUnified2DArrayU32S32:
597 return "NVPTXISD::TexUnified2DArrayU32S32";
598 case NVPTXISD::TexUnified2DArrayU32Float:
599 return "NVPTXISD::TexUnified2DArrayU32Float";
600 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
601 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
602 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
603 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
604 case NVPTXISD::TexUnified3DFloatS32:
605 return "NVPTXISD::TexUnified3DFloatS32";
606 case NVPTXISD::TexUnified3DFloatFloat:
607 return "NVPTXISD::TexUnified3DFloatFloat";
608 case NVPTXISD::TexUnified3DFloatFloatLevel:
609 return "NVPTXISD::TexUnified3DFloatFloatLevel";
610 case NVPTXISD::TexUnified3DFloatFloatGrad:
611 return "NVPTXISD::TexUnified3DFloatFloatGrad";
612 case NVPTXISD::TexUnified3DS32S32:
613 return "NVPTXISD::TexUnified3DS32S32";
614 case NVPTXISD::TexUnified3DS32Float:
615 return "NVPTXISD::TexUnified3DS32Float";
616 case NVPTXISD::TexUnified3DS32FloatLevel:
617 return "NVPTXISD::TexUnified3DS32FloatLevel";
618 case NVPTXISD::TexUnified3DS32FloatGrad:
619 return "NVPTXISD::TexUnified3DS32FloatGrad";
620 case NVPTXISD::TexUnified3DU32S32:
621 return "NVPTXISD::TexUnified3DU32S32";
622 case NVPTXISD::TexUnified3DU32Float:
623 return "NVPTXISD::TexUnified3DU32Float";
624 case NVPTXISD::TexUnified3DU32FloatLevel:
625 return "NVPTXISD::TexUnified3DU32FloatLevel";
626 case NVPTXISD::TexUnified3DU32FloatGrad:
627 return "NVPTXISD::TexUnified3DU32FloatGrad";
628 case NVPTXISD::TexUnifiedCubeFloatFloat:
629 return "NVPTXISD::TexUnifiedCubeFloatFloat";
630 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
631 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
632 case NVPTXISD::TexUnifiedCubeS32Float:
633 return "NVPTXISD::TexUnifiedCubeS32Float";
634 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
635 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
636 case NVPTXISD::TexUnifiedCubeU32Float:
637 return "NVPTXISD::TexUnifiedCubeU32Float";
638 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
639 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
640 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
641 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
642 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
643 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
644 case NVPTXISD::TexUnifiedCubeArrayS32Float:
645 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
646 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
647 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
648 case NVPTXISD::TexUnifiedCubeArrayU32Float:
649 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
650 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
651 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
652 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
653 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
654 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
655 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
656 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
657 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
658 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
659 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
660 case NVPTXISD::Tld4UnifiedR2DS64Float:
661 return "NVPTXISD::Tld4UnifiedR2DS64Float";
662 case NVPTXISD::Tld4UnifiedG2DS64Float:
663 return "NVPTXISD::Tld4UnifiedG2DS64Float";
664 case NVPTXISD::Tld4UnifiedB2DS64Float:
665 return "NVPTXISD::Tld4UnifiedB2DS64Float";
666 case NVPTXISD::Tld4UnifiedA2DS64Float:
667 return "NVPTXISD::Tld4UnifiedA2DS64Float";
668 case NVPTXISD::Tld4UnifiedR2DU64Float:
669 return "NVPTXISD::Tld4UnifiedR2DU64Float";
670 case NVPTXISD::Tld4UnifiedG2DU64Float:
671 return "NVPTXISD::Tld4UnifiedG2DU64Float";
672 case NVPTXISD::Tld4UnifiedB2DU64Float:
673 return "NVPTXISD::Tld4UnifiedB2DU64Float";
674 case NVPTXISD::Tld4UnifiedA2DU64Float:
675 return "NVPTXISD::Tld4UnifiedA2DU64Float";
677 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
678 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
679 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
680 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
681 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
682 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
683 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
684 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
685 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
686 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
687 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
689 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
690 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
691 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
692 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
693 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
694 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
695 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
696 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
697 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
698 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
699 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
701 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
702 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
703 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
704 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
705 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
706 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
707 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
708 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
709 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
710 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
711 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
713 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
714 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
715 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
716 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
717 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
718 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
719 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
720 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
721 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
722 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
723 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
725 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
726 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
727 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
728 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
729 case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
730 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
731 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
732 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
733 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
734 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
735 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
737 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
738 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
739 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
740 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
741 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
742 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
743 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
744 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
745 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
746 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
747 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
749 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
750 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
751 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
752 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
753 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
754 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
755 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
756 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
757 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
758 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
759 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
761 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
762 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
763 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
764 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
765 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
766 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
767 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
768 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
769 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
770 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
771 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
773 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
774 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
775 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
776 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
777 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
778 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
779 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
780 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
781 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
782 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
783 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
785 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
786 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
787 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
788 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
789 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
790 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
791 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
792 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
793 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
794 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
795 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
797 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
798 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
799 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
800 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
801 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
802 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
803 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
804 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
805 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
806 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
807 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
809 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
810 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
811 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
812 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
813 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
814 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
815 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
816 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
817 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
818 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
819 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
821 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
822 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
823 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
824 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
825 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
826 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
827 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
828 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
829 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
830 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
831 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
833 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
834 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
835 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
836 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
837 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
838 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
839 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
840 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
841 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
842 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
843 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
845 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
846 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
847 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
848 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
849 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
850 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
851 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
852 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
853 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
854 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
855 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
859 TargetLoweringBase::LegalizeTypeAction
860 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
861 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
862 return TypeSplitVector;
864 return TargetLoweringBase::getPreferredVectorAction(VT);
868 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
870 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
871 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
872 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
876 NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
877 const SmallVectorImpl<ISD::OutputArg> &Outs,
878 unsigned retAlignment,
879 const ImmutableCallSite *CS) const {
881 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
882 assert(isABI && "Non-ABI compilation is not supported");
887 O << "prototype_" << uniqueCallSite << " : .callprototype ";
889 if (retTy->getTypeID() == Type::VoidTyID) {
893 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
895 if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
896 size = ITy->getBitWidth();
900 assert(retTy->isFloatingPointTy() &&
901 "Floating point type expected here");
902 size = retTy->getPrimitiveSizeInBits();
905 O << ".param .b" << size << " _";
906 } else if (isa<PointerType>(retTy)) {
907 O << ".param .b" << getPointerTy().getSizeInBits() << " _";
909 if((retTy->getTypeID() == Type::StructTyID) ||
910 isa<VectorType>(retTy)) {
911 O << ".param .align "
914 << getDataLayout()->getTypeAllocSize(retTy) << "]";
916 assert(false && "Unknown return type");
924 MVT thePointerTy = getPointerTy();
927 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
928 Type *Ty = Args[i].Ty;
934 if (Outs[OIdx].Flags.isByVal() == false) {
935 if (Ty->isAggregateType() || Ty->isVectorTy()) {
937 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
938 const DataLayout *TD = getDataLayout();
939 // +1 because index 0 is reserved for return type alignment
940 if (!llvm::getAlign(*CallI, i + 1, align))
941 align = TD->getABITypeAlignment(Ty);
942 unsigned sz = TD->getTypeAllocSize(Ty);
943 O << ".param .align " << align << " .b8 ";
945 O << "[" << sz << "]";
946 // update the index for Outs
947 SmallVector<EVT, 16> vtparts;
948 ComputeValueVTs(*this, Ty, vtparts);
949 if (unsigned len = vtparts.size())
953 // i8 types in IR will be i16 types in SDAG
954 assert((getValueType(Ty) == Outs[OIdx].VT ||
955 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
956 "type mismatch between callee prototype and arguments");
959 if (isa<IntegerType>(Ty)) {
960 sz = cast<IntegerType>(Ty)->getBitWidth();
963 } else if (isa<PointerType>(Ty))
964 sz = thePointerTy.getSizeInBits();
966 sz = Ty->getPrimitiveSizeInBits();
967 O << ".param .b" << sz << " ";
971 const PointerType *PTy = dyn_cast<PointerType>(Ty);
972 assert(PTy && "Param with byval attribute should be a pointer type");
973 Type *ETy = PTy->getElementType();
975 unsigned align = Outs[OIdx].Flags.getByValAlign();
976 unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
977 O << ".param .align " << align << " .b8 ";
979 O << "[" << sz << "]";
986 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
987 const ImmutableCallSite *CS,
989 unsigned Idx) const {
990 const DataLayout *TD = getDataLayout();
992 const Value *DirectCallee = CS->getCalledFunction();
995 // We don't have a direct function symbol, but that may be because of
996 // constant cast instructions in the call.
997 const Instruction *CalleeI = CS->getInstruction();
998 assert(CalleeI && "Call target is not a function or derived value?");
1000 // With bitcast'd call targets, the instruction will be the call
1001 if (isa<CallInst>(CalleeI)) {
1002 // Check if we have call alignment metadata
1003 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1006 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1007 // Ignore any bitcast instructions
1008 while(isa<ConstantExpr>(CalleeV)) {
1009 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1012 // Look through the bitcast
1013 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1016 // We have now looked past all of the bitcasts. Do we finally have a
1018 if (isa<Function>(CalleeV))
1019 DirectCallee = CalleeV;
1023 // Check for function alignment information if we found that the
1024 // ultimate target is a Function
1026 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
1029 // Call is indirect or alignment information is not available, fall back to
1030 // the ABI type alignment
1031 return TD->getABITypeAlignment(Ty);
1034 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1035 SmallVectorImpl<SDValue> &InVals) const {
1036 SelectionDAG &DAG = CLI.DAG;
1038 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1039 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1040 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1041 SDValue Chain = CLI.Chain;
1042 SDValue Callee = CLI.Callee;
1043 bool &isTailCall = CLI.IsTailCall;
1044 ArgListTy &Args = CLI.getArgs();
1045 Type *retTy = CLI.RetTy;
1046 ImmutableCallSite *CS = CLI.CS;
1048 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
1049 assert(isABI && "Non-ABI compilation is not supported");
1052 const DataLayout *TD = getDataLayout();
1053 MachineFunction &MF = DAG.getMachineFunction();
1054 const Function *F = MF.getFunction();
1056 SDValue tempChain = Chain;
1058 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
1060 SDValue InFlag = Chain.getValue(1);
1062 unsigned paramCount = 0;
1063 // Args.size() and Outs.size() need not match.
1064 // Outs.size() will be larger
1065 // * if there is an aggregate argument with multiple fields (each field
1066 // showing up separately in Outs)
1067 // * if there is a vector argument with more than typical vector-length
1068 // elements (generally if more than 4) where each vector element is
1069 // individually present in Outs.
1070 // So a different index should be used for indexing into Outs/OutVals.
1071 // See similar issue in LowerFormalArguments.
1073 // Declare the .params or .reg need to pass values
1075 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1076 EVT VT = Outs[OIdx].VT;
1077 Type *Ty = Args[i].Ty;
1079 if (Outs[OIdx].Flags.isByVal() == false) {
1080 if (Ty->isAggregateType()) {
1082 SmallVector<EVT, 16> vtparts;
1083 SmallVector<uint64_t, 16> Offsets;
1084 ComputePTXValueVTs(*this, Ty, vtparts, &Offsets, 0);
1086 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1087 // declare .param .align <align> .b8 .param<n>[<size>];
1088 unsigned sz = TD->getTypeAllocSize(Ty);
1089 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1090 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
1091 DAG.getConstant(paramCount, MVT::i32),
1092 DAG.getConstant(sz, MVT::i32), InFlag };
1093 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1095 InFlag = Chain.getValue(1);
1096 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1097 EVT elemtype = vtparts[j];
1098 unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
1099 if (elemtype.isInteger() && (sz < 8))
1101 SDValue StVal = OutVals[OIdx];
1102 if (elemtype.getSizeInBits() < 16) {
1103 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1105 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1106 SDValue CopyParamOps[] = { Chain,
1107 DAG.getConstant(paramCount, MVT::i32),
1108 DAG.getConstant(Offsets[j], MVT::i32),
1110 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1111 CopyParamVTs, CopyParamOps,
1112 elemtype, MachinePointerInfo(),
1114 InFlag = Chain.getValue(1);
1117 if (vtparts.size() > 0)
1122 if (Ty->isVectorTy()) {
1123 EVT ObjectVT = getValueType(Ty);
1124 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1125 // declare .param .align <align> .b8 .param<n>[<size>];
1126 unsigned sz = TD->getTypeAllocSize(Ty);
1127 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1128 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
1129 DAG.getConstant(paramCount, MVT::i32),
1130 DAG.getConstant(sz, MVT::i32), InFlag };
1131 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1133 InFlag = Chain.getValue(1);
1134 unsigned NumElts = ObjectVT.getVectorNumElements();
1135 EVT EltVT = ObjectVT.getVectorElementType();
1137 bool NeedExtend = false;
1138 if (EltVT.getSizeInBits() < 16) {
1145 SDValue Elt = OutVals[OIdx++];
1147 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
1149 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1150 SDValue CopyParamOps[] = { Chain,
1151 DAG.getConstant(paramCount, MVT::i32),
1152 DAG.getConstant(0, MVT::i32), Elt,
1154 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1155 CopyParamVTs, CopyParamOps,
1156 MemVT, MachinePointerInfo());
1157 InFlag = Chain.getValue(1);
1158 } else if (NumElts == 2) {
1159 SDValue Elt0 = OutVals[OIdx++];
1160 SDValue Elt1 = OutVals[OIdx++];
1162 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
1163 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
1166 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1167 SDValue CopyParamOps[] = { Chain,
1168 DAG.getConstant(paramCount, MVT::i32),
1169 DAG.getConstant(0, MVT::i32), Elt0, Elt1,
1171 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
1172 CopyParamVTs, CopyParamOps,
1173 MemVT, MachinePointerInfo());
1174 InFlag = Chain.getValue(1);
1176 unsigned curOffset = 0;
1178 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1180 // vector will be expanded to a power of 2 elements, so we know we can
1181 // always round up to the next multiple of 4 when creating the vector
1183 // e.g. 4 elem => 1 st.v4
1184 // 6 elem => 2 st.v4
1185 // 8 elem => 2 st.v4
1186 // 11 elem => 3 st.v4
1187 unsigned VecSize = 4;
1188 if (EltVT.getSizeInBits() == 64)
1191 // This is potentially only part of a vector, so assume all elements
1192 // are packed together.
1193 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
1195 for (unsigned i = 0; i < NumElts; i += VecSize) {
1198 SmallVector<SDValue, 8> Ops;
1199 Ops.push_back(Chain);
1200 Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
1201 Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
1203 unsigned Opc = NVPTXISD::StoreParamV2;
1205 StoreVal = OutVals[OIdx++];
1207 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1208 Ops.push_back(StoreVal);
1210 if (i + 1 < NumElts) {
1211 StoreVal = OutVals[OIdx++];
1214 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1216 StoreVal = DAG.getUNDEF(EltVT);
1218 Ops.push_back(StoreVal);
1221 Opc = NVPTXISD::StoreParamV4;
1222 if (i + 2 < NumElts) {
1223 StoreVal = OutVals[OIdx++];
1226 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1228 StoreVal = DAG.getUNDEF(EltVT);
1230 Ops.push_back(StoreVal);
1232 if (i + 3 < NumElts) {
1233 StoreVal = OutVals[OIdx++];
1236 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1238 StoreVal = DAG.getUNDEF(EltVT);
1240 Ops.push_back(StoreVal);
1243 Ops.push_back(InFlag);
1245 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1246 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1247 MemVT, MachinePointerInfo());
1248 InFlag = Chain.getValue(1);
1249 curOffset += PerStoreOffset;
1257 // for ABI, declare .param .b<size> .param<n>;
1258 unsigned sz = VT.getSizeInBits();
1259 bool needExtend = false;
1260 if (VT.isInteger()) {
1266 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1267 SDValue DeclareParamOps[] = { Chain,
1268 DAG.getConstant(paramCount, MVT::i32),
1269 DAG.getConstant(sz, MVT::i32),
1270 DAG.getConstant(0, MVT::i32), InFlag };
1271 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1273 InFlag = Chain.getValue(1);
1274 SDValue OutV = OutVals[OIdx];
1276 // zext/sext i1 to i16
1277 unsigned opc = ISD::ZERO_EXTEND;
1278 if (Outs[OIdx].Flags.isSExt())
1279 opc = ISD::SIGN_EXTEND;
1280 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
1282 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1283 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
1284 DAG.getConstant(0, MVT::i32), OutV, InFlag };
1286 unsigned opcode = NVPTXISD::StoreParam;
1287 if (Outs[OIdx].Flags.isZExt())
1288 opcode = NVPTXISD::StoreParamU32;
1289 else if (Outs[OIdx].Flags.isSExt())
1290 opcode = NVPTXISD::StoreParamS32;
1291 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
1292 VT, MachinePointerInfo());
1294 InFlag = Chain.getValue(1);
1299 SmallVector<EVT, 16> vtparts;
1300 SmallVector<uint64_t, 16> Offsets;
1301 const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
1302 assert(PTy && "Type of a byval parameter should be pointer");
1303 ComputePTXValueVTs(*this, PTy->getElementType(), vtparts, &Offsets, 0);
1305 // declare .param .align <align> .b8 .param<n>[<size>];
1306 unsigned sz = Outs[OIdx].Flags.getByValSize();
1307 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1308 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1309 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1310 // so we don't need to worry about natural alignment or not.
1311 // See TargetLowering::LowerCallTo().
1312 SDValue DeclareParamOps[] = {
1313 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
1314 DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
1317 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1319 InFlag = Chain.getValue(1);
1320 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1321 EVT elemtype = vtparts[j];
1322 int curOffset = Offsets[j];
1323 unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1325 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
1326 DAG.getConstant(curOffset, getPointerTy()));
1327 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1328 MachinePointerInfo(), false, false, false,
1330 if (elemtype.getSizeInBits() < 16) {
1331 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1333 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1334 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
1335 DAG.getConstant(curOffset, MVT::i32), theVal,
1337 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1338 CopyParamOps, elemtype,
1339 MachinePointerInfo());
1341 InFlag = Chain.getValue(1);
1346 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1347 unsigned retAlignment = 0;
1350 if (Ins.size() > 0) {
1351 SmallVector<EVT, 16> resvtparts;
1352 ComputeValueVTs(*this, retTy, resvtparts);
1355 // .param .align 16 .b8 retval0[<size-in-bytes>], or
1356 // .param .b<size-in-bits> retval0
1357 unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
1358 if (retTy->isSingleValueType()) {
1359 // Scalar needs to be at least 32bit wide
1362 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1363 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
1364 DAG.getConstant(resultsz, MVT::i32),
1365 DAG.getConstant(0, MVT::i32), InFlag };
1366 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1368 InFlag = Chain.getValue(1);
1370 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1371 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1372 SDValue DeclareRetOps[] = { Chain,
1373 DAG.getConstant(retAlignment, MVT::i32),
1374 DAG.getConstant(resultsz / 8, MVT::i32),
1375 DAG.getConstant(0, MVT::i32), InFlag };
1376 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1378 InFlag = Chain.getValue(1);
1383 // This is indirect function call case : PTX requires a prototype of the
1385 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1386 // to be emitted, and the label has to used as the last arg of call
1388 // The prototype is embedded in a string and put as the operand for a
1389 // CallPrototype SDNode which will print out to the value of the string.
1390 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1391 std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
1392 const char *ProtoStr =
1393 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1394 SDValue ProtoOps[] = {
1395 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1397 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1398 InFlag = Chain.getValue(1);
1400 // Op to just print "call"
1401 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1402 SDValue PrintCallOps[] = {
1403 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
1405 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
1406 dl, PrintCallVTs, PrintCallOps);
1407 InFlag = Chain.getValue(1);
1409 // Ops to print out the function name
1410 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1411 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1412 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1413 InFlag = Chain.getValue(1);
1415 // Ops to print out the param list
1416 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1417 SDValue CallArgBeginOps[] = { Chain, InFlag };
1418 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1420 InFlag = Chain.getValue(1);
1422 for (unsigned i = 0, e = paramCount; i != e; ++i) {
1425 opcode = NVPTXISD::LastCallArg;
1427 opcode = NVPTXISD::CallArg;
1428 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1429 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
1430 DAG.getConstant(i, MVT::i32), InFlag };
1431 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1432 InFlag = Chain.getValue(1);
1434 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1435 SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
1437 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1438 InFlag = Chain.getValue(1);
1441 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1442 SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
1444 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1445 InFlag = Chain.getValue(1);
1448 // Generate loads from param memory/moves from registers for result
1449 if (Ins.size() > 0) {
1450 if (retTy && retTy->isVectorTy()) {
1451 EVT ObjectVT = getValueType(retTy);
1452 unsigned NumElts = ObjectVT.getVectorNumElements();
1453 EVT EltVT = ObjectVT.getVectorElementType();
1454 assert(nvTM->getTargetLowering()->getNumRegisters(F->getContext(),
1455 ObjectVT) == NumElts &&
1456 "Vector was not scalarized");
1457 unsigned sz = EltVT.getSizeInBits();
1458 bool needTruncate = sz < 8 ? true : false;
1461 // Just a simple load
1462 SmallVector<EVT, 4> LoadRetVTs;
1463 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1464 // If loading i1/i8 result, generate
1468 LoadRetVTs.push_back(MVT::i16);
1470 LoadRetVTs.push_back(EltVT);
1471 LoadRetVTs.push_back(MVT::Other);
1472 LoadRetVTs.push_back(MVT::Glue);
1473 SmallVector<SDValue, 4> LoadRetOps;
1474 LoadRetOps.push_back(Chain);
1475 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1476 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1477 LoadRetOps.push_back(InFlag);
1478 SDValue retval = DAG.getMemIntrinsicNode(
1479 NVPTXISD::LoadParam, dl,
1480 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1481 Chain = retval.getValue(1);
1482 InFlag = retval.getValue(2);
1483 SDValue Ret0 = retval;
1485 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1486 InVals.push_back(Ret0);
1487 } else if (NumElts == 2) {
1489 SmallVector<EVT, 4> LoadRetVTs;
1490 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1491 // If loading i1/i8 result, generate
1495 LoadRetVTs.push_back(MVT::i16);
1496 LoadRetVTs.push_back(MVT::i16);
1498 LoadRetVTs.push_back(EltVT);
1499 LoadRetVTs.push_back(EltVT);
1501 LoadRetVTs.push_back(MVT::Other);
1502 LoadRetVTs.push_back(MVT::Glue);
1503 SmallVector<SDValue, 4> LoadRetOps;
1504 LoadRetOps.push_back(Chain);
1505 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1506 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1507 LoadRetOps.push_back(InFlag);
1508 SDValue retval = DAG.getMemIntrinsicNode(
1509 NVPTXISD::LoadParamV2, dl,
1510 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1511 Chain = retval.getValue(2);
1512 InFlag = retval.getValue(3);
1513 SDValue Ret0 = retval.getValue(0);
1514 SDValue Ret1 = retval.getValue(1);
1516 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1517 InVals.push_back(Ret0);
1518 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1519 InVals.push_back(Ret1);
1521 InVals.push_back(Ret0);
1522 InVals.push_back(Ret1);
1525 // Split into N LoadV4
1527 unsigned VecSize = 4;
1528 unsigned Opc = NVPTXISD::LoadParamV4;
1529 if (EltVT.getSizeInBits() == 64) {
1531 Opc = NVPTXISD::LoadParamV2;
1533 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1534 for (unsigned i = 0; i < NumElts; i += VecSize) {
1535 SmallVector<EVT, 8> LoadRetVTs;
1536 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1537 // If loading i1/i8 result, generate
1541 for (unsigned j = 0; j < VecSize; ++j)
1542 LoadRetVTs.push_back(MVT::i16);
1544 for (unsigned j = 0; j < VecSize; ++j)
1545 LoadRetVTs.push_back(EltVT);
1547 LoadRetVTs.push_back(MVT::Other);
1548 LoadRetVTs.push_back(MVT::Glue);
1549 SmallVector<SDValue, 4> LoadRetOps;
1550 LoadRetOps.push_back(Chain);
1551 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1552 LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
1553 LoadRetOps.push_back(InFlag);
1554 SDValue retval = DAG.getMemIntrinsicNode(
1555 Opc, dl, DAG.getVTList(LoadRetVTs),
1556 LoadRetOps, EltVT, MachinePointerInfo());
1558 Chain = retval.getValue(2);
1559 InFlag = retval.getValue(3);
1561 Chain = retval.getValue(4);
1562 InFlag = retval.getValue(5);
1565 for (unsigned j = 0; j < VecSize; ++j) {
1566 if (i + j >= NumElts)
1568 SDValue Elt = retval.getValue(j);
1570 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1571 InVals.push_back(Elt);
1573 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1577 SmallVector<EVT, 16> VTs;
1578 SmallVector<uint64_t, 16> Offsets;
1579 ComputePTXValueVTs(*this, retTy, VTs, &Offsets, 0);
1580 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1581 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
1582 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1583 unsigned sz = VTs[i].getSizeInBits();
1584 unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1585 bool needTruncate = sz < 8 ? true : false;
1586 if (VTs[i].isInteger() && (sz < 8))
1589 SmallVector<EVT, 4> LoadRetVTs;
1590 EVT TheLoadType = VTs[i];
1591 if (retTy->isIntegerTy() &&
1592 TD->getTypeAllocSizeInBits(retTy) < 32) {
1593 // This is for integer types only, and specifically not for
1595 LoadRetVTs.push_back(MVT::i32);
1596 TheLoadType = MVT::i32;
1597 } else if (sz < 16) {
1598 // If loading i1/i8 result, generate
1600 // trunc i16 to i1/i8
1601 LoadRetVTs.push_back(MVT::i16);
1603 LoadRetVTs.push_back(Ins[i].VT);
1604 LoadRetVTs.push_back(MVT::Other);
1605 LoadRetVTs.push_back(MVT::Glue);
1607 SmallVector<SDValue, 4> LoadRetOps;
1608 LoadRetOps.push_back(Chain);
1609 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1610 LoadRetOps.push_back(DAG.getConstant(Offsets[i], MVT::i32));
1611 LoadRetOps.push_back(InFlag);
1612 SDValue retval = DAG.getMemIntrinsicNode(
1613 NVPTXISD::LoadParam, dl,
1614 DAG.getVTList(LoadRetVTs), LoadRetOps,
1615 TheLoadType, MachinePointerInfo(), AlignI);
1616 Chain = retval.getValue(1);
1617 InFlag = retval.getValue(2);
1618 SDValue Ret0 = retval.getValue(0);
1620 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1621 InVals.push_back(Ret0);
1626 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
1627 DAG.getIntPtrConstant(uniqueCallSite + 1, true),
1631 // set isTailCall to false for now, until we figure out how to express
1632 // tail call optimization in PTX
1637 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1638 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1639 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1641 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1642 SDNode *Node = Op.getNode();
1644 SmallVector<SDValue, 8> Ops;
1645 unsigned NumOperands = Node->getNumOperands();
1646 for (unsigned i = 0; i < NumOperands; ++i) {
1647 SDValue SubOp = Node->getOperand(i);
1648 EVT VVT = SubOp.getNode()->getValueType(0);
1649 EVT EltVT = VVT.getVectorElementType();
1650 unsigned NumSubElem = VVT.getVectorNumElements();
1651 for (unsigned j = 0; j < NumSubElem; ++j) {
1652 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1653 DAG.getIntPtrConstant(j)));
1656 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
1659 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1660 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1662 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1664 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1665 SelectionDAG &DAG) const {
1666 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1667 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1669 EVT VT = Op.getValueType();
1670 unsigned VTBits = VT.getSizeInBits();
1672 SDValue ShOpLo = Op.getOperand(0);
1673 SDValue ShOpHi = Op.getOperand(1);
1674 SDValue ShAmt = Op.getOperand(2);
1675 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1677 if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
1679 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1680 // {dHi, dLo} = {aHi, aLo} >> Amt
1682 // dLo = shf.r.clamp aLo, aHi, Amt
1684 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1685 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1688 SDValue Ops[2] = { Lo, Hi };
1689 return DAG.getMergeValues(Ops, dl);
1693 // {dHi, dLo} = {aHi, aLo} >> Amt
1694 // - if (Amt>=size) then
1695 // dLo = aHi >> (Amt-size)
1696 // dHi = aHi >> Amt (this is either all 0 or all 1)
1698 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1701 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1702 DAG.getConstant(VTBits, MVT::i32), ShAmt);
1703 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1704 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1705 DAG.getConstant(VTBits, MVT::i32));
1706 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1707 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1708 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1710 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1711 DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
1712 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1713 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1715 SDValue Ops[2] = { Lo, Hi };
1716 return DAG.getMergeValues(Ops, dl);
1720 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1721 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1723 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1725 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1726 SelectionDAG &DAG) const {
1727 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1728 assert(Op.getOpcode() == ISD::SHL_PARTS);
1730 EVT VT = Op.getValueType();
1731 unsigned VTBits = VT.getSizeInBits();
1733 SDValue ShOpLo = Op.getOperand(0);
1734 SDValue ShOpHi = Op.getOperand(1);
1735 SDValue ShAmt = Op.getOperand(2);
1737 if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
1739 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1740 // {dHi, dLo} = {aHi, aLo} << Amt
1741 // dHi = shf.l.clamp aLo, aHi, Amt
1744 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1746 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1748 SDValue Ops[2] = { Lo, Hi };
1749 return DAG.getMergeValues(Ops, dl);
1753 // {dHi, dLo} = {aHi, aLo} << Amt
1754 // - if (Amt>=size) then
1755 // dLo = aLo << Amt (all 0)
1756 // dLo = aLo << (Amt-size)
1759 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1761 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1762 DAG.getConstant(VTBits, MVT::i32), ShAmt);
1763 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1764 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1765 DAG.getConstant(VTBits, MVT::i32));
1766 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1767 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1768 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1770 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1771 DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
1772 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1773 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1775 SDValue Ops[2] = { Lo, Hi };
1776 return DAG.getMergeValues(Ops, dl);
1781 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1782 switch (Op.getOpcode()) {
1783 case ISD::RETURNADDR:
1785 case ISD::FRAMEADDR:
1787 case ISD::GlobalAddress:
1788 return LowerGlobalAddress(Op, DAG);
1789 case ISD::INTRINSIC_W_CHAIN:
1791 case ISD::BUILD_VECTOR:
1792 case ISD::EXTRACT_SUBVECTOR:
1794 case ISD::CONCAT_VECTORS:
1795 return LowerCONCAT_VECTORS(Op, DAG);
1797 return LowerSTORE(Op, DAG);
1799 return LowerLOAD(Op, DAG);
1800 case ISD::SHL_PARTS:
1801 return LowerShiftLeftParts(Op, DAG);
1802 case ISD::SRA_PARTS:
1803 case ISD::SRL_PARTS:
1804 return LowerShiftRightParts(Op, DAG);
1806 llvm_unreachable("Custom lowering not defined for operation");
1810 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1811 if (Op.getValueType() == MVT::i1)
1812 return LowerLOADi1(Op, DAG);
1819 // v1 = ld i8* addr (-> i16)
1820 // v = trunc i16 to i1
1821 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
1822 SDNode *Node = Op.getNode();
1823 LoadSDNode *LD = cast<LoadSDNode>(Node);
1825 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
1826 assert(Node->getValueType(0) == MVT::i1 &&
1827 "Custom lowering for i1 load only");
1829 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
1830 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1831 LD->isInvariant(), LD->getAlignment());
1832 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1833 // The legalizer (the caller) is expecting two values from the legalized
1834 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1835 // in LegalizeDAG.cpp which also uses MergeValues.
1836 SDValue Ops[] = { result, LD->getChain() };
1837 return DAG.getMergeValues(Ops, dl);
1840 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1841 EVT ValVT = Op.getOperand(1).getValueType();
1842 if (ValVT == MVT::i1)
1843 return LowerSTOREi1(Op, DAG);
1844 else if (ValVT.isVector())
1845 return LowerSTOREVector(Op, DAG);
1851 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1852 SDNode *N = Op.getNode();
1853 SDValue Val = N->getOperand(1);
1855 EVT ValVT = Val.getValueType();
1857 if (ValVT.isVector()) {
1858 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1859 // legal. We can (and should) split that into 2 stores of <2 x double> here
1860 // but I'm leaving that as a TODO for now.
1861 if (!ValVT.isSimple())
1863 switch (ValVT.getSimpleVT().SimpleTy) {
1876 // This is a "native" vector type
1880 MemSDNode *MemSD = cast<MemSDNode>(N);
1881 const DataLayout *TD = getDataLayout();
1883 unsigned Align = MemSD->getAlignment();
1884 unsigned PrefAlign =
1885 TD->getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
1886 if (Align < PrefAlign) {
1887 // This store is not sufficiently aligned, so bail out and let this vector
1888 // store be scalarized. Note that we may still be able to emit smaller
1889 // vector stores. For example, if we are storing a <4 x float> with an
1890 // alignment of 8, this check will fail but the legalizer will try again
1891 // with 2 x <2 x float>, which will succeed with an alignment of 8.
1895 unsigned Opcode = 0;
1896 EVT EltVT = ValVT.getVectorElementType();
1897 unsigned NumElts = ValVT.getVectorNumElements();
1899 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1900 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
1901 // stored type to i16 and propagate the "real" type as the memory type.
1902 bool NeedExt = false;
1903 if (EltVT.getSizeInBits() < 16)
1910 Opcode = NVPTXISD::StoreV2;
1913 Opcode = NVPTXISD::StoreV4;
1918 SmallVector<SDValue, 8> Ops;
1920 // First is the chain
1921 Ops.push_back(N->getOperand(0));
1923 // Then the split values
1924 for (unsigned i = 0; i < NumElts; ++i) {
1925 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1926 DAG.getIntPtrConstant(i));
1928 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
1929 Ops.push_back(ExtVal);
1932 // Then any remaining arguments
1933 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1934 Ops.push_back(N->getOperand(i));
1937 SDValue NewSt = DAG.getMemIntrinsicNode(
1938 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
1939 MemSD->getMemoryVT(), MemSD->getMemOperand());
1941 //return DCI.CombineTo(N, NewSt, true);
1950 // v1 = zxt v to i16
1952 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
1953 SDNode *Node = Op.getNode();
1955 StoreSDNode *ST = cast<StoreSDNode>(Node);
1956 SDValue Tmp1 = ST->getChain();
1957 SDValue Tmp2 = ST->getBasePtr();
1958 SDValue Tmp3 = ST->getValue();
1959 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
1960 unsigned Alignment = ST->getAlignment();
1961 bool isVolatile = ST->isVolatile();
1962 bool isNonTemporal = ST->isNonTemporal();
1963 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
1964 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1965 ST->getPointerInfo(), MVT::i8, isNonTemporal,
1966 isVolatile, Alignment);
1970 SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
1971 int idx, EVT v) const {
1972 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
1973 std::stringstream suffix;
1975 *name += suffix.str();
1976 return DAG.getTargetExternalSymbol(name->c_str(), v);
1980 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
1981 std::string ParamSym;
1982 raw_string_ostream ParamStr(ParamSym);
1984 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
1987 std::string *SavedStr =
1988 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
1989 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
1992 SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
1993 return getExtSymb(DAG, ".HLPPARAM", idx);
1996 // Check to see if the kernel argument is image*_t or sampler_t
1998 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
1999 static const char *const specialTypes[] = { "struct._image2d_t",
2000 "struct._image3d_t",
2001 "struct._sampler_t" };
2003 const Type *Ty = arg->getType();
2004 const PointerType *PTy = dyn_cast<PointerType>(Ty);
2012 const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
2013 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
2015 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
2016 if (TypeName == specialTypes[i])
2022 SDValue NVPTXTargetLowering::LowerFormalArguments(
2023 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2024 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2025 SmallVectorImpl<SDValue> &InVals) const {
2026 MachineFunction &MF = DAG.getMachineFunction();
2027 const DataLayout *TD = getDataLayout();
2029 const Function *F = MF.getFunction();
2030 const AttributeSet &PAL = F->getAttributes();
2031 const TargetLowering *TLI = DAG.getTarget().getTargetLowering();
2033 SDValue Root = DAG.getRoot();
2034 std::vector<SDValue> OutChains;
2036 bool isKernel = llvm::isKernelFunction(*F);
2037 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
2038 assert(isABI && "Non-ABI compilation is not supported");
2042 std::vector<Type *> argTypes;
2043 std::vector<const Argument *> theArgs;
2044 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
2046 theArgs.push_back(I);
2047 argTypes.push_back(I->getType());
2049 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2050 // Ins.size() will be larger
2051 // * if there is an aggregate argument with multiple fields (each field
2052 // showing up separately in Ins)
2053 // * if there is a vector argument with more than typical vector-length
2054 // elements (generally if more than 4) where each vector element is
2055 // individually present in Ins.
2056 // So a different index should be used for indexing into Ins.
2057 // See similar issue in LowerCall.
2058 unsigned InsIdx = 0;
2061 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2062 Type *Ty = argTypes[i];
2064 // If the kernel argument is image*_t or sampler_t, convert it to
2065 // a i32 constant holding the parameter position. This can later
2066 // matched in the AsmPrinter to output the correct mangled name.
2067 if (isImageOrSamplerVal(
2069 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2071 assert(isKernel && "Only kernels can have image/sampler params");
2072 InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
2076 if (theArgs[i]->use_empty()) {
2078 if (Ty->isAggregateType()) {
2079 SmallVector<EVT, 16> vtparts;
2081 ComputePTXValueVTs(*this, Ty, vtparts);
2082 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2083 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2085 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2088 if (vtparts.size() > 0)
2092 if (Ty->isVectorTy()) {
2093 EVT ObjectVT = getValueType(Ty);
2094 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2095 for (unsigned parti = 0; parti < NumRegs; ++parti) {
2096 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2103 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2107 // In the following cases, assign a node order of "idx+1"
2108 // to newly created nodes. The SDNodes for params have to
2109 // appear in the same order as their order of appearance
2110 // in the original function. "idx+1" holds that order.
2111 if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
2112 if (Ty->isAggregateType()) {
2113 SmallVector<EVT, 16> vtparts;
2114 SmallVector<uint64_t, 16> offsets;
2116 // NOTE: Here, we lose the ability to issue vector loads for vectors
2117 // that are a part of a struct. This should be investigated in the
2119 ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
2120 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2121 bool aggregateIsPacked = false;
2122 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
2123 aggregateIsPacked = STy->isPacked();
2125 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2126 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2128 EVT partVT = vtparts[parti];
2129 Value *srcValue = Constant::getNullValue(
2130 PointerType::get(partVT.getTypeForEVT(F->getContext()),
2131 llvm::ADDRESS_SPACE_PARAM));
2133 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
2134 DAG.getConstant(offsets[parti], getPointerTy()));
2135 unsigned partAlign =
2136 aggregateIsPacked ? 1
2137 : TD->getABITypeAlignment(
2138 partVT.getTypeForEVT(F->getContext()));
2140 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
2141 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2142 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2143 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2144 MachinePointerInfo(srcValue), partVT, false,
2147 p = DAG.getLoad(partVT, dl, Root, srcAddr,
2148 MachinePointerInfo(srcValue), false, false, false,
2152 p.getNode()->setIROrder(idx + 1);
2153 InVals.push_back(p);
2156 if (vtparts.size() > 0)
2160 if (Ty->isVectorTy()) {
2161 EVT ObjectVT = getValueType(Ty);
2162 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2163 unsigned NumElts = ObjectVT.getVectorNumElements();
2164 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
2165 "Vector was not scalarized");
2167 EVT EltVT = ObjectVT.getVectorElementType();
2172 // We only have one element, so just directly load it
2173 Value *SrcValue = Constant::getNullValue(PointerType::get(
2174 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2175 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
2176 DAG.getConstant(Ofst, getPointerTy()));
2177 SDValue P = DAG.getLoad(
2178 EltVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2180 TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
2182 P.getNode()->setIROrder(idx + 1);
2184 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2185 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
2186 InVals.push_back(P);
2187 Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
2189 } else if (NumElts == 2) {
2191 // f32,f32 = load ...
2192 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
2193 Value *SrcValue = Constant::getNullValue(PointerType::get(
2194 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2195 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
2196 DAG.getConstant(Ofst, getPointerTy()));
2197 SDValue P = DAG.getLoad(
2198 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2200 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2202 P.getNode()->setIROrder(idx + 1);
2204 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2205 DAG.getIntPtrConstant(0));
2206 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2207 DAG.getIntPtrConstant(1));
2209 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
2210 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
2211 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
2214 InVals.push_back(Elt0);
2215 InVals.push_back(Elt1);
2216 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2220 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
2222 // vector will be expanded to a power of 2 elements, so we know we can
2223 // always round up to the next multiple of 4 when creating the vector
2225 // e.g. 4 elem => 1 ld.v4
2226 // 6 elem => 2 ld.v4
2227 // 8 elem => 2 ld.v4
2228 // 11 elem => 3 ld.v4
2229 unsigned VecSize = 4;
2230 if (EltVT.getSizeInBits() == 64) {
2233 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2234 for (unsigned i = 0; i < NumElts; i += VecSize) {
2235 Value *SrcValue = Constant::getNullValue(
2236 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
2237 llvm::ADDRESS_SPACE_PARAM));
2239 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
2240 DAG.getConstant(Ofst, getPointerTy()));
2241 SDValue P = DAG.getLoad(
2242 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2244 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2246 P.getNode()->setIROrder(idx + 1);
2248 for (unsigned j = 0; j < VecSize; ++j) {
2249 if (i + j >= NumElts)
2251 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2252 DAG.getIntPtrConstant(j));
2253 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2254 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
2255 InVals.push_back(Elt);
2257 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2267 EVT ObjectVT = getValueType(Ty);
2268 // If ABI, load from the param symbol
2269 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2270 Value *srcValue = Constant::getNullValue(PointerType::get(
2271 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2273 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2274 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2275 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2276 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
2277 MachinePointerInfo(srcValue), ObjectVT, false, false,
2278 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2280 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
2281 MachinePointerInfo(srcValue), false, false, false,
2282 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2285 p.getNode()->setIROrder(idx + 1);
2286 InVals.push_back(p);
2290 // Param has ByVal attribute
2291 // Return MoveParam(param symbol).
2292 // Ideally, the param symbol can be returned directly,
2293 // but when SDNode builder decides to use it in a CopyToReg(),
2294 // machine instruction fails because TargetExternalSymbol
2295 // (not lowered) is target dependent, and CopyToReg assumes
2296 // the source is lowered.
2297 EVT ObjectVT = getValueType(Ty);
2298 assert(ObjectVT == Ins[InsIdx].VT &&
2299 "Ins type did not match function type");
2300 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
2301 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2303 p.getNode()->setIROrder(idx + 1);
2305 InVals.push_back(p);
2307 SDValue p2 = DAG.getNode(
2308 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
2309 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
2310 InVals.push_back(p2);
2314 // Clang will check explicit VarArg and issue error if any. However, Clang
2315 // will let code with
2316 // implicit var arg like f() pass. See bug 617733.
2317 // We treat this case as if the arg list is empty.
2318 // if (F.isVarArg()) {
2319 // assert(0 && "VarArg not supported yet!");
2322 if (!OutChains.empty())
2323 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2330 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2332 const SmallVectorImpl<ISD::OutputArg> &Outs,
2333 const SmallVectorImpl<SDValue> &OutVals,
2334 SDLoc dl, SelectionDAG &DAG) const {
2335 MachineFunction &MF = DAG.getMachineFunction();
2336 const Function *F = MF.getFunction();
2337 Type *RetTy = F->getReturnType();
2338 const DataLayout *TD = getDataLayout();
2340 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
2341 assert(isABI && "Non-ABI compilation is not supported");
2345 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2346 // If we have a vector type, the OutVals array will be the scalarized
2347 // components and we have combine them into 1 or more vector stores.
2348 unsigned NumElts = VTy->getNumElements();
2349 assert(NumElts == Outs.size() && "Bad scalarization of return value");
2351 // const_cast can be removed in later LLVM versions
2352 EVT EltVT = getValueType(RetTy).getVectorElementType();
2353 bool NeedExtend = false;
2354 if (EltVT.getSizeInBits() < 16)
2359 SDValue StoreVal = OutVals[0];
2360 // We only have one element, so just directly store it
2362 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
2363 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
2364 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2365 DAG.getVTList(MVT::Other), Ops,
2366 EltVT, MachinePointerInfo());
2368 } else if (NumElts == 2) {
2370 SDValue StoreVal0 = OutVals[0];
2371 SDValue StoreVal1 = OutVals[1];
2374 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2375 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
2378 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
2380 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
2381 DAG.getVTList(MVT::Other), Ops,
2382 EltVT, MachinePointerInfo());
2385 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2386 // vector will be expanded to a power of 2 elements, so we know we can
2387 // always round up to the next multiple of 4 when creating the vector
2389 // e.g. 4 elem => 1 st.v4
2390 // 6 elem => 2 st.v4
2391 // 8 elem => 2 st.v4
2392 // 11 elem => 3 st.v4
2394 unsigned VecSize = 4;
2395 if (OutVals[0].getValueType().getSizeInBits() == 64)
2398 unsigned Offset = 0;
2401 EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2402 unsigned PerStoreOffset =
2403 TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2405 for (unsigned i = 0; i < NumElts; i += VecSize) {
2408 SmallVector<SDValue, 8> Ops;
2409 Ops.push_back(Chain);
2410 Ops.push_back(DAG.getConstant(Offset, MVT::i32));
2411 unsigned Opc = NVPTXISD::StoreRetvalV2;
2412 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
2414 StoreVal = OutVals[i];
2416 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2417 Ops.push_back(StoreVal);
2419 if (i + 1 < NumElts) {
2420 StoreVal = OutVals[i + 1];
2422 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2424 StoreVal = DAG.getUNDEF(ExtendedVT);
2426 Ops.push_back(StoreVal);
2429 Opc = NVPTXISD::StoreRetvalV4;
2430 if (i + 2 < NumElts) {
2431 StoreVal = OutVals[i + 2];
2434 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2436 StoreVal = DAG.getUNDEF(ExtendedVT);
2438 Ops.push_back(StoreVal);
2440 if (i + 3 < NumElts) {
2441 StoreVal = OutVals[i + 3];
2444 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2446 StoreVal = DAG.getUNDEF(ExtendedVT);
2448 Ops.push_back(StoreVal);
2451 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2453 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2454 EltVT, MachinePointerInfo());
2455 Offset += PerStoreOffset;
2459 SmallVector<EVT, 16> ValVTs;
2460 SmallVector<uint64_t, 16> Offsets;
2461 ComputePTXValueVTs(*this, RetTy, ValVTs, &Offsets, 0);
2462 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2464 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2465 SDValue theVal = OutVals[i];
2466 EVT TheValType = theVal.getValueType();
2467 unsigned numElems = 1;
2468 if (TheValType.isVector())
2469 numElems = TheValType.getVectorNumElements();
2470 for (unsigned j = 0, je = numElems; j != je; ++j) {
2471 SDValue TmpVal = theVal;
2472 if (TheValType.isVector())
2473 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2474 TheValType.getVectorElementType(), TmpVal,
2475 DAG.getIntPtrConstant(j));
2476 EVT TheStoreType = ValVTs[i];
2477 if (RetTy->isIntegerTy() &&
2478 TD->getTypeAllocSizeInBits(RetTy) < 32) {
2479 // The following zero-extension is for integer types only, and
2480 // specifically not for aggregates.
2481 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2482 TheStoreType = MVT::i32;
2484 else if (TmpVal.getValueType().getSizeInBits() < 16)
2485 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2489 DAG.getConstant(Offsets[i], MVT::i32),
2491 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2492 DAG.getVTList(MVT::Other), Ops,
2494 MachinePointerInfo());
2499 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2503 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2504 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2505 SelectionDAG &DAG) const {
2506 if (Constraint.length() > 1)
2509 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2512 // NVPTX suuport vector of legal types of any length in Intrinsics because the
2513 // NVPTX specific type legalizer
2514 // will legalize them to the PTX supported length.
2515 bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
2516 if (isTypeLegal(VT))
2518 if (VT.isVector()) {
2519 MVT eVT = VT.getVectorElementType();
2520 if (isTypeLegal(eVT))
2526 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2527 switch (Intrinsic) {
2531 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2532 return NVPTXISD::Tex1DFloatS32;
2533 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2534 return NVPTXISD::Tex1DFloatFloat;
2535 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2536 return NVPTXISD::Tex1DFloatFloatLevel;
2537 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2538 return NVPTXISD::Tex1DFloatFloatGrad;
2539 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2540 return NVPTXISD::Tex1DS32S32;
2541 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2542 return NVPTXISD::Tex1DS32Float;
2543 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2544 return NVPTXISD::Tex1DS32FloatLevel;
2545 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2546 return NVPTXISD::Tex1DS32FloatGrad;
2547 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2548 return NVPTXISD::Tex1DU32S32;
2549 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2550 return NVPTXISD::Tex1DU32Float;
2551 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2552 return NVPTXISD::Tex1DU32FloatLevel;
2553 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2554 return NVPTXISD::Tex1DU32FloatGrad;
2556 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2557 return NVPTXISD::Tex1DArrayFloatS32;
2558 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2559 return NVPTXISD::Tex1DArrayFloatFloat;
2560 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2561 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2562 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2563 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2564 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2565 return NVPTXISD::Tex1DArrayS32S32;
2566 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2567 return NVPTXISD::Tex1DArrayS32Float;
2568 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2569 return NVPTXISD::Tex1DArrayS32FloatLevel;
2570 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2571 return NVPTXISD::Tex1DArrayS32FloatGrad;
2572 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2573 return NVPTXISD::Tex1DArrayU32S32;
2574 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2575 return NVPTXISD::Tex1DArrayU32Float;
2576 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2577 return NVPTXISD::Tex1DArrayU32FloatLevel;
2578 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2579 return NVPTXISD::Tex1DArrayU32FloatGrad;
2581 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2582 return NVPTXISD::Tex2DFloatS32;
2583 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2584 return NVPTXISD::Tex2DFloatFloat;
2585 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2586 return NVPTXISD::Tex2DFloatFloatLevel;
2587 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2588 return NVPTXISD::Tex2DFloatFloatGrad;
2589 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2590 return NVPTXISD::Tex2DS32S32;
2591 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2592 return NVPTXISD::Tex2DS32Float;
2593 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2594 return NVPTXISD::Tex2DS32FloatLevel;
2595 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2596 return NVPTXISD::Tex2DS32FloatGrad;
2597 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2598 return NVPTXISD::Tex2DU32S32;
2599 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2600 return NVPTXISD::Tex2DU32Float;
2601 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2602 return NVPTXISD::Tex2DU32FloatLevel;
2603 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2604 return NVPTXISD::Tex2DU32FloatGrad;
2606 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2607 return NVPTXISD::Tex2DArrayFloatS32;
2608 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2609 return NVPTXISD::Tex2DArrayFloatFloat;
2610 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2611 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2612 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2613 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2614 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2615 return NVPTXISD::Tex2DArrayS32S32;
2616 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2617 return NVPTXISD::Tex2DArrayS32Float;
2618 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2619 return NVPTXISD::Tex2DArrayS32FloatLevel;
2620 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2621 return NVPTXISD::Tex2DArrayS32FloatGrad;
2622 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2623 return NVPTXISD::Tex2DArrayU32S32;
2624 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2625 return NVPTXISD::Tex2DArrayU32Float;
2626 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2627 return NVPTXISD::Tex2DArrayU32FloatLevel;
2628 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2629 return NVPTXISD::Tex2DArrayU32FloatGrad;
2631 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2632 return NVPTXISD::Tex3DFloatS32;
2633 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2634 return NVPTXISD::Tex3DFloatFloat;
2635 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2636 return NVPTXISD::Tex3DFloatFloatLevel;
2637 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2638 return NVPTXISD::Tex3DFloatFloatGrad;
2639 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2640 return NVPTXISD::Tex3DS32S32;
2641 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2642 return NVPTXISD::Tex3DS32Float;
2643 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2644 return NVPTXISD::Tex3DS32FloatLevel;
2645 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2646 return NVPTXISD::Tex3DS32FloatGrad;
2647 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2648 return NVPTXISD::Tex3DU32S32;
2649 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2650 return NVPTXISD::Tex3DU32Float;
2651 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2652 return NVPTXISD::Tex3DU32FloatLevel;
2653 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2654 return NVPTXISD::Tex3DU32FloatGrad;
2656 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2657 return NVPTXISD::TexCubeFloatFloat;
2658 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2659 return NVPTXISD::TexCubeFloatFloatLevel;
2660 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2661 return NVPTXISD::TexCubeS32Float;
2662 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2663 return NVPTXISD::TexCubeS32FloatLevel;
2664 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2665 return NVPTXISD::TexCubeU32Float;
2666 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2667 return NVPTXISD::TexCubeU32FloatLevel;
2669 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2670 return NVPTXISD::TexCubeArrayFloatFloat;
2671 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2672 return NVPTXISD::TexCubeArrayFloatFloatLevel;
2673 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2674 return NVPTXISD::TexCubeArrayS32Float;
2675 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2676 return NVPTXISD::TexCubeArrayS32FloatLevel;
2677 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2678 return NVPTXISD::TexCubeArrayU32Float;
2679 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2680 return NVPTXISD::TexCubeArrayU32FloatLevel;
2682 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2683 return NVPTXISD::Tld4R2DFloatFloat;
2684 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2685 return NVPTXISD::Tld4G2DFloatFloat;
2686 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2687 return NVPTXISD::Tld4B2DFloatFloat;
2688 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2689 return NVPTXISD::Tld4A2DFloatFloat;
2690 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2691 return NVPTXISD::Tld4R2DS64Float;
2692 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2693 return NVPTXISD::Tld4G2DS64Float;
2694 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2695 return NVPTXISD::Tld4B2DS64Float;
2696 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2697 return NVPTXISD::Tld4A2DS64Float;
2698 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2699 return NVPTXISD::Tld4R2DU64Float;
2700 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2701 return NVPTXISD::Tld4G2DU64Float;
2702 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2703 return NVPTXISD::Tld4B2DU64Float;
2704 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2705 return NVPTXISD::Tld4A2DU64Float;
2707 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2708 return NVPTXISD::TexUnified1DFloatS32;
2709 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2710 return NVPTXISD::TexUnified1DFloatFloat;
2711 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2712 return NVPTXISD::TexUnified1DFloatFloatLevel;
2713 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2714 return NVPTXISD::TexUnified1DFloatFloatGrad;
2715 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2716 return NVPTXISD::TexUnified1DS32S32;
2717 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2718 return NVPTXISD::TexUnified1DS32Float;
2719 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2720 return NVPTXISD::TexUnified1DS32FloatLevel;
2721 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2722 return NVPTXISD::TexUnified1DS32FloatGrad;
2723 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2724 return NVPTXISD::TexUnified1DU32S32;
2725 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2726 return NVPTXISD::TexUnified1DU32Float;
2727 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2728 return NVPTXISD::TexUnified1DU32FloatLevel;
2729 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2730 return NVPTXISD::TexUnified1DU32FloatGrad;
2732 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2733 return NVPTXISD::TexUnified1DArrayFloatS32;
2734 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2735 return NVPTXISD::TexUnified1DArrayFloatFloat;
2736 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2737 return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2738 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2739 return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2740 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2741 return NVPTXISD::TexUnified1DArrayS32S32;
2742 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2743 return NVPTXISD::TexUnified1DArrayS32Float;
2744 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2745 return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2746 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2747 return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2748 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2749 return NVPTXISD::TexUnified1DArrayU32S32;
2750 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2751 return NVPTXISD::TexUnified1DArrayU32Float;
2752 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2753 return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2754 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2755 return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2757 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2758 return NVPTXISD::TexUnified2DFloatS32;
2759 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2760 return NVPTXISD::TexUnified2DFloatFloat;
2761 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2762 return NVPTXISD::TexUnified2DFloatFloatLevel;
2763 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2764 return NVPTXISD::TexUnified2DFloatFloatGrad;
2765 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2766 return NVPTXISD::TexUnified2DS32S32;
2767 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2768 return NVPTXISD::TexUnified2DS32Float;
2769 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2770 return NVPTXISD::TexUnified2DS32FloatLevel;
2771 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2772 return NVPTXISD::TexUnified2DS32FloatGrad;
2773 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2774 return NVPTXISD::TexUnified2DU32S32;
2775 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2776 return NVPTXISD::TexUnified2DU32Float;
2777 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2778 return NVPTXISD::TexUnified2DU32FloatLevel;
2779 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2780 return NVPTXISD::TexUnified2DU32FloatGrad;
2782 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2783 return NVPTXISD::TexUnified2DArrayFloatS32;
2784 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2785 return NVPTXISD::TexUnified2DArrayFloatFloat;
2786 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2787 return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2788 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2789 return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2790 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2791 return NVPTXISD::TexUnified2DArrayS32S32;
2792 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2793 return NVPTXISD::TexUnified2DArrayS32Float;
2794 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2795 return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2796 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2797 return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2798 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2799 return NVPTXISD::TexUnified2DArrayU32S32;
2800 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2801 return NVPTXISD::TexUnified2DArrayU32Float;
2802 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2803 return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2804 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2805 return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2807 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2808 return NVPTXISD::TexUnified3DFloatS32;
2809 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2810 return NVPTXISD::TexUnified3DFloatFloat;
2811 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2812 return NVPTXISD::TexUnified3DFloatFloatLevel;
2813 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2814 return NVPTXISD::TexUnified3DFloatFloatGrad;
2815 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2816 return NVPTXISD::TexUnified3DS32S32;
2817 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2818 return NVPTXISD::TexUnified3DS32Float;
2819 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2820 return NVPTXISD::TexUnified3DS32FloatLevel;
2821 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2822 return NVPTXISD::TexUnified3DS32FloatGrad;
2823 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2824 return NVPTXISD::TexUnified3DU32S32;
2825 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2826 return NVPTXISD::TexUnified3DU32Float;
2827 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2828 return NVPTXISD::TexUnified3DU32FloatLevel;
2829 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2830 return NVPTXISD::TexUnified3DU32FloatGrad;
2832 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2833 return NVPTXISD::TexUnifiedCubeFloatFloat;
2834 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2835 return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2836 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2837 return NVPTXISD::TexUnifiedCubeS32Float;
2838 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2839 return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2840 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2841 return NVPTXISD::TexUnifiedCubeU32Float;
2842 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2843 return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2845 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2846 return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2847 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2848 return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2849 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2850 return NVPTXISD::TexUnifiedCubeArrayS32Float;
2851 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2852 return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2853 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2854 return NVPTXISD::TexUnifiedCubeArrayU32Float;
2855 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2856 return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2858 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2859 return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2860 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2861 return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2862 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2863 return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2864 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2865 return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2866 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2867 return NVPTXISD::Tld4UnifiedR2DS64Float;
2868 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2869 return NVPTXISD::Tld4UnifiedG2DS64Float;
2870 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2871 return NVPTXISD::Tld4UnifiedB2DS64Float;
2872 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2873 return NVPTXISD::Tld4UnifiedA2DS64Float;
2874 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2875 return NVPTXISD::Tld4UnifiedR2DU64Float;
2876 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2877 return NVPTXISD::Tld4UnifiedG2DU64Float;
2878 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2879 return NVPTXISD::Tld4UnifiedB2DU64Float;
2880 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2881 return NVPTXISD::Tld4UnifiedA2DU64Float;
2885 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2886 switch (Intrinsic) {
2889 case Intrinsic::nvvm_suld_1d_i8_clamp:
2890 return NVPTXISD::Suld1DI8Clamp;
2891 case Intrinsic::nvvm_suld_1d_i16_clamp:
2892 return NVPTXISD::Suld1DI16Clamp;
2893 case Intrinsic::nvvm_suld_1d_i32_clamp:
2894 return NVPTXISD::Suld1DI32Clamp;
2895 case Intrinsic::nvvm_suld_1d_i64_clamp:
2896 return NVPTXISD::Suld1DI64Clamp;
2897 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2898 return NVPTXISD::Suld1DV2I8Clamp;
2899 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2900 return NVPTXISD::Suld1DV2I16Clamp;
2901 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2902 return NVPTXISD::Suld1DV2I32Clamp;
2903 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2904 return NVPTXISD::Suld1DV2I64Clamp;
2905 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2906 return NVPTXISD::Suld1DV4I8Clamp;
2907 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2908 return NVPTXISD::Suld1DV4I16Clamp;
2909 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2910 return NVPTXISD::Suld1DV4I32Clamp;
2911 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2912 return NVPTXISD::Suld1DArrayI8Clamp;
2913 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2914 return NVPTXISD::Suld1DArrayI16Clamp;
2915 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2916 return NVPTXISD::Suld1DArrayI32Clamp;
2917 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2918 return NVPTXISD::Suld1DArrayI64Clamp;
2919 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2920 return NVPTXISD::Suld1DArrayV2I8Clamp;
2921 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2922 return NVPTXISD::Suld1DArrayV2I16Clamp;
2923 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2924 return NVPTXISD::Suld1DArrayV2I32Clamp;
2925 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2926 return NVPTXISD::Suld1DArrayV2I64Clamp;
2927 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2928 return NVPTXISD::Suld1DArrayV4I8Clamp;
2929 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2930 return NVPTXISD::Suld1DArrayV4I16Clamp;
2931 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2932 return NVPTXISD::Suld1DArrayV4I32Clamp;
2933 case Intrinsic::nvvm_suld_2d_i8_clamp:
2934 return NVPTXISD::Suld2DI8Clamp;
2935 case Intrinsic::nvvm_suld_2d_i16_clamp:
2936 return NVPTXISD::Suld2DI16Clamp;
2937 case Intrinsic::nvvm_suld_2d_i32_clamp:
2938 return NVPTXISD::Suld2DI32Clamp;
2939 case Intrinsic::nvvm_suld_2d_i64_clamp:
2940 return NVPTXISD::Suld2DI64Clamp;
2941 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2942 return NVPTXISD::Suld2DV2I8Clamp;
2943 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2944 return NVPTXISD::Suld2DV2I16Clamp;
2945 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2946 return NVPTXISD::Suld2DV2I32Clamp;
2947 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2948 return NVPTXISD::Suld2DV2I64Clamp;
2949 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2950 return NVPTXISD::Suld2DV4I8Clamp;
2951 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2952 return NVPTXISD::Suld2DV4I16Clamp;
2953 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2954 return NVPTXISD::Suld2DV4I32Clamp;
2955 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2956 return NVPTXISD::Suld2DArrayI8Clamp;
2957 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2958 return NVPTXISD::Suld2DArrayI16Clamp;
2959 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
2960 return NVPTXISD::Suld2DArrayI32Clamp;
2961 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
2962 return NVPTXISD::Suld2DArrayI64Clamp;
2963 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
2964 return NVPTXISD::Suld2DArrayV2I8Clamp;
2965 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
2966 return NVPTXISD::Suld2DArrayV2I16Clamp;
2967 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
2968 return NVPTXISD::Suld2DArrayV2I32Clamp;
2969 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
2970 return NVPTXISD::Suld2DArrayV2I64Clamp;
2971 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
2972 return NVPTXISD::Suld2DArrayV4I8Clamp;
2973 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
2974 return NVPTXISD::Suld2DArrayV4I16Clamp;
2975 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
2976 return NVPTXISD::Suld2DArrayV4I32Clamp;
2977 case Intrinsic::nvvm_suld_3d_i8_clamp:
2978 return NVPTXISD::Suld3DI8Clamp;
2979 case Intrinsic::nvvm_suld_3d_i16_clamp:
2980 return NVPTXISD::Suld3DI16Clamp;
2981 case Intrinsic::nvvm_suld_3d_i32_clamp:
2982 return NVPTXISD::Suld3DI32Clamp;
2983 case Intrinsic::nvvm_suld_3d_i64_clamp:
2984 return NVPTXISD::Suld3DI64Clamp;
2985 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
2986 return NVPTXISD::Suld3DV2I8Clamp;
2987 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
2988 return NVPTXISD::Suld3DV2I16Clamp;
2989 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
2990 return NVPTXISD::Suld3DV2I32Clamp;
2991 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
2992 return NVPTXISD::Suld3DV2I64Clamp;
2993 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
2994 return NVPTXISD::Suld3DV4I8Clamp;
2995 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
2996 return NVPTXISD::Suld3DV4I16Clamp;
2997 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
2998 return NVPTXISD::Suld3DV4I32Clamp;
2999 case Intrinsic::nvvm_suld_1d_i8_trap:
3000 return NVPTXISD::Suld1DI8Trap;
3001 case Intrinsic::nvvm_suld_1d_i16_trap:
3002 return NVPTXISD::Suld1DI16Trap;
3003 case Intrinsic::nvvm_suld_1d_i32_trap:
3004 return NVPTXISD::Suld1DI32Trap;
3005 case Intrinsic::nvvm_suld_1d_i64_trap:
3006 return NVPTXISD::Suld1DI64Trap;
3007 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3008 return NVPTXISD::Suld1DV2I8Trap;
3009 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3010 return NVPTXISD::Suld1DV2I16Trap;
3011 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3012 return NVPTXISD::Suld1DV2I32Trap;
3013 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3014 return NVPTXISD::Suld1DV2I64Trap;
3015 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3016 return NVPTXISD::Suld1DV4I8Trap;
3017 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3018 return NVPTXISD::Suld1DV4I16Trap;
3019 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3020 return NVPTXISD::Suld1DV4I32Trap;
3021 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3022 return NVPTXISD::Suld1DArrayI8Trap;
3023 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3024 return NVPTXISD::Suld1DArrayI16Trap;
3025 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3026 return NVPTXISD::Suld1DArrayI32Trap;
3027 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3028 return NVPTXISD::Suld1DArrayI64Trap;
3029 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3030 return NVPTXISD::Suld1DArrayV2I8Trap;
3031 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3032 return NVPTXISD::Suld1DArrayV2I16Trap;
3033 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3034 return NVPTXISD::Suld1DArrayV2I32Trap;
3035 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3036 return NVPTXISD::Suld1DArrayV2I64Trap;
3037 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3038 return NVPTXISD::Suld1DArrayV4I8Trap;
3039 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3040 return NVPTXISD::Suld1DArrayV4I16Trap;
3041 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3042 return NVPTXISD::Suld1DArrayV4I32Trap;
3043 case Intrinsic::nvvm_suld_2d_i8_trap:
3044 return NVPTXISD::Suld2DI8Trap;
3045 case Intrinsic::nvvm_suld_2d_i16_trap:
3046 return NVPTXISD::Suld2DI16Trap;
3047 case Intrinsic::nvvm_suld_2d_i32_trap:
3048 return NVPTXISD::Suld2DI32Trap;
3049 case Intrinsic::nvvm_suld_2d_i64_trap:
3050 return NVPTXISD::Suld2DI64Trap;
3051 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3052 return NVPTXISD::Suld2DV2I8Trap;
3053 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3054 return NVPTXISD::Suld2DV2I16Trap;
3055 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3056 return NVPTXISD::Suld2DV2I32Trap;
3057 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3058 return NVPTXISD::Suld2DV2I64Trap;
3059 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3060 return NVPTXISD::Suld2DV4I8Trap;
3061 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3062 return NVPTXISD::Suld2DV4I16Trap;
3063 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3064 return NVPTXISD::Suld2DV4I32Trap;
3065 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3066 return NVPTXISD::Suld2DArrayI8Trap;
3067 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3068 return NVPTXISD::Suld2DArrayI16Trap;
3069 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3070 return NVPTXISD::Suld2DArrayI32Trap;
3071 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3072 return NVPTXISD::Suld2DArrayI64Trap;
3073 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3074 return NVPTXISD::Suld2DArrayV2I8Trap;
3075 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3076 return NVPTXISD::Suld2DArrayV2I16Trap;
3077 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3078 return NVPTXISD::Suld2DArrayV2I32Trap;
3079 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3080 return NVPTXISD::Suld2DArrayV2I64Trap;
3081 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3082 return NVPTXISD::Suld2DArrayV4I8Trap;
3083 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3084 return NVPTXISD::Suld2DArrayV4I16Trap;
3085 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3086 return NVPTXISD::Suld2DArrayV4I32Trap;
3087 case Intrinsic::nvvm_suld_3d_i8_trap:
3088 return NVPTXISD::Suld3DI8Trap;
3089 case Intrinsic::nvvm_suld_3d_i16_trap:
3090 return NVPTXISD::Suld3DI16Trap;
3091 case Intrinsic::nvvm_suld_3d_i32_trap:
3092 return NVPTXISD::Suld3DI32Trap;
3093 case Intrinsic::nvvm_suld_3d_i64_trap:
3094 return NVPTXISD::Suld3DI64Trap;
3095 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3096 return NVPTXISD::Suld3DV2I8Trap;
3097 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3098 return NVPTXISD::Suld3DV2I16Trap;
3099 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3100 return NVPTXISD::Suld3DV2I32Trap;
3101 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3102 return NVPTXISD::Suld3DV2I64Trap;
3103 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3104 return NVPTXISD::Suld3DV4I8Trap;
3105 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3106 return NVPTXISD::Suld3DV4I16Trap;
3107 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3108 return NVPTXISD::Suld3DV4I32Trap;
3109 case Intrinsic::nvvm_suld_1d_i8_zero:
3110 return NVPTXISD::Suld1DI8Zero;
3111 case Intrinsic::nvvm_suld_1d_i16_zero:
3112 return NVPTXISD::Suld1DI16Zero;
3113 case Intrinsic::nvvm_suld_1d_i32_zero:
3114 return NVPTXISD::Suld1DI32Zero;
3115 case Intrinsic::nvvm_suld_1d_i64_zero:
3116 return NVPTXISD::Suld1DI64Zero;
3117 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3118 return NVPTXISD::Suld1DV2I8Zero;
3119 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3120 return NVPTXISD::Suld1DV2I16Zero;
3121 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3122 return NVPTXISD::Suld1DV2I32Zero;
3123 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3124 return NVPTXISD::Suld1DV2I64Zero;
3125 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3126 return NVPTXISD::Suld1DV4I8Zero;
3127 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3128 return NVPTXISD::Suld1DV4I16Zero;
3129 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3130 return NVPTXISD::Suld1DV4I32Zero;
3131 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3132 return NVPTXISD::Suld1DArrayI8Zero;
3133 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3134 return NVPTXISD::Suld1DArrayI16Zero;
3135 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3136 return NVPTXISD::Suld1DArrayI32Zero;
3137 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3138 return NVPTXISD::Suld1DArrayI64Zero;
3139 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3140 return NVPTXISD::Suld1DArrayV2I8Zero;
3141 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3142 return NVPTXISD::Suld1DArrayV2I16Zero;
3143 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3144 return NVPTXISD::Suld1DArrayV2I32Zero;
3145 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3146 return NVPTXISD::Suld1DArrayV2I64Zero;
3147 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3148 return NVPTXISD::Suld1DArrayV4I8Zero;
3149 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3150 return NVPTXISD::Suld1DArrayV4I16Zero;
3151 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3152 return NVPTXISD::Suld1DArrayV4I32Zero;
3153 case Intrinsic::nvvm_suld_2d_i8_zero:
3154 return NVPTXISD::Suld2DI8Zero;
3155 case Intrinsic::nvvm_suld_2d_i16_zero:
3156 return NVPTXISD::Suld2DI16Zero;
3157 case Intrinsic::nvvm_suld_2d_i32_zero:
3158 return NVPTXISD::Suld2DI32Zero;
3159 case Intrinsic::nvvm_suld_2d_i64_zero:
3160 return NVPTXISD::Suld2DI64Zero;
3161 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3162 return NVPTXISD::Suld2DV2I8Zero;
3163 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3164 return NVPTXISD::Suld2DV2I16Zero;
3165 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3166 return NVPTXISD::Suld2DV2I32Zero;
3167 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3168 return NVPTXISD::Suld2DV2I64Zero;
3169 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3170 return NVPTXISD::Suld2DV4I8Zero;
3171 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3172 return NVPTXISD::Suld2DV4I16Zero;
3173 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3174 return NVPTXISD::Suld2DV4I32Zero;
3175 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3176 return NVPTXISD::Suld2DArrayI8Zero;
3177 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3178 return NVPTXISD::Suld2DArrayI16Zero;
3179 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3180 return NVPTXISD::Suld2DArrayI32Zero;
3181 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3182 return NVPTXISD::Suld2DArrayI64Zero;
3183 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3184 return NVPTXISD::Suld2DArrayV2I8Zero;
3185 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3186 return NVPTXISD::Suld2DArrayV2I16Zero;
3187 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3188 return NVPTXISD::Suld2DArrayV2I32Zero;
3189 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3190 return NVPTXISD::Suld2DArrayV2I64Zero;
3191 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3192 return NVPTXISD::Suld2DArrayV4I8Zero;
3193 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3194 return NVPTXISD::Suld2DArrayV4I16Zero;
3195 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3196 return NVPTXISD::Suld2DArrayV4I32Zero;
3197 case Intrinsic::nvvm_suld_3d_i8_zero:
3198 return NVPTXISD::Suld3DI8Zero;
3199 case Intrinsic::nvvm_suld_3d_i16_zero:
3200 return NVPTXISD::Suld3DI16Zero;
3201 case Intrinsic::nvvm_suld_3d_i32_zero:
3202 return NVPTXISD::Suld3DI32Zero;
3203 case Intrinsic::nvvm_suld_3d_i64_zero:
3204 return NVPTXISD::Suld3DI64Zero;
3205 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3206 return NVPTXISD::Suld3DV2I8Zero;
3207 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3208 return NVPTXISD::Suld3DV2I16Zero;
3209 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3210 return NVPTXISD::Suld3DV2I32Zero;
3211 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3212 return NVPTXISD::Suld3DV2I64Zero;
3213 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3214 return NVPTXISD::Suld3DV4I8Zero;
3215 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3216 return NVPTXISD::Suld3DV4I16Zero;
3217 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3218 return NVPTXISD::Suld3DV4I32Zero;
3222 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3224 // because we need the information that is only available in the "Value" type
3226 // pointer. In particular, the address space information.
3227 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3228 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3229 switch (Intrinsic) {
3233 case Intrinsic::nvvm_atomic_load_add_f32:
3234 Info.opc = ISD::INTRINSIC_W_CHAIN;
3235 Info.memVT = MVT::f32;
3236 Info.ptrVal = I.getArgOperand(0);
3239 Info.readMem = true;
3240 Info.writeMem = true;
3244 case Intrinsic::nvvm_atomic_load_inc_32:
3245 case Intrinsic::nvvm_atomic_load_dec_32:
3246 Info.opc = ISD::INTRINSIC_W_CHAIN;
3247 Info.memVT = MVT::i32;
3248 Info.ptrVal = I.getArgOperand(0);
3251 Info.readMem = true;
3252 Info.writeMem = true;
3256 case Intrinsic::nvvm_ldu_global_i:
3257 case Intrinsic::nvvm_ldu_global_f:
3258 case Intrinsic::nvvm_ldu_global_p: {
3260 Info.opc = ISD::INTRINSIC_W_CHAIN;
3261 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3262 Info.memVT = getValueType(I.getType());
3263 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3264 Info.memVT = getPointerTy();
3266 Info.memVT = getValueType(I.getType());
3267 Info.ptrVal = I.getArgOperand(0);
3270 Info.readMem = true;
3271 Info.writeMem = false;
3273 // alignment is available as metadata.
3274 // Grab it and set the alignment.
3275 assert(I.hasMetadataOtherThanDebugLoc() && "Must have alignment metadata");
3276 MDNode *AlignMD = I.getMetadata("align");
3277 assert(AlignMD && "Must have a non-null MDNode");
3278 assert(AlignMD->getNumOperands() == 1 && "Must have a single operand");
3279 Value *Align = AlignMD->getOperand(0);
3280 int64_t Alignment = cast<ConstantInt>(Align)->getZExtValue();
3281 Info.align = Alignment;
3285 case Intrinsic::nvvm_ldg_global_i:
3286 case Intrinsic::nvvm_ldg_global_f:
3287 case Intrinsic::nvvm_ldg_global_p: {
3289 Info.opc = ISD::INTRINSIC_W_CHAIN;
3290 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3291 Info.memVT = getValueType(I.getType());
3292 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3293 Info.memVT = getPointerTy();
3295 Info.memVT = getValueType(I.getType());
3296 Info.ptrVal = I.getArgOperand(0);
3299 Info.readMem = true;
3300 Info.writeMem = false;
3302 // alignment is available as metadata.
3303 // Grab it and set the alignment.
3304 assert(I.hasMetadataOtherThanDebugLoc() && "Must have alignment metadata");
3305 MDNode *AlignMD = I.getMetadata("align");
3306 assert(AlignMD && "Must have a non-null MDNode");
3307 assert(AlignMD->getNumOperands() == 1 && "Must have a single operand");
3308 Value *Align = AlignMD->getOperand(0);
3309 int64_t Alignment = cast<ConstantInt>(Align)->getZExtValue();
3310 Info.align = Alignment;
3315 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3316 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3317 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3318 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3319 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3320 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3321 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3322 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3323 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3324 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3325 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3326 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3327 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3328 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3329 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3330 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3331 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3332 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3333 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3334 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3335 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3336 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3337 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3338 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3339 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3340 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3341 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3342 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3343 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3344 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3345 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3346 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3347 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3348 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3349 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3350 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3351 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3352 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3353 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3354 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3355 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3356 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3357 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3358 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3359 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3360 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3361 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3362 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3363 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3364 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3365 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3366 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3367 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3368 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3369 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3370 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3371 Info.opc = getOpcForTextureInstr(Intrinsic);
3372 Info.memVT = MVT::v4f32;
3373 Info.ptrVal = nullptr;
3376 Info.readMem = true;
3377 Info.writeMem = false;
3381 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3382 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3383 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3384 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3385 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3386 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3387 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3388 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3389 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3390 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3391 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3392 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3393 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3394 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3395 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3396 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3397 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3398 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3399 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3400 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3401 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3402 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3403 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3404 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3405 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3406 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3407 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3408 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3409 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3410 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3411 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3412 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3413 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3414 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3415 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3416 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3417 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3418 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3419 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3420 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3421 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3422 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3423 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3424 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3425 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3426 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3427 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3428 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3429 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3430 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3431 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3432 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3433 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3434 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3435 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3436 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3437 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3438 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3439 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3440 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3441 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3442 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3443 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3444 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3445 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3446 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3447 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3448 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3449 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3450 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3451 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3452 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3453 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3454 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3455 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3456 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3457 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3458 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3459 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3460 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3461 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3462 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3463 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3464 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3465 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3466 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3467 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3468 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3469 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3470 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3471 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3472 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3473 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3474 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3475 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3476 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3477 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3478 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3479 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3480 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3481 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3482 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3483 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3484 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3485 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3486 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3487 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3488 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3489 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3490 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3491 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3492 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3493 Info.opc = getOpcForTextureInstr(Intrinsic);
3494 Info.memVT = MVT::v4i32;
3495 Info.ptrVal = nullptr;
3498 Info.readMem = true;
3499 Info.writeMem = false;
3503 case Intrinsic::nvvm_suld_1d_i8_clamp:
3504 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3505 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3506 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3507 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3508 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3509 case Intrinsic::nvvm_suld_2d_i8_clamp:
3510 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3511 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3512 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3513 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3514 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3515 case Intrinsic::nvvm_suld_3d_i8_clamp:
3516 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3517 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3518 case Intrinsic::nvvm_suld_1d_i8_trap:
3519 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3520 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3521 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3522 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3523 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3524 case Intrinsic::nvvm_suld_2d_i8_trap:
3525 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3526 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3527 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3528 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3529 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3530 case Intrinsic::nvvm_suld_3d_i8_trap:
3531 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3532 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3533 case Intrinsic::nvvm_suld_1d_i8_zero:
3534 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3535 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3536 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3537 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3538 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3539 case Intrinsic::nvvm_suld_2d_i8_zero:
3540 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3541 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3542 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3543 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3544 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3545 case Intrinsic::nvvm_suld_3d_i8_zero:
3546 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3547 case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3548 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3549 Info.memVT = MVT::i8;
3550 Info.ptrVal = nullptr;
3553 Info.readMem = true;
3554 Info.writeMem = false;
3558 case Intrinsic::nvvm_suld_1d_i16_clamp:
3559 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3560 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3561 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3562 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3563 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3564 case Intrinsic::nvvm_suld_2d_i16_clamp:
3565 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3566 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3567 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3568 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3569 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3570 case Intrinsic::nvvm_suld_3d_i16_clamp:
3571 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3572 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3573 case Intrinsic::nvvm_suld_1d_i16_trap:
3574 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3575 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3576 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3577 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3578 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3579 case Intrinsic::nvvm_suld_2d_i16_trap:
3580 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3581 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3582 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3583 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3584 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3585 case Intrinsic::nvvm_suld_3d_i16_trap:
3586 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3587 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3588 case Intrinsic::nvvm_suld_1d_i16_zero:
3589 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3590 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3591 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3592 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3593 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3594 case Intrinsic::nvvm_suld_2d_i16_zero:
3595 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3596 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3597 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3598 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3599 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3600 case Intrinsic::nvvm_suld_3d_i16_zero:
3601 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3602 case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3603 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3604 Info.memVT = MVT::i16;
3605 Info.ptrVal = nullptr;
3608 Info.readMem = true;
3609 Info.writeMem = false;
3613 case Intrinsic::nvvm_suld_1d_i32_clamp:
3614 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3615 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3616 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3617 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3618 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3619 case Intrinsic::nvvm_suld_2d_i32_clamp:
3620 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3621 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3622 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3623 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3624 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3625 case Intrinsic::nvvm_suld_3d_i32_clamp:
3626 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3627 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3628 case Intrinsic::nvvm_suld_1d_i32_trap:
3629 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3630 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3631 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3632 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3633 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3634 case Intrinsic::nvvm_suld_2d_i32_trap:
3635 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3636 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3637 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3638 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3639 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3640 case Intrinsic::nvvm_suld_3d_i32_trap:
3641 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3642 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3643 case Intrinsic::nvvm_suld_1d_i32_zero:
3644 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3645 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3646 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3647 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3648 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3649 case Intrinsic::nvvm_suld_2d_i32_zero:
3650 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3651 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3652 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3653 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3654 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3655 case Intrinsic::nvvm_suld_3d_i32_zero:
3656 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3657 case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3658 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3659 Info.memVT = MVT::i32;
3660 Info.ptrVal = nullptr;
3663 Info.readMem = true;
3664 Info.writeMem = false;
3668 case Intrinsic::nvvm_suld_1d_i64_clamp:
3669 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3670 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3671 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3672 case Intrinsic::nvvm_suld_2d_i64_clamp:
3673 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3674 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3675 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3676 case Intrinsic::nvvm_suld_3d_i64_clamp:
3677 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3678 case Intrinsic::nvvm_suld_1d_i64_trap:
3679 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3680 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3681 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3682 case Intrinsic::nvvm_suld_2d_i64_trap:
3683 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3684 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3685 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3686 case Intrinsic::nvvm_suld_3d_i64_trap:
3687 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3688 case Intrinsic::nvvm_suld_1d_i64_zero:
3689 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3690 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3691 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3692 case Intrinsic::nvvm_suld_2d_i64_zero:
3693 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3694 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3695 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3696 case Intrinsic::nvvm_suld_3d_i64_zero:
3697 case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3698 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3699 Info.memVT = MVT::i64;
3700 Info.ptrVal = nullptr;
3703 Info.readMem = true;
3704 Info.writeMem = false;
3712 /// isLegalAddressingMode - Return true if the addressing mode represented
3713 /// by AM is legal for this target, for a load/store of the specified type.
3714 /// Used to guide target specific optimizations, like loop strength reduction
3715 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3716 /// (CodeGenPrepare.cpp)
3717 bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3720 // AddrMode - This represents an addressing mode of:
3721 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3723 // The legal address modes are
3730 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
3736 case 0: // "r", "r+i" or "i" is allowed
3739 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3741 // Otherwise we have r+i.
3744 // No scale > 1 is allowed
3750 //===----------------------------------------------------------------------===//
3751 // NVPTX Inline Assembly Support
3752 //===----------------------------------------------------------------------===//
3754 /// getConstraintType - Given a constraint letter, return the type of
3755 /// constraint it is for this target.
3756 NVPTXTargetLowering::ConstraintType
3757 NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
3758 if (Constraint.size() == 1) {
3759 switch (Constraint[0]) {
3771 return C_RegisterClass;
3774 return TargetLowering::getConstraintType(Constraint);
3777 std::pair<unsigned, const TargetRegisterClass *>
3778 NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3780 if (Constraint.size() == 1) {
3781 switch (Constraint[0]) {
3783 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3785 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3787 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3789 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3792 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3794 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3796 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3799 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3802 /// getFunctionAlignment - Return the Log2 alignment of this function.
3803 unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
3807 //===----------------------------------------------------------------------===//
3808 // NVPTX DAG Combining
3809 //===----------------------------------------------------------------------===//
3811 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3812 CodeGenOpt::Level OptLevel) const {
3813 const Function *F = MF.getFunction();
3814 const TargetOptions &TO = MF.getTarget().Options;
3816 // Always honor command-line argument
3817 if (FMAContractLevelOpt.getNumOccurrences() > 0) {
3818 return FMAContractLevelOpt > 0;
3819 } else if (OptLevel == 0) {
3820 // Do not contract if we're not optimizing the code
3822 } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
3823 // Honor TargetOptions flags that explicitly say fusion is okay
3825 } else if (F->hasFnAttribute("unsafe-fp-math")) {
3826 // Check for unsafe-fp-math=true coming from Clang
3827 Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3828 StringRef Val = Attr.getValueAsString();
3833 // We did not have a clear indication that fusion is allowed, so assume not
3837 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3838 /// operands N0 and N1. This is a helper for PerformADDCombine that is
3839 /// called with the default operands, and if that fails, with commuted
3841 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3842 TargetLowering::DAGCombinerInfo &DCI,
3843 const NVPTXSubtarget &Subtarget,
3844 CodeGenOpt::Level OptLevel) {
3845 SelectionDAG &DAG = DCI.DAG;
3846 // Skip non-integer, non-scalar case
3847 EVT VT=N0.getValueType();
3851 // fold (add (mul a, b), c) -> (mad a, b, c)
3853 if (N0.getOpcode() == ISD::MUL) {
3854 assert (VT.isInteger());
3856 // Since integer multiply-add costs the same as integer multiply
3857 // but is more costly than integer add, do the fusion only when
3858 // the mul is only used in the add.
3859 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3860 !N0.getNode()->hasOneUse())
3864 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3865 N0.getOperand(0), N0.getOperand(1), N1);
3867 else if (N0.getOpcode() == ISD::FMUL) {
3868 if (VT == MVT::f32 || VT == MVT::f64) {
3869 NVPTXTargetLowering *TLI =
3870 (NVPTXTargetLowering *)&DAG.getTargetLoweringInfo();
3871 if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3874 // For floating point:
3875 // Do the fusion only when the mul has less than 5 uses and all
3877 // The heuristic is that if a use is not an add, then that use
3878 // cannot be fused into fma, therefore mul is still needed anyway.
3879 // If there are more than 4 uses, even if they are all add, fusing
3880 // them will increase register pressue.
3883 int nonAddCount = 0;
3884 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3885 UE = N0.getNode()->use_end();
3889 if (User->getOpcode() != ISD::FADD)
3895 int orderNo = N->getIROrder();
3896 int orderNo2 = N0.getNode()->getIROrder();
3897 // simple heuristics here for considering potential register
3898 // pressure, the logics here is that the differnce are used
3899 // to measure the distance between def and use, the longer distance
3900 // more likely cause register pressure.
3901 if (orderNo - orderNo2 < 500)
3904 // Now, check if at least one of the FMUL's operands is live beyond the node N,
3905 // which guarantees that the FMA will not increase register pressure at node N.
3906 bool opIsLive = false;
3907 const SDNode *left = N0.getOperand(0).getNode();
3908 const SDNode *right = N0.getOperand(1).getNode();
3910 if (dyn_cast<ConstantSDNode>(left) || dyn_cast<ConstantSDNode>(right))
3914 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
3916 int orderNo3 = User->getIROrder();
3917 if (orderNo3 > orderNo) {
3924 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
3926 int orderNo3 = User->getIROrder();
3927 if (orderNo3 > orderNo) {
3937 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
3938 N0.getOperand(0), N0.getOperand(1), N1);
3945 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3947 static SDValue PerformADDCombine(SDNode *N,
3948 TargetLowering::DAGCombinerInfo &DCI,
3949 const NVPTXSubtarget &Subtarget,
3950 CodeGenOpt::Level OptLevel) {
3951 SDValue N0 = N->getOperand(0);
3952 SDValue N1 = N->getOperand(1);
3954 // First try with the default operand order.
3955 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
3957 if (Result.getNode())
3960 // If that didn't work, try again with the operands commuted.
3961 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
3964 static SDValue PerformANDCombine(SDNode *N,
3965 TargetLowering::DAGCombinerInfo &DCI) {
3966 // The type legalizer turns a vector load of i8 values into a zextload to i16
3967 // registers, optionally ANY_EXTENDs it (if target type is integer),
3968 // and ANDs off the high 8 bits. Since we turn this load into a
3969 // target-specific DAG node, the DAG combiner fails to eliminate these AND
3970 // nodes. Do that here.
3971 SDValue Val = N->getOperand(0);
3972 SDValue Mask = N->getOperand(1);
3974 if (isa<ConstantSDNode>(Val)) {
3975 std::swap(Val, Mask);
3979 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
3980 if (Val.getOpcode() == ISD::ANY_EXTEND) {
3982 Val = Val->getOperand(0);
3985 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
3986 Val = Val->getOperand(0);
3989 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
3990 Val->getOpcode() == NVPTXISD::LoadV4) {
3991 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
3993 // Not an AND with a constant
3997 uint64_t MaskVal = MaskCnst->getZExtValue();
3998 if (MaskVal != 0xff) {
3999 // Not an AND that chops off top 8 bits
4003 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4005 // Not a MemSDNode?!?
4009 EVT MemVT = Mem->getMemoryVT();
4010 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4011 // We only handle the i8 case
4016 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4018 if (ExtType == ISD::SEXTLOAD) {
4019 // If for some reason the load is a sextload, the and is needed to zero
4020 // out the high 8 bits
4025 if (AExt.getNode() != 0) {
4026 // Re-insert the ext as a zext.
4027 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4028 AExt.getValueType(), Val);
4032 // If we get here, the AND is unnecessary. Just replace it with the load
4033 DCI.CombineTo(N, Val, AddTo);
4039 enum OperandSignedness {
4045 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4046 /// that can be demoted to \p OptSize bits without loss of information. The
4047 /// signedness of the operand, if determinable, is placed in \p S.
4048 static bool IsMulWideOperandDemotable(SDValue Op,
4050 OperandSignedness &S) {
4053 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4054 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4055 EVT OrigVT = Op.getOperand(0).getValueType();
4056 if (OrigVT.getSizeInBits() == OptSize) {
4060 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4061 EVT OrigVT = Op.getOperand(0).getValueType();
4062 if (OrigVT.getSizeInBits() == OptSize) {
4071 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4072 /// be demoted to \p OptSize bits without loss of information. If the operands
4073 /// contain a constant, it should appear as the RHS operand. The signedness of
4074 /// the operands is placed in \p IsSigned.
4075 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4079 OperandSignedness LHSSign;
4081 // The LHS operand must be a demotable op
4082 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4085 // We should have been able to determine the signedness from the LHS
4086 if (LHSSign == Unknown)
4089 IsSigned = (LHSSign == Signed);
4091 // The RHS can be a demotable op or a constant
4092 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4093 APInt Val = CI->getAPIntValue();
4094 if (LHSSign == Unsigned) {
4095 if (Val.isIntN(OptSize)) {
4100 if (Val.isSignedIntN(OptSize)) {
4106 OperandSignedness RHSSign;
4107 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4110 if (LHSSign != RHSSign)
4117 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4118 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4119 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4121 static SDValue TryMULWIDECombine(SDNode *N,
4122 TargetLowering::DAGCombinerInfo &DCI) {
4123 EVT MulType = N->getValueType(0);
4124 if (MulType != MVT::i32 && MulType != MVT::i64) {
4128 unsigned OptSize = MulType.getSizeInBits() >> 1;
4129 SDValue LHS = N->getOperand(0);
4130 SDValue RHS = N->getOperand(1);
4132 // Canonicalize the multiply so the constant (if any) is on the right
4133 if (N->getOpcode() == ISD::MUL) {
4134 if (isa<ConstantSDNode>(LHS)) {
4135 std::swap(LHS, RHS);
4139 // If we have a SHL, determine the actual multiply amount
4140 if (N->getOpcode() == ISD::SHL) {
4141 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4146 APInt ShiftAmt = ShlRHS->getAPIntValue();
4147 unsigned BitWidth = MulType.getSizeInBits();
4148 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4149 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4150 RHS = DCI.DAG.getConstant(MulVal, MulType);
4157 // Verify that our operands are demotable
4158 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4163 if (MulType == MVT::i32) {
4164 DemotedVT = MVT::i16;
4166 DemotedVT = MVT::i32;
4169 // Truncate the operands to the correct size. Note that these are just for
4170 // type consistency and will (likely) be eliminated in later phases.
4172 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
4174 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
4178 Opc = NVPTXISD::MUL_WIDE_SIGNED;
4180 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4183 return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
4186 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4187 static SDValue PerformMULCombine(SDNode *N,
4188 TargetLowering::DAGCombinerInfo &DCI,
4189 CodeGenOpt::Level OptLevel) {
4191 // Try mul.wide combining at OptLevel > 0
4192 SDValue Ret = TryMULWIDECombine(N, DCI);
4200 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4201 static SDValue PerformSHLCombine(SDNode *N,
4202 TargetLowering::DAGCombinerInfo &DCI,
4203 CodeGenOpt::Level OptLevel) {
4205 // Try mul.wide combining at OptLevel > 0
4206 SDValue Ret = TryMULWIDECombine(N, DCI);
4214 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4215 DAGCombinerInfo &DCI) const {
4216 CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4217 switch (N->getOpcode()) {
4221 return PerformADDCombine(N, DCI, nvptxSubtarget, OptLevel);
4223 return PerformMULCombine(N, DCI, OptLevel);
4225 return PerformSHLCombine(N, DCI, OptLevel);
4227 return PerformANDCombine(N, DCI);
4232 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4233 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4234 const DataLayout *TD,
4235 SmallVectorImpl<SDValue> &Results) {
4236 EVT ResVT = N->getValueType(0);
4239 assert(ResVT.isVector() && "Vector load must have vector type");
4241 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4242 // legal. We can (and should) split that into 2 loads of <2 x double> here
4243 // but I'm leaving that as a TODO for now.
4244 assert(ResVT.isSimple() && "Can only handle simple types");
4245 switch (ResVT.getSimpleVT().SimpleTy) {
4258 // This is a "native" vector type
4262 LoadSDNode *LD = cast<LoadSDNode>(N);
4264 unsigned Align = LD->getAlignment();
4265 unsigned PrefAlign =
4266 TD->getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4267 if (Align < PrefAlign) {
4268 // This load is not sufficiently aligned, so bail out and let this vector
4269 // load be scalarized. Note that we may still be able to emit smaller
4270 // vector loads. For example, if we are loading a <4 x float> with an
4271 // alignment of 8, this check will fail but the legalizer will try again
4272 // with 2 x <2 x float>, which will succeed with an alignment of 8.
4276 EVT EltVT = ResVT.getVectorElementType();
4277 unsigned NumElts = ResVT.getVectorNumElements();
4279 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4280 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4281 // loaded type to i16 and propagate the "real" type as the memory type.
4282 bool NeedTrunc = false;
4283 if (EltVT.getSizeInBits() < 16) {
4288 unsigned Opcode = 0;
4295 Opcode = NVPTXISD::LoadV2;
4296 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4299 Opcode = NVPTXISD::LoadV4;
4300 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4301 LdResVTs = DAG.getVTList(ListVTs);
4306 SmallVector<SDValue, 8> OtherOps;
4308 // Copy regular operands
4309 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4310 OtherOps.push_back(N->getOperand(i));
4312 // The select routine does not have access to the LoadSDNode instance, so
4313 // pass along the extension information
4314 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
4316 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4318 LD->getMemOperand());
4320 SmallVector<SDValue, 4> ScalarRes;
4322 for (unsigned i = 0; i < NumElts; ++i) {
4323 SDValue Res = NewLD.getValue(i);
4325 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4326 ScalarRes.push_back(Res);
4329 SDValue LoadChain = NewLD.getValue(NumElts);
4331 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4333 Results.push_back(BuildVec);
4334 Results.push_back(LoadChain);
4337 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4338 SmallVectorImpl<SDValue> &Results) {
4339 SDValue Chain = N->getOperand(0);
4340 SDValue Intrin = N->getOperand(1);
4343 // Get the intrinsic ID
4344 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4348 case Intrinsic::nvvm_ldg_global_i:
4349 case Intrinsic::nvvm_ldg_global_f:
4350 case Intrinsic::nvvm_ldg_global_p:
4351 case Intrinsic::nvvm_ldu_global_i:
4352 case Intrinsic::nvvm_ldu_global_f:
4353 case Intrinsic::nvvm_ldu_global_p: {
4354 EVT ResVT = N->getValueType(0);
4356 if (ResVT.isVector()) {
4359 unsigned NumElts = ResVT.getVectorNumElements();
4360 EVT EltVT = ResVT.getVectorElementType();
4362 // Since LDU/LDG are target nodes, we cannot rely on DAG type
4364 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4365 // loaded type to i16 and propagate the "real" type as the memory type.
4366 bool NeedTrunc = false;
4367 if (EltVT.getSizeInBits() < 16) {
4372 unsigned Opcode = 0;
4382 case Intrinsic::nvvm_ldg_global_i:
4383 case Intrinsic::nvvm_ldg_global_f:
4384 case Intrinsic::nvvm_ldg_global_p:
4385 Opcode = NVPTXISD::LDGV2;
4387 case Intrinsic::nvvm_ldu_global_i:
4388 case Intrinsic::nvvm_ldu_global_f:
4389 case Intrinsic::nvvm_ldu_global_p:
4390 Opcode = NVPTXISD::LDUV2;
4393 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4399 case Intrinsic::nvvm_ldg_global_i:
4400 case Intrinsic::nvvm_ldg_global_f:
4401 case Intrinsic::nvvm_ldg_global_p:
4402 Opcode = NVPTXISD::LDGV4;
4404 case Intrinsic::nvvm_ldu_global_i:
4405 case Intrinsic::nvvm_ldu_global_f:
4406 case Intrinsic::nvvm_ldu_global_p:
4407 Opcode = NVPTXISD::LDUV4;
4410 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4411 LdResVTs = DAG.getVTList(ListVTs);
4416 SmallVector<SDValue, 8> OtherOps;
4418 // Copy regular operands
4420 OtherOps.push_back(Chain); // Chain
4421 // Skip operand 1 (intrinsic ID)
4423 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
4424 OtherOps.push_back(N->getOperand(i));
4426 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4428 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4429 MemSD->getMemoryVT(),
4430 MemSD->getMemOperand());
4432 SmallVector<SDValue, 4> ScalarRes;
4434 for (unsigned i = 0; i < NumElts; ++i) {
4435 SDValue Res = NewLD.getValue(i);
4438 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4439 ScalarRes.push_back(Res);
4442 SDValue LoadChain = NewLD.getValue(NumElts);
4445 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4447 Results.push_back(BuildVec);
4448 Results.push_back(LoadChain);
4451 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4452 "Custom handling of non-i8 ldu/ldg?");
4454 // Just copy all operands as-is
4455 SmallVector<SDValue, 4> Ops;
4456 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4457 Ops.push_back(N->getOperand(i));
4459 // Force output to i16
4460 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4462 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4464 // We make sure the memory type is i8, which will be used during isel
4465 // to select the proper instruction.
4467 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4468 MVT::i8, MemSD->getMemOperand());
4470 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4471 NewLD.getValue(0)));
4472 Results.push_back(NewLD.getValue(1));
4478 void NVPTXTargetLowering::ReplaceNodeResults(
4479 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4480 switch (N->getOpcode()) {
4482 report_fatal_error("Unhandled custom legalization");
4484 ReplaceLoadVector(N, DAG, getDataLayout(), Results);
4486 case ISD::INTRINSIC_W_CHAIN:
4487 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4492 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4493 void NVPTXSection::anchor() {}
4495 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4499 delete ReadOnlySection;
4501 delete StaticCtorSection;
4502 delete StaticDtorSection;
4504 delete EHFrameSection;
4505 delete DwarfAbbrevSection;
4506 delete DwarfInfoSection;
4507 delete DwarfLineSection;
4508 delete DwarfFrameSection;
4509 delete DwarfPubTypesSection;
4510 delete DwarfDebugInlineSection;
4511 delete DwarfStrSection;
4512 delete DwarfLocSection;
4513 delete DwarfARangesSection;
4514 delete DwarfRangesSection;
4515 delete DwarfMacroInfoSection;