1 //===-- NVPTXISelLowering.cpp - NVPTX DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/NVPTXBaseInfo.h"
17 #include "NVPTXISelLowering.h"
18 #include "NVPTXSection.h"
19 #include "NVPTXSubtarget.h"
20 #include "NVPTXTargetMachine.h"
21 #include "NVPTXTargetObjectFile.h"
22 #include "NVPTXUtilities.h"
23 #include "llvm/ADT/APInt.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/IR/Argument.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/IR/Value.h"
46 #include "llvm/Support/Casting.h"
47 #include "llvm/Support/CodeGen.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetCallingConv.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
66 #define DEBUG_TYPE "nvptx-lower"
70 static unsigned int uniqueCallSite = 0;
72 static cl::opt<bool> sched4reg(
74 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
76 static cl::opt<unsigned>
77 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
78 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
79 " 1: do it 2: do it aggressively"),
82 static bool IsPTXVectorType(MVT VT) {
83 switch (VT.SimpleTy) {
102 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
103 /// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
104 /// into their primitive components.
105 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
106 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
107 /// LowerCall, and LowerReturn.
108 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
109 Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
110 SmallVectorImpl<uint64_t> *Offsets = nullptr,
111 uint64_t StartingOffset = 0) {
112 SmallVector<EVT, 16> TempVTs;
113 SmallVector<uint64_t, 16> TempOffsets;
115 ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
116 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
118 uint64_t Off = TempOffsets[i];
120 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
121 ValueVTs.push_back(VT.getVectorElementType());
123 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
126 ValueVTs.push_back(VT);
128 Offsets->push_back(Off);
133 // NVPTXTargetLowering Constructor.
134 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
135 const NVPTXSubtarget &STI)
136 : TargetLowering(TM), nvTM(&TM), STI(STI) {
137 // always lower memset, memcpy, and memmove intrinsics to load/store
138 // instructions, rather
139 // then generating calls to memset, mempcy or memmove.
140 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
141 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
142 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
144 setBooleanContents(ZeroOrNegativeOneBooleanContent);
145 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
147 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
148 // condition branches.
149 setJumpIsExpensive(true);
151 // Wide divides are _very_ slow. Try to reduce the width of the divide if
153 addBypassSlowDiv(64, 32);
155 // By default, use the Source scheduling
157 setSchedulingPreference(Sched::RegPressure);
159 setSchedulingPreference(Sched::Source);
161 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
162 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
163 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
164 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
165 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
166 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
168 // Operations not directly supported by NVPTX.
169 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
170 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
171 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
172 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
173 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
174 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
175 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
176 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
177 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
178 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
179 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
180 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
181 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
182 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
183 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
184 // For others we will expand to a SHL/SRA pair.
185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
186 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
191 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
192 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
193 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
194 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
195 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
196 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
198 if (STI.hasROT64()) {
199 setOperationAction(ISD::ROTL, MVT::i64, Legal);
200 setOperationAction(ISD::ROTR, MVT::i64, Legal);
202 setOperationAction(ISD::ROTL, MVT::i64, Expand);
203 setOperationAction(ISD::ROTR, MVT::i64, Expand);
205 if (STI.hasROT32()) {
206 setOperationAction(ISD::ROTL, MVT::i32, Legal);
207 setOperationAction(ISD::ROTR, MVT::i32, Legal);
209 setOperationAction(ISD::ROTL, MVT::i32, Expand);
210 setOperationAction(ISD::ROTR, MVT::i32, Expand);
213 setOperationAction(ISD::ROTL, MVT::i16, Expand);
214 setOperationAction(ISD::ROTR, MVT::i16, Expand);
215 setOperationAction(ISD::ROTL, MVT::i8, Expand);
216 setOperationAction(ISD::ROTR, MVT::i8, Expand);
217 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
218 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
219 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
221 // Indirect branch is not supported.
222 // This also disables Jump Table creation.
223 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
224 setOperationAction(ISD::BRIND, MVT::Other, Expand);
226 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
227 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
229 // We want to legalize constant related memmove and memcopy
231 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
233 // Turn FP extload into load/fpextend
234 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
235 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
236 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
237 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
238 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
239 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
240 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
241 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
242 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
243 // Turn FP truncstore into trunc + store.
244 // FIXME: vector types should also be expanded
245 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
246 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
247 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
249 // PTX does not support load / store predicate registers
250 setOperationAction(ISD::LOAD, MVT::i1, Custom);
251 setOperationAction(ISD::STORE, MVT::i1, Custom);
253 for (MVT VT : MVT::integer_valuetypes()) {
254 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
255 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
256 setTruncStoreAction(VT, MVT::i1, Expand);
259 // This is legal in NVPTX
260 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
261 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
263 // TRAP can be lowered to PTX trap
264 setOperationAction(ISD::TRAP, MVT::Other, Legal);
266 setOperationAction(ISD::ADDC, MVT::i64, Expand);
267 setOperationAction(ISD::ADDE, MVT::i64, Expand);
269 // Register custom handling for vector loads/stores
270 for (MVT VT : MVT::vector_valuetypes()) {
271 if (IsPTXVectorType(VT)) {
272 setOperationAction(ISD::LOAD, VT, Custom);
273 setOperationAction(ISD::STORE, VT, Custom);
274 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
278 // Custom handling for i8 intrinsics
279 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
281 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
282 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
283 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
284 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
285 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
286 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
287 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
288 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
289 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
291 // PTX does not directly support SELP of i1, so promote to i32 first
292 setOperationAction(ISD::SELECT, MVT::i1, Custom);
294 // PTX cannot multiply two i64s in a single instruction.
295 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
296 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
298 // We have some custom DAG combine patterns for these nodes
299 setTargetDAGCombine(ISD::ADD);
300 setTargetDAGCombine(ISD::AND);
301 setTargetDAGCombine(ISD::FADD);
302 setTargetDAGCombine(ISD::MUL);
303 setTargetDAGCombine(ISD::SHL);
304 setTargetDAGCombine(ISD::SELECT);
305 setTargetDAGCombine(ISD::SREM);
306 setTargetDAGCombine(ISD::UREM);
308 // Library functions. These default to Expand, but we have instructions
310 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
311 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
312 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
313 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
314 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
315 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
316 setOperationAction(ISD::FRINT, MVT::f32, Legal);
317 setOperationAction(ISD::FRINT, MVT::f64, Legal);
318 setOperationAction(ISD::FROUND, MVT::f32, Legal);
319 setOperationAction(ISD::FROUND, MVT::f64, Legal);
320 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
321 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
322 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
323 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
324 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
325 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
327 // No FEXP2, FLOG2. The PTX ex2 and log2 functions are always approximate.
328 // No FPOW or FREM in PTX.
330 // Now deduce the information based on the above mentioned
332 computeRegisterProperties(STI.getRegisterInfo());
335 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
336 switch ((NVPTXISD::NodeType)Opcode) {
337 case NVPTXISD::FIRST_NUMBER:
340 return "NVPTXISD::CALL";
341 case NVPTXISD::RET_FLAG:
342 return "NVPTXISD::RET_FLAG";
343 case NVPTXISD::LOAD_PARAM:
344 return "NVPTXISD::LOAD_PARAM";
345 case NVPTXISD::Wrapper:
346 return "NVPTXISD::Wrapper";
347 case NVPTXISD::DeclareParam:
348 return "NVPTXISD::DeclareParam";
349 case NVPTXISD::DeclareScalarParam:
350 return "NVPTXISD::DeclareScalarParam";
351 case NVPTXISD::DeclareRet:
352 return "NVPTXISD::DeclareRet";
353 case NVPTXISD::DeclareScalarRet:
354 return "NVPTXISD::DeclareScalarRet";
355 case NVPTXISD::DeclareRetParam:
356 return "NVPTXISD::DeclareRetParam";
357 case NVPTXISD::PrintCall:
358 return "NVPTXISD::PrintCall";
359 case NVPTXISD::PrintConvergentCall:
360 return "NVPTXISD::PrintConvergentCall";
361 case NVPTXISD::PrintCallUni:
362 return "NVPTXISD::PrintCallUni";
363 case NVPTXISD::PrintConvergentCallUni:
364 return "NVPTXISD::PrintConvergentCallUni";
365 case NVPTXISD::LoadParam:
366 return "NVPTXISD::LoadParam";
367 case NVPTXISD::LoadParamV2:
368 return "NVPTXISD::LoadParamV2";
369 case NVPTXISD::LoadParamV4:
370 return "NVPTXISD::LoadParamV4";
371 case NVPTXISD::StoreParam:
372 return "NVPTXISD::StoreParam";
373 case NVPTXISD::StoreParamV2:
374 return "NVPTXISD::StoreParamV2";
375 case NVPTXISD::StoreParamV4:
376 return "NVPTXISD::StoreParamV4";
377 case NVPTXISD::StoreParamS32:
378 return "NVPTXISD::StoreParamS32";
379 case NVPTXISD::StoreParamU32:
380 return "NVPTXISD::StoreParamU32";
381 case NVPTXISD::CallArgBegin:
382 return "NVPTXISD::CallArgBegin";
383 case NVPTXISD::CallArg:
384 return "NVPTXISD::CallArg";
385 case NVPTXISD::LastCallArg:
386 return "NVPTXISD::LastCallArg";
387 case NVPTXISD::CallArgEnd:
388 return "NVPTXISD::CallArgEnd";
389 case NVPTXISD::CallVoid:
390 return "NVPTXISD::CallVoid";
391 case NVPTXISD::CallVal:
392 return "NVPTXISD::CallVal";
393 case NVPTXISD::CallSymbol:
394 return "NVPTXISD::CallSymbol";
395 case NVPTXISD::Prototype:
396 return "NVPTXISD::Prototype";
397 case NVPTXISD::MoveParam:
398 return "NVPTXISD::MoveParam";
399 case NVPTXISD::StoreRetval:
400 return "NVPTXISD::StoreRetval";
401 case NVPTXISD::StoreRetvalV2:
402 return "NVPTXISD::StoreRetvalV2";
403 case NVPTXISD::StoreRetvalV4:
404 return "NVPTXISD::StoreRetvalV4";
405 case NVPTXISD::PseudoUseParam:
406 return "NVPTXISD::PseudoUseParam";
407 case NVPTXISD::RETURN:
408 return "NVPTXISD::RETURN";
409 case NVPTXISD::CallSeqBegin:
410 return "NVPTXISD::CallSeqBegin";
411 case NVPTXISD::CallSeqEnd:
412 return "NVPTXISD::CallSeqEnd";
413 case NVPTXISD::CallPrototype:
414 return "NVPTXISD::CallPrototype";
415 case NVPTXISD::LoadV2:
416 return "NVPTXISD::LoadV2";
417 case NVPTXISD::LoadV4:
418 return "NVPTXISD::LoadV4";
419 case NVPTXISD::LDGV2:
420 return "NVPTXISD::LDGV2";
421 case NVPTXISD::LDGV4:
422 return "NVPTXISD::LDGV4";
423 case NVPTXISD::LDUV2:
424 return "NVPTXISD::LDUV2";
425 case NVPTXISD::LDUV4:
426 return "NVPTXISD::LDUV4";
427 case NVPTXISD::StoreV2:
428 return "NVPTXISD::StoreV2";
429 case NVPTXISD::StoreV4:
430 return "NVPTXISD::StoreV4";
431 case NVPTXISD::FUN_SHFL_CLAMP:
432 return "NVPTXISD::FUN_SHFL_CLAMP";
433 case NVPTXISD::FUN_SHFR_CLAMP:
434 return "NVPTXISD::FUN_SHFR_CLAMP";
436 return "NVPTXISD::IMAD";
437 case NVPTXISD::Dummy:
438 return "NVPTXISD::Dummy";
439 case NVPTXISD::MUL_WIDE_SIGNED:
440 return "NVPTXISD::MUL_WIDE_SIGNED";
441 case NVPTXISD::MUL_WIDE_UNSIGNED:
442 return "NVPTXISD::MUL_WIDE_UNSIGNED";
443 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
444 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
445 case NVPTXISD::Tex1DFloatFloatLevel:
446 return "NVPTXISD::Tex1DFloatFloatLevel";
447 case NVPTXISD::Tex1DFloatFloatGrad:
448 return "NVPTXISD::Tex1DFloatFloatGrad";
449 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
450 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
451 case NVPTXISD::Tex1DS32FloatLevel:
452 return "NVPTXISD::Tex1DS32FloatLevel";
453 case NVPTXISD::Tex1DS32FloatGrad:
454 return "NVPTXISD::Tex1DS32FloatGrad";
455 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
456 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
457 case NVPTXISD::Tex1DU32FloatLevel:
458 return "NVPTXISD::Tex1DU32FloatLevel";
459 case NVPTXISD::Tex1DU32FloatGrad:
460 return "NVPTXISD::Tex1DU32FloatGrad";
461 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
462 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
463 case NVPTXISD::Tex1DArrayFloatFloatLevel:
464 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
465 case NVPTXISD::Tex1DArrayFloatFloatGrad:
466 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
467 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
468 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
469 case NVPTXISD::Tex1DArrayS32FloatLevel:
470 return "NVPTXISD::Tex1DArrayS32FloatLevel";
471 case NVPTXISD::Tex1DArrayS32FloatGrad:
472 return "NVPTXISD::Tex1DArrayS32FloatGrad";
473 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
474 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
475 case NVPTXISD::Tex1DArrayU32FloatLevel:
476 return "NVPTXISD::Tex1DArrayU32FloatLevel";
477 case NVPTXISD::Tex1DArrayU32FloatGrad:
478 return "NVPTXISD::Tex1DArrayU32FloatGrad";
479 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
480 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
481 case NVPTXISD::Tex2DFloatFloatLevel:
482 return "NVPTXISD::Tex2DFloatFloatLevel";
483 case NVPTXISD::Tex2DFloatFloatGrad:
484 return "NVPTXISD::Tex2DFloatFloatGrad";
485 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
486 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
487 case NVPTXISD::Tex2DS32FloatLevel:
488 return "NVPTXISD::Tex2DS32FloatLevel";
489 case NVPTXISD::Tex2DS32FloatGrad:
490 return "NVPTXISD::Tex2DS32FloatGrad";
491 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
492 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
493 case NVPTXISD::Tex2DU32FloatLevel:
494 return "NVPTXISD::Tex2DU32FloatLevel";
495 case NVPTXISD::Tex2DU32FloatGrad:
496 return "NVPTXISD::Tex2DU32FloatGrad";
497 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
498 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
499 case NVPTXISD::Tex2DArrayFloatFloatLevel:
500 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
501 case NVPTXISD::Tex2DArrayFloatFloatGrad:
502 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
503 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
504 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
505 case NVPTXISD::Tex2DArrayS32FloatLevel:
506 return "NVPTXISD::Tex2DArrayS32FloatLevel";
507 case NVPTXISD::Tex2DArrayS32FloatGrad:
508 return "NVPTXISD::Tex2DArrayS32FloatGrad";
509 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
510 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
511 case NVPTXISD::Tex2DArrayU32FloatLevel:
512 return "NVPTXISD::Tex2DArrayU32FloatLevel";
513 case NVPTXISD::Tex2DArrayU32FloatGrad:
514 return "NVPTXISD::Tex2DArrayU32FloatGrad";
515 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
516 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
517 case NVPTXISD::Tex3DFloatFloatLevel:
518 return "NVPTXISD::Tex3DFloatFloatLevel";
519 case NVPTXISD::Tex3DFloatFloatGrad:
520 return "NVPTXISD::Tex3DFloatFloatGrad";
521 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
522 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
523 case NVPTXISD::Tex3DS32FloatLevel:
524 return "NVPTXISD::Tex3DS32FloatLevel";
525 case NVPTXISD::Tex3DS32FloatGrad:
526 return "NVPTXISD::Tex3DS32FloatGrad";
527 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
528 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
529 case NVPTXISD::Tex3DU32FloatLevel:
530 return "NVPTXISD::Tex3DU32FloatLevel";
531 case NVPTXISD::Tex3DU32FloatGrad:
532 return "NVPTXISD::Tex3DU32FloatGrad";
533 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
534 case NVPTXISD::TexCubeFloatFloatLevel:
535 return "NVPTXISD::TexCubeFloatFloatLevel";
536 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
537 case NVPTXISD::TexCubeS32FloatLevel:
538 return "NVPTXISD::TexCubeS32FloatLevel";
539 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
540 case NVPTXISD::TexCubeU32FloatLevel:
541 return "NVPTXISD::TexCubeU32FloatLevel";
542 case NVPTXISD::TexCubeArrayFloatFloat:
543 return "NVPTXISD::TexCubeArrayFloatFloat";
544 case NVPTXISD::TexCubeArrayFloatFloatLevel:
545 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
546 case NVPTXISD::TexCubeArrayS32Float:
547 return "NVPTXISD::TexCubeArrayS32Float";
548 case NVPTXISD::TexCubeArrayS32FloatLevel:
549 return "NVPTXISD::TexCubeArrayS32FloatLevel";
550 case NVPTXISD::TexCubeArrayU32Float:
551 return "NVPTXISD::TexCubeArrayU32Float";
552 case NVPTXISD::TexCubeArrayU32FloatLevel:
553 return "NVPTXISD::TexCubeArrayU32FloatLevel";
554 case NVPTXISD::Tld4R2DFloatFloat:
555 return "NVPTXISD::Tld4R2DFloatFloat";
556 case NVPTXISD::Tld4G2DFloatFloat:
557 return "NVPTXISD::Tld4G2DFloatFloat";
558 case NVPTXISD::Tld4B2DFloatFloat:
559 return "NVPTXISD::Tld4B2DFloatFloat";
560 case NVPTXISD::Tld4A2DFloatFloat:
561 return "NVPTXISD::Tld4A2DFloatFloat";
562 case NVPTXISD::Tld4R2DS64Float:
563 return "NVPTXISD::Tld4R2DS64Float";
564 case NVPTXISD::Tld4G2DS64Float:
565 return "NVPTXISD::Tld4G2DS64Float";
566 case NVPTXISD::Tld4B2DS64Float:
567 return "NVPTXISD::Tld4B2DS64Float";
568 case NVPTXISD::Tld4A2DS64Float:
569 return "NVPTXISD::Tld4A2DS64Float";
570 case NVPTXISD::Tld4R2DU64Float:
571 return "NVPTXISD::Tld4R2DU64Float";
572 case NVPTXISD::Tld4G2DU64Float:
573 return "NVPTXISD::Tld4G2DU64Float";
574 case NVPTXISD::Tld4B2DU64Float:
575 return "NVPTXISD::Tld4B2DU64Float";
576 case NVPTXISD::Tld4A2DU64Float:
577 return "NVPTXISD::Tld4A2DU64Float";
579 case NVPTXISD::TexUnified1DFloatS32:
580 return "NVPTXISD::TexUnified1DFloatS32";
581 case NVPTXISD::TexUnified1DFloatFloat:
582 return "NVPTXISD::TexUnified1DFloatFloat";
583 case NVPTXISD::TexUnified1DFloatFloatLevel:
584 return "NVPTXISD::TexUnified1DFloatFloatLevel";
585 case NVPTXISD::TexUnified1DFloatFloatGrad:
586 return "NVPTXISD::TexUnified1DFloatFloatGrad";
587 case NVPTXISD::TexUnified1DS32S32:
588 return "NVPTXISD::TexUnified1DS32S32";
589 case NVPTXISD::TexUnified1DS32Float:
590 return "NVPTXISD::TexUnified1DS32Float";
591 case NVPTXISD::TexUnified1DS32FloatLevel:
592 return "NVPTXISD::TexUnified1DS32FloatLevel";
593 case NVPTXISD::TexUnified1DS32FloatGrad:
594 return "NVPTXISD::TexUnified1DS32FloatGrad";
595 case NVPTXISD::TexUnified1DU32S32:
596 return "NVPTXISD::TexUnified1DU32S32";
597 case NVPTXISD::TexUnified1DU32Float:
598 return "NVPTXISD::TexUnified1DU32Float";
599 case NVPTXISD::TexUnified1DU32FloatLevel:
600 return "NVPTXISD::TexUnified1DU32FloatLevel";
601 case NVPTXISD::TexUnified1DU32FloatGrad:
602 return "NVPTXISD::TexUnified1DU32FloatGrad";
603 case NVPTXISD::TexUnified1DArrayFloatS32:
604 return "NVPTXISD::TexUnified1DArrayFloatS32";
605 case NVPTXISD::TexUnified1DArrayFloatFloat:
606 return "NVPTXISD::TexUnified1DArrayFloatFloat";
607 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
608 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
609 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
610 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
611 case NVPTXISD::TexUnified1DArrayS32S32:
612 return "NVPTXISD::TexUnified1DArrayS32S32";
613 case NVPTXISD::TexUnified1DArrayS32Float:
614 return "NVPTXISD::TexUnified1DArrayS32Float";
615 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
616 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
617 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
618 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
619 case NVPTXISD::TexUnified1DArrayU32S32:
620 return "NVPTXISD::TexUnified1DArrayU32S32";
621 case NVPTXISD::TexUnified1DArrayU32Float:
622 return "NVPTXISD::TexUnified1DArrayU32Float";
623 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
624 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
625 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
626 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
627 case NVPTXISD::TexUnified2DFloatS32:
628 return "NVPTXISD::TexUnified2DFloatS32";
629 case NVPTXISD::TexUnified2DFloatFloat:
630 return "NVPTXISD::TexUnified2DFloatFloat";
631 case NVPTXISD::TexUnified2DFloatFloatLevel:
632 return "NVPTXISD::TexUnified2DFloatFloatLevel";
633 case NVPTXISD::TexUnified2DFloatFloatGrad:
634 return "NVPTXISD::TexUnified2DFloatFloatGrad";
635 case NVPTXISD::TexUnified2DS32S32:
636 return "NVPTXISD::TexUnified2DS32S32";
637 case NVPTXISD::TexUnified2DS32Float:
638 return "NVPTXISD::TexUnified2DS32Float";
639 case NVPTXISD::TexUnified2DS32FloatLevel:
640 return "NVPTXISD::TexUnified2DS32FloatLevel";
641 case NVPTXISD::TexUnified2DS32FloatGrad:
642 return "NVPTXISD::TexUnified2DS32FloatGrad";
643 case NVPTXISD::TexUnified2DU32S32:
644 return "NVPTXISD::TexUnified2DU32S32";
645 case NVPTXISD::TexUnified2DU32Float:
646 return "NVPTXISD::TexUnified2DU32Float";
647 case NVPTXISD::TexUnified2DU32FloatLevel:
648 return "NVPTXISD::TexUnified2DU32FloatLevel";
649 case NVPTXISD::TexUnified2DU32FloatGrad:
650 return "NVPTXISD::TexUnified2DU32FloatGrad";
651 case NVPTXISD::TexUnified2DArrayFloatS32:
652 return "NVPTXISD::TexUnified2DArrayFloatS32";
653 case NVPTXISD::TexUnified2DArrayFloatFloat:
654 return "NVPTXISD::TexUnified2DArrayFloatFloat";
655 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
656 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
657 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
658 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
659 case NVPTXISD::TexUnified2DArrayS32S32:
660 return "NVPTXISD::TexUnified2DArrayS32S32";
661 case NVPTXISD::TexUnified2DArrayS32Float:
662 return "NVPTXISD::TexUnified2DArrayS32Float";
663 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
664 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
665 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
666 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
667 case NVPTXISD::TexUnified2DArrayU32S32:
668 return "NVPTXISD::TexUnified2DArrayU32S32";
669 case NVPTXISD::TexUnified2DArrayU32Float:
670 return "NVPTXISD::TexUnified2DArrayU32Float";
671 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
672 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
673 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
674 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
675 case NVPTXISD::TexUnified3DFloatS32:
676 return "NVPTXISD::TexUnified3DFloatS32";
677 case NVPTXISD::TexUnified3DFloatFloat:
678 return "NVPTXISD::TexUnified3DFloatFloat";
679 case NVPTXISD::TexUnified3DFloatFloatLevel:
680 return "NVPTXISD::TexUnified3DFloatFloatLevel";
681 case NVPTXISD::TexUnified3DFloatFloatGrad:
682 return "NVPTXISD::TexUnified3DFloatFloatGrad";
683 case NVPTXISD::TexUnified3DS32S32:
684 return "NVPTXISD::TexUnified3DS32S32";
685 case NVPTXISD::TexUnified3DS32Float:
686 return "NVPTXISD::TexUnified3DS32Float";
687 case NVPTXISD::TexUnified3DS32FloatLevel:
688 return "NVPTXISD::TexUnified3DS32FloatLevel";
689 case NVPTXISD::TexUnified3DS32FloatGrad:
690 return "NVPTXISD::TexUnified3DS32FloatGrad";
691 case NVPTXISD::TexUnified3DU32S32:
692 return "NVPTXISD::TexUnified3DU32S32";
693 case NVPTXISD::TexUnified3DU32Float:
694 return "NVPTXISD::TexUnified3DU32Float";
695 case NVPTXISD::TexUnified3DU32FloatLevel:
696 return "NVPTXISD::TexUnified3DU32FloatLevel";
697 case NVPTXISD::TexUnified3DU32FloatGrad:
698 return "NVPTXISD::TexUnified3DU32FloatGrad";
699 case NVPTXISD::TexUnifiedCubeFloatFloat:
700 return "NVPTXISD::TexUnifiedCubeFloatFloat";
701 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
702 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
703 case NVPTXISD::TexUnifiedCubeS32Float:
704 return "NVPTXISD::TexUnifiedCubeS32Float";
705 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
706 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
707 case NVPTXISD::TexUnifiedCubeU32Float:
708 return "NVPTXISD::TexUnifiedCubeU32Float";
709 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
710 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
711 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
712 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
713 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
714 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
715 case NVPTXISD::TexUnifiedCubeArrayS32Float:
716 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
717 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
718 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
719 case NVPTXISD::TexUnifiedCubeArrayU32Float:
720 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
721 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
722 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
723 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
724 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
725 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
726 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
727 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
728 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
729 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
730 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
731 case NVPTXISD::Tld4UnifiedR2DS64Float:
732 return "NVPTXISD::Tld4UnifiedR2DS64Float";
733 case NVPTXISD::Tld4UnifiedG2DS64Float:
734 return "NVPTXISD::Tld4UnifiedG2DS64Float";
735 case NVPTXISD::Tld4UnifiedB2DS64Float:
736 return "NVPTXISD::Tld4UnifiedB2DS64Float";
737 case NVPTXISD::Tld4UnifiedA2DS64Float:
738 return "NVPTXISD::Tld4UnifiedA2DS64Float";
739 case NVPTXISD::Tld4UnifiedR2DU64Float:
740 return "NVPTXISD::Tld4UnifiedR2DU64Float";
741 case NVPTXISD::Tld4UnifiedG2DU64Float:
742 return "NVPTXISD::Tld4UnifiedG2DU64Float";
743 case NVPTXISD::Tld4UnifiedB2DU64Float:
744 return "NVPTXISD::Tld4UnifiedB2DU64Float";
745 case NVPTXISD::Tld4UnifiedA2DU64Float:
746 return "NVPTXISD::Tld4UnifiedA2DU64Float";
748 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
749 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
750 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
751 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
752 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
753 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
754 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
755 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
756 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
757 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
758 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
760 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
761 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
762 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
763 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
764 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
765 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
766 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
767 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
768 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
769 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
770 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
772 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
773 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
774 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
775 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
776 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
777 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
778 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
779 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
780 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
781 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
782 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
784 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
785 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
786 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
787 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
788 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
789 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
790 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
791 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
792 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
793 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
794 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
796 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
797 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
798 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
799 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
800 case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
801 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
802 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
803 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
804 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
805 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
806 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
808 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
809 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
810 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
811 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
812 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
813 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
814 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
815 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
816 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
817 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
818 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
820 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
821 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
822 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
823 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
824 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
825 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
826 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
827 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
828 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
829 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
830 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
832 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
833 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
834 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
835 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
836 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
837 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
838 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
839 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
840 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
841 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
842 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
844 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
845 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
846 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
847 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
848 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
849 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
850 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
851 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
852 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
853 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
854 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
856 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
857 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
858 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
859 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
860 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
861 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
862 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
863 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
864 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
865 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
866 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
868 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
869 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
870 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
871 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
872 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
873 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
874 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
875 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
876 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
877 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
878 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
880 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
881 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
882 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
883 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
884 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
885 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
886 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
887 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
888 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
889 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
890 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
892 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
893 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
894 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
895 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
896 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
897 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
898 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
899 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
900 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
901 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
902 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
904 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
905 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
906 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
907 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
908 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
909 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
910 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
911 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
912 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
913 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
914 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
916 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
917 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
918 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
919 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
920 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
921 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
922 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
923 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
924 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
925 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
926 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
931 TargetLoweringBase::LegalizeTypeAction
932 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
933 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
934 return TypeSplitVector;
936 return TargetLoweringBase::getPreferredVectorAction(VT);
940 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
942 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
943 auto PtrVT = getPointerTy(DAG.getDataLayout());
944 Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
945 return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
948 std::string NVPTXTargetLowering::getPrototype(
949 const DataLayout &DL, Type *retTy, const ArgListTy &Args,
950 const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
951 const ImmutableCallSite *CS) const {
952 auto PtrVT = getPointerTy(DL);
954 bool isABI = (STI.getSmVersion() >= 20);
955 assert(isABI && "Non-ABI compilation is not supported");
960 O << "prototype_" << uniqueCallSite << " : .callprototype ";
962 if (retTy->getTypeID() == Type::VoidTyID) {
966 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
968 if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
969 size = ITy->getBitWidth();
973 assert(retTy->isFloatingPointTy() &&
974 "Floating point type expected here");
975 size = retTy->getPrimitiveSizeInBits();
978 O << ".param .b" << size << " _";
979 } else if (isa<PointerType>(retTy)) {
980 O << ".param .b" << PtrVT.getSizeInBits() << " _";
981 } else if ((retTy->getTypeID() == Type::StructTyID) ||
982 isa<VectorType>(retTy)) {
983 auto &DL = CS->getCalledFunction()->getParent()->getDataLayout();
984 O << ".param .align " << retAlignment << " .b8 _["
985 << DL.getTypeAllocSize(retTy) << "]";
987 llvm_unreachable("Unknown return type");
996 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
997 Type *Ty = Args[i].Ty;
1003 if (!Outs[OIdx].Flags.isByVal()) {
1004 if (Ty->isAggregateType() || Ty->isVectorTy()) {
1006 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
1007 // +1 because index 0 is reserved for return type alignment
1008 if (!getAlign(*CallI, i + 1, align))
1009 align = DL.getABITypeAlignment(Ty);
1010 unsigned sz = DL.getTypeAllocSize(Ty);
1011 O << ".param .align " << align << " .b8 ";
1013 O << "[" << sz << "]";
1014 // update the index for Outs
1015 SmallVector<EVT, 16> vtparts;
1016 ComputeValueVTs(*this, DL, Ty, vtparts);
1017 if (unsigned len = vtparts.size())
1021 // i8 types in IR will be i16 types in SDAG
1022 assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
1023 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
1024 "type mismatch between callee prototype and arguments");
1027 if (isa<IntegerType>(Ty)) {
1028 sz = cast<IntegerType>(Ty)->getBitWidth();
1031 } else if (isa<PointerType>(Ty))
1032 sz = PtrVT.getSizeInBits();
1034 sz = Ty->getPrimitiveSizeInBits();
1035 O << ".param .b" << sz << " ";
1039 auto *PTy = dyn_cast<PointerType>(Ty);
1040 assert(PTy && "Param with byval attribute should be a pointer type");
1041 Type *ETy = PTy->getElementType();
1043 unsigned align = Outs[OIdx].Flags.getByValAlign();
1044 unsigned sz = DL.getTypeAllocSize(ETy);
1045 O << ".param .align " << align << " .b8 ";
1047 O << "[" << sz << "]";
1053 unsigned NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1054 const ImmutableCallSite *CS,
1055 Type *Ty, unsigned Idx,
1056 const DataLayout &DL) const {
1058 // CallSite is zero, fallback to ABI type alignment
1059 return DL.getABITypeAlignment(Ty);
1063 const Value *DirectCallee = CS->getCalledFunction();
1065 if (!DirectCallee) {
1066 // We don't have a direct function symbol, but that may be because of
1067 // constant cast instructions in the call.
1068 const Instruction *CalleeI = CS->getInstruction();
1069 assert(CalleeI && "Call target is not a function or derived value?");
1071 // With bitcast'd call targets, the instruction will be the call
1072 if (isa<CallInst>(CalleeI)) {
1073 // Check if we have call alignment metadata
1074 if (getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1077 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1078 // Ignore any bitcast instructions
1079 while (isa<ConstantExpr>(CalleeV)) {
1080 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1083 // Look through the bitcast
1084 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1087 // We have now looked past all of the bitcasts. Do we finally have a
1089 if (isa<Function>(CalleeV))
1090 DirectCallee = CalleeV;
1094 // Check for function alignment information if we found that the
1095 // ultimate target is a Function
1097 if (getAlign(*cast<Function>(DirectCallee), Idx, Align))
1100 // Call is indirect or alignment information is not available, fall back to
1101 // the ABI type alignment
1102 return DL.getABITypeAlignment(Ty);
1105 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1106 SmallVectorImpl<SDValue> &InVals) const {
1107 SelectionDAG &DAG = CLI.DAG;
1109 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1110 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1111 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1112 SDValue Chain = CLI.Chain;
1113 SDValue Callee = CLI.Callee;
1114 bool &isTailCall = CLI.IsTailCall;
1115 ArgListTy &Args = CLI.getArgs();
1116 Type *retTy = CLI.RetTy;
1117 ImmutableCallSite *CS = CLI.CS;
1119 bool isABI = (STI.getSmVersion() >= 20);
1120 assert(isABI && "Non-ABI compilation is not supported");
1123 MachineFunction &MF = DAG.getMachineFunction();
1124 const Function *F = MF.getFunction();
1125 auto &DL = MF.getDataLayout();
1127 SDValue tempChain = Chain;
1128 Chain = DAG.getCALLSEQ_START(Chain,
1129 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1131 SDValue InFlag = Chain.getValue(1);
1133 unsigned paramCount = 0;
1134 // Args.size() and Outs.size() need not match.
1135 // Outs.size() will be larger
1136 // * if there is an aggregate argument with multiple fields (each field
1137 // showing up separately in Outs)
1138 // * if there is a vector argument with more than typical vector-length
1139 // elements (generally if more than 4) where each vector element is
1140 // individually present in Outs.
1141 // So a different index should be used for indexing into Outs/OutVals.
1142 // See similar issue in LowerFormalArguments.
1144 // Declare the .params or .reg need to pass values
1146 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1147 EVT VT = Outs[OIdx].VT;
1148 Type *Ty = Args[i].Ty;
1150 if (!Outs[OIdx].Flags.isByVal()) {
1151 if (Ty->isAggregateType()) {
1153 SmallVector<EVT, 16> vtparts;
1154 SmallVector<uint64_t, 16> Offsets;
1155 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &Offsets,
1159 getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1160 // declare .param .align <align> .b8 .param<n>[<size>];
1161 unsigned sz = DL.getTypeAllocSize(Ty);
1162 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1163 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
1165 DAG.getConstant(paramCount, dl, MVT::i32),
1166 DAG.getConstant(sz, dl, MVT::i32),
1168 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1170 InFlag = Chain.getValue(1);
1171 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1172 EVT elemtype = vtparts[j];
1173 unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
1174 if (elemtype.isInteger() && (sz < 8))
1176 SDValue StVal = OutVals[OIdx];
1177 if (elemtype.getSizeInBits() < 16) {
1178 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1180 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1181 SDValue CopyParamOps[] = { Chain,
1182 DAG.getConstant(paramCount, dl, MVT::i32),
1183 DAG.getConstant(Offsets[j], dl, MVT::i32),
1185 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1186 CopyParamVTs, CopyParamOps,
1187 elemtype, MachinePointerInfo(),
1189 InFlag = Chain.getValue(1);
1192 if (vtparts.size() > 0)
1197 if (Ty->isVectorTy()) {
1198 EVT ObjectVT = getValueType(DL, Ty);
1200 getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1201 // declare .param .align <align> .b8 .param<n>[<size>];
1202 unsigned sz = DL.getTypeAllocSize(Ty);
1203 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1204 SDValue DeclareParamOps[] = { Chain,
1205 DAG.getConstant(align, dl, MVT::i32),
1206 DAG.getConstant(paramCount, dl, MVT::i32),
1207 DAG.getConstant(sz, dl, MVT::i32),
1209 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1211 InFlag = Chain.getValue(1);
1212 unsigned NumElts = ObjectVT.getVectorNumElements();
1213 EVT EltVT = ObjectVT.getVectorElementType();
1215 bool NeedExtend = false;
1216 if (EltVT.getSizeInBits() < 16) {
1223 SDValue Elt = OutVals[OIdx++];
1225 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
1227 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1228 SDValue CopyParamOps[] = { Chain,
1229 DAG.getConstant(paramCount, dl, MVT::i32),
1230 DAG.getConstant(0, dl, MVT::i32), Elt,
1232 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1233 CopyParamVTs, CopyParamOps,
1234 MemVT, MachinePointerInfo());
1235 InFlag = Chain.getValue(1);
1236 } else if (NumElts == 2) {
1237 SDValue Elt0 = OutVals[OIdx++];
1238 SDValue Elt1 = OutVals[OIdx++];
1240 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
1241 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
1244 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1245 SDValue CopyParamOps[] = { Chain,
1246 DAG.getConstant(paramCount, dl, MVT::i32),
1247 DAG.getConstant(0, dl, MVT::i32), Elt0,
1249 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
1250 CopyParamVTs, CopyParamOps,
1251 MemVT, MachinePointerInfo());
1252 InFlag = Chain.getValue(1);
1254 unsigned curOffset = 0;
1256 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1258 // vector will be expanded to a power of 2 elements, so we know we can
1259 // always round up to the next multiple of 4 when creating the vector
1261 // e.g. 4 elem => 1 st.v4
1262 // 6 elem => 2 st.v4
1263 // 8 elem => 2 st.v4
1264 // 11 elem => 3 st.v4
1265 unsigned VecSize = 4;
1266 if (EltVT.getSizeInBits() == 64)
1269 // This is potentially only part of a vector, so assume all elements
1270 // are packed together.
1271 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
1273 for (unsigned i = 0; i < NumElts; i += VecSize) {
1276 SmallVector<SDValue, 8> Ops;
1277 Ops.push_back(Chain);
1278 Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1279 Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32));
1281 unsigned Opc = NVPTXISD::StoreParamV2;
1283 StoreVal = OutVals[OIdx++];
1285 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1286 Ops.push_back(StoreVal);
1288 if (i + 1 < NumElts) {
1289 StoreVal = OutVals[OIdx++];
1292 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1294 StoreVal = DAG.getUNDEF(EltVT);
1296 Ops.push_back(StoreVal);
1299 Opc = NVPTXISD::StoreParamV4;
1300 if (i + 2 < NumElts) {
1301 StoreVal = OutVals[OIdx++];
1304 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1306 StoreVal = DAG.getUNDEF(EltVT);
1308 Ops.push_back(StoreVal);
1310 if (i + 3 < NumElts) {
1311 StoreVal = OutVals[OIdx++];
1314 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1316 StoreVal = DAG.getUNDEF(EltVT);
1318 Ops.push_back(StoreVal);
1321 Ops.push_back(InFlag);
1323 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1324 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1325 MemVT, MachinePointerInfo());
1326 InFlag = Chain.getValue(1);
1327 curOffset += PerStoreOffset;
1335 // for ABI, declare .param .b<size> .param<n>;
1336 unsigned sz = VT.getSizeInBits();
1337 bool needExtend = false;
1338 if (VT.isInteger()) {
1344 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1345 SDValue DeclareParamOps[] = { Chain,
1346 DAG.getConstant(paramCount, dl, MVT::i32),
1347 DAG.getConstant(sz, dl, MVT::i32),
1348 DAG.getConstant(0, dl, MVT::i32), InFlag };
1349 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1351 InFlag = Chain.getValue(1);
1352 SDValue OutV = OutVals[OIdx];
1354 // zext/sext i1 to i16
1355 unsigned opc = ISD::ZERO_EXTEND;
1356 if (Outs[OIdx].Flags.isSExt())
1357 opc = ISD::SIGN_EXTEND;
1358 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
1360 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1361 SDValue CopyParamOps[] = { Chain,
1362 DAG.getConstant(paramCount, dl, MVT::i32),
1363 DAG.getConstant(0, dl, MVT::i32), OutV,
1366 unsigned opcode = NVPTXISD::StoreParam;
1367 if (Outs[OIdx].Flags.isZExt() && VT.getSizeInBits() < 32)
1368 opcode = NVPTXISD::StoreParamU32;
1369 else if (Outs[OIdx].Flags.isSExt() && VT.getSizeInBits() < 32)
1370 opcode = NVPTXISD::StoreParamS32;
1371 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
1372 VT, MachinePointerInfo());
1374 InFlag = Chain.getValue(1);
1379 SmallVector<EVT, 16> vtparts;
1380 SmallVector<uint64_t, 16> Offsets;
1381 auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
1382 assert(PTy && "Type of a byval parameter should be pointer");
1383 ComputePTXValueVTs(*this, DAG.getDataLayout(), PTy->getElementType(),
1384 vtparts, &Offsets, 0);
1386 // declare .param .align <align> .b8 .param<n>[<size>];
1387 unsigned sz = Outs[OIdx].Flags.getByValSize();
1388 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1389 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1390 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1391 // so we don't need to worry about natural alignment or not.
1392 // See TargetLowering::LowerCallTo().
1394 // Enforce minumum alignment of 4 to work around ptxas miscompile
1395 // for sm_50+. See corresponding alignment adjustment in
1396 // emitFunctionParamList() for details.
1399 SDValue DeclareParamOps[] = {Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1400 DAG.getConstant(paramCount, dl, MVT::i32),
1401 DAG.getConstant(sz, dl, MVT::i32), InFlag};
1402 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1404 InFlag = Chain.getValue(1);
1405 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1406 EVT elemtype = vtparts[j];
1407 int curOffset = Offsets[j];
1408 unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1409 auto PtrVT = getPointerTy(DAG.getDataLayout());
1410 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1411 DAG.getConstant(curOffset, dl, PtrVT));
1412 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1413 MachinePointerInfo(), PartAlign);
1414 if (elemtype.getSizeInBits() < 16) {
1415 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1417 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1418 SDValue CopyParamOps[] = { Chain,
1419 DAG.getConstant(paramCount, dl, MVT::i32),
1420 DAG.getConstant(curOffset, dl, MVT::i32),
1422 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1423 CopyParamOps, elemtype,
1424 MachinePointerInfo());
1426 InFlag = Chain.getValue(1);
1431 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1432 unsigned retAlignment = 0;
1435 if (Ins.size() > 0) {
1436 SmallVector<EVT, 16> resvtparts;
1437 ComputeValueVTs(*this, DL, retTy, resvtparts);
1440 // .param .align 16 .b8 retval0[<size-in-bytes>], or
1441 // .param .b<size-in-bits> retval0
1442 unsigned resultsz = DL.getTypeAllocSizeInBits(retTy);
1443 // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1444 // these three types to match the logic in
1445 // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1446 // Plus, this behavior is consistent with nvcc's.
1447 if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
1448 retTy->isPointerTy()) {
1449 // Scalar needs to be at least 32bit wide
1452 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1453 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1454 DAG.getConstant(resultsz, dl, MVT::i32),
1455 DAG.getConstant(0, dl, MVT::i32), InFlag };
1456 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1458 InFlag = Chain.getValue(1);
1460 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0, DL);
1461 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1462 SDValue DeclareRetOps[] = { Chain,
1463 DAG.getConstant(retAlignment, dl, MVT::i32),
1464 DAG.getConstant(resultsz / 8, dl, MVT::i32),
1465 DAG.getConstant(0, dl, MVT::i32), InFlag };
1466 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1468 InFlag = Chain.getValue(1);
1473 // This is indirect function call case : PTX requires a prototype of the
1475 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1476 // to be emitted, and the label has to used as the last arg of call
1478 // The prototype is embedded in a string and put as the operand for a
1479 // CallPrototype SDNode which will print out to the value of the string.
1480 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1482 getPrototype(DAG.getDataLayout(), retTy, Args, Outs, retAlignment, CS);
1483 const char *ProtoStr =
1484 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1485 SDValue ProtoOps[] = {
1486 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1488 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1489 InFlag = Chain.getValue(1);
1491 // Op to just print "call"
1492 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1493 SDValue PrintCallOps[] = {
1494 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1496 // We model convergent calls as separate opcodes.
1497 unsigned Opcode = Func ? NVPTXISD::PrintCallUni : NVPTXISD::PrintCall;
1498 if (CLI.IsConvergent)
1499 Opcode = Opcode == NVPTXISD::PrintCallUni ? NVPTXISD::PrintConvergentCallUni
1500 : NVPTXISD::PrintConvergentCall;
1501 Chain = DAG.getNode(Opcode, dl, PrintCallVTs, PrintCallOps);
1502 InFlag = Chain.getValue(1);
1504 // Ops to print out the function name
1505 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1506 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1507 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1508 InFlag = Chain.getValue(1);
1510 // Ops to print out the param list
1511 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1512 SDValue CallArgBeginOps[] = { Chain, InFlag };
1513 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1515 InFlag = Chain.getValue(1);
1517 for (unsigned i = 0, e = paramCount; i != e; ++i) {
1520 opcode = NVPTXISD::LastCallArg;
1522 opcode = NVPTXISD::CallArg;
1523 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1524 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1525 DAG.getConstant(i, dl, MVT::i32), InFlag };
1526 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1527 InFlag = Chain.getValue(1);
1529 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1530 SDValue CallArgEndOps[] = { Chain,
1531 DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1533 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1534 InFlag = Chain.getValue(1);
1537 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1538 SDValue PrototypeOps[] = { Chain,
1539 DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1541 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1542 InFlag = Chain.getValue(1);
1545 // Generate loads from param memory/moves from registers for result
1546 if (Ins.size() > 0) {
1547 if (retTy && retTy->isVectorTy()) {
1548 EVT ObjectVT = getValueType(DL, retTy);
1549 unsigned NumElts = ObjectVT.getVectorNumElements();
1550 EVT EltVT = ObjectVT.getVectorElementType();
1551 assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
1552 ObjectVT) == NumElts &&
1553 "Vector was not scalarized");
1554 unsigned sz = EltVT.getSizeInBits();
1555 bool needTruncate = sz < 8;
1558 // Just a simple load
1559 SmallVector<EVT, 4> LoadRetVTs;
1560 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1561 // If loading i1/i8 result, generate
1565 LoadRetVTs.push_back(MVT::i16);
1567 LoadRetVTs.push_back(EltVT);
1568 LoadRetVTs.push_back(MVT::Other);
1569 LoadRetVTs.push_back(MVT::Glue);
1570 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1571 DAG.getConstant(0, dl, MVT::i32), InFlag};
1572 SDValue retval = DAG.getMemIntrinsicNode(
1573 NVPTXISD::LoadParam, dl,
1574 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1575 Chain = retval.getValue(1);
1576 InFlag = retval.getValue(2);
1577 SDValue Ret0 = retval;
1579 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1580 InVals.push_back(Ret0);
1581 } else if (NumElts == 2) {
1583 SmallVector<EVT, 4> LoadRetVTs;
1584 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1585 // If loading i1/i8 result, generate
1589 LoadRetVTs.push_back(MVT::i16);
1590 LoadRetVTs.push_back(MVT::i16);
1592 LoadRetVTs.push_back(EltVT);
1593 LoadRetVTs.push_back(EltVT);
1595 LoadRetVTs.push_back(MVT::Other);
1596 LoadRetVTs.push_back(MVT::Glue);
1597 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1598 DAG.getConstant(0, dl, MVT::i32), InFlag};
1599 SDValue retval = DAG.getMemIntrinsicNode(
1600 NVPTXISD::LoadParamV2, dl,
1601 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1602 Chain = retval.getValue(2);
1603 InFlag = retval.getValue(3);
1604 SDValue Ret0 = retval.getValue(0);
1605 SDValue Ret1 = retval.getValue(1);
1607 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1608 InVals.push_back(Ret0);
1609 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1610 InVals.push_back(Ret1);
1612 InVals.push_back(Ret0);
1613 InVals.push_back(Ret1);
1616 // Split into N LoadV4
1618 unsigned VecSize = 4;
1619 unsigned Opc = NVPTXISD::LoadParamV4;
1620 if (EltVT.getSizeInBits() == 64) {
1622 Opc = NVPTXISD::LoadParamV2;
1624 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1625 for (unsigned i = 0; i < NumElts; i += VecSize) {
1626 SmallVector<EVT, 8> LoadRetVTs;
1627 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1628 // If loading i1/i8 result, generate
1632 for (unsigned j = 0; j < VecSize; ++j)
1633 LoadRetVTs.push_back(MVT::i16);
1635 for (unsigned j = 0; j < VecSize; ++j)
1636 LoadRetVTs.push_back(EltVT);
1638 LoadRetVTs.push_back(MVT::Other);
1639 LoadRetVTs.push_back(MVT::Glue);
1640 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1641 DAG.getConstant(Ofst, dl, MVT::i32), InFlag};
1642 SDValue retval = DAG.getMemIntrinsicNode(
1643 Opc, dl, DAG.getVTList(LoadRetVTs),
1644 LoadRetOps, EltVT, MachinePointerInfo());
1646 Chain = retval.getValue(2);
1647 InFlag = retval.getValue(3);
1649 Chain = retval.getValue(4);
1650 InFlag = retval.getValue(5);
1653 for (unsigned j = 0; j < VecSize; ++j) {
1654 if (i + j >= NumElts)
1656 SDValue Elt = retval.getValue(j);
1658 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1659 InVals.push_back(Elt);
1661 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1665 SmallVector<EVT, 16> VTs;
1666 SmallVector<uint64_t, 16> Offsets;
1667 auto &DL = DAG.getDataLayout();
1668 ComputePTXValueVTs(*this, DL, retTy, VTs, &Offsets, 0);
1669 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1670 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0, DL);
1671 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1672 unsigned sz = VTs[i].getSizeInBits();
1673 unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1674 bool needTruncate = false;
1675 if (VTs[i].isInteger() && sz < 8) {
1677 needTruncate = true;
1680 SmallVector<EVT, 4> LoadRetVTs;
1681 EVT TheLoadType = VTs[i];
1682 if (retTy->isIntegerTy() && DL.getTypeAllocSizeInBits(retTy) < 32) {
1683 // This is for integer types only, and specifically not for
1685 LoadRetVTs.push_back(MVT::i32);
1686 TheLoadType = MVT::i32;
1687 needTruncate = true;
1688 } else if (sz < 16) {
1689 // If loading i1/i8 result, generate
1691 // trunc i16 to i1/i8
1693 // FIXME: Do we need to set needTruncate to true here, too? We could
1694 // not figure out what this branch is for in D17872, so we left it
1695 // alone. The comment above about loading i1/i8 may be wrong, as the
1696 // branch above seems to cover integers of size < 32.
1697 LoadRetVTs.push_back(MVT::i16);
1699 LoadRetVTs.push_back(Ins[i].VT);
1700 LoadRetVTs.push_back(MVT::Other);
1701 LoadRetVTs.push_back(MVT::Glue);
1703 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1704 DAG.getConstant(Offsets[i], dl, MVT::i32),
1706 SDValue retval = DAG.getMemIntrinsicNode(
1707 NVPTXISD::LoadParam, dl,
1708 DAG.getVTList(LoadRetVTs), LoadRetOps,
1709 TheLoadType, MachinePointerInfo(), AlignI);
1710 Chain = retval.getValue(1);
1711 InFlag = retval.getValue(2);
1712 SDValue Ret0 = retval.getValue(0);
1714 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1715 InVals.push_back(Ret0);
1720 Chain = DAG.getCALLSEQ_END(Chain,
1721 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1722 DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1727 // set isTailCall to false for now, until we figure out how to express
1728 // tail call optimization in PTX
1733 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1734 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1735 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1737 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1738 SDNode *Node = Op.getNode();
1740 SmallVector<SDValue, 8> Ops;
1741 unsigned NumOperands = Node->getNumOperands();
1742 for (unsigned i = 0; i < NumOperands; ++i) {
1743 SDValue SubOp = Node->getOperand(i);
1744 EVT VVT = SubOp.getNode()->getValueType(0);
1745 EVT EltVT = VVT.getVectorElementType();
1746 unsigned NumSubElem = VVT.getVectorNumElements();
1747 for (unsigned j = 0; j < NumSubElem; ++j) {
1748 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1749 DAG.getIntPtrConstant(j, dl)));
1752 return DAG.getBuildVector(Node->getValueType(0), dl, Ops);
1755 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1756 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1758 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1760 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1761 SelectionDAG &DAG) const {
1762 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1763 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1765 EVT VT = Op.getValueType();
1766 unsigned VTBits = VT.getSizeInBits();
1768 SDValue ShOpLo = Op.getOperand(0);
1769 SDValue ShOpHi = Op.getOperand(1);
1770 SDValue ShAmt = Op.getOperand(2);
1771 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1773 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1774 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1775 // {dHi, dLo} = {aHi, aLo} >> Amt
1777 // dLo = shf.r.clamp aLo, aHi, Amt
1779 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1780 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1783 SDValue Ops[2] = { Lo, Hi };
1784 return DAG.getMergeValues(Ops, dl);
1787 // {dHi, dLo} = {aHi, aLo} >> Amt
1788 // - if (Amt>=size) then
1789 // dLo = aHi >> (Amt-size)
1790 // dHi = aHi >> Amt (this is either all 0 or all 1)
1792 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1795 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1796 DAG.getConstant(VTBits, dl, MVT::i32),
1798 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1799 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1800 DAG.getConstant(VTBits, dl, MVT::i32));
1801 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1802 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1803 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1805 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1806 DAG.getConstant(VTBits, dl, MVT::i32),
1808 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1809 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1811 SDValue Ops[2] = { Lo, Hi };
1812 return DAG.getMergeValues(Ops, dl);
1816 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1817 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1819 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1821 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1822 SelectionDAG &DAG) const {
1823 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1824 assert(Op.getOpcode() == ISD::SHL_PARTS);
1826 EVT VT = Op.getValueType();
1827 unsigned VTBits = VT.getSizeInBits();
1829 SDValue ShOpLo = Op.getOperand(0);
1830 SDValue ShOpHi = Op.getOperand(1);
1831 SDValue ShAmt = Op.getOperand(2);
1833 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1834 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1835 // {dHi, dLo} = {aHi, aLo} << Amt
1836 // dHi = shf.l.clamp aLo, aHi, Amt
1839 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1841 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1843 SDValue Ops[2] = { Lo, Hi };
1844 return DAG.getMergeValues(Ops, dl);
1847 // {dHi, dLo} = {aHi, aLo} << Amt
1848 // - if (Amt>=size) then
1849 // dLo = aLo << Amt (all 0)
1850 // dLo = aLo << (Amt-size)
1853 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1855 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1856 DAG.getConstant(VTBits, dl, MVT::i32),
1858 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1859 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1860 DAG.getConstant(VTBits, dl, MVT::i32));
1861 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1862 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1863 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1865 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1866 DAG.getConstant(VTBits, dl, MVT::i32),
1868 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1869 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1871 SDValue Ops[2] = { Lo, Hi };
1872 return DAG.getMergeValues(Ops, dl);
1877 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1878 switch (Op.getOpcode()) {
1879 case ISD::RETURNADDR:
1881 case ISD::FRAMEADDR:
1883 case ISD::GlobalAddress:
1884 return LowerGlobalAddress(Op, DAG);
1885 case ISD::INTRINSIC_W_CHAIN:
1887 case ISD::BUILD_VECTOR:
1888 case ISD::EXTRACT_SUBVECTOR:
1890 case ISD::CONCAT_VECTORS:
1891 return LowerCONCAT_VECTORS(Op, DAG);
1893 return LowerSTORE(Op, DAG);
1895 return LowerLOAD(Op, DAG);
1896 case ISD::SHL_PARTS:
1897 return LowerShiftLeftParts(Op, DAG);
1898 case ISD::SRA_PARTS:
1899 case ISD::SRL_PARTS:
1900 return LowerShiftRightParts(Op, DAG);
1902 return LowerSelect(Op, DAG);
1904 llvm_unreachable("Custom lowering not defined for operation");
1908 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
1909 SDValue Op0 = Op->getOperand(0);
1910 SDValue Op1 = Op->getOperand(1);
1911 SDValue Op2 = Op->getOperand(2);
1912 SDLoc DL(Op.getNode());
1914 assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
1916 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
1917 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
1918 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
1919 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
1924 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1925 if (Op.getValueType() == MVT::i1)
1926 return LowerLOADi1(Op, DAG);
1933 // v1 = ld i8* addr (-> i16)
1934 // v = trunc i16 to i1
1935 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
1936 SDNode *Node = Op.getNode();
1937 LoadSDNode *LD = cast<LoadSDNode>(Node);
1939 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
1940 assert(Node->getValueType(0) == MVT::i1 &&
1941 "Custom lowering for i1 load only");
1942 SDValue newLD = DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
1943 LD->getPointerInfo(), LD->getAlignment(),
1944 LD->getMemOperand()->getFlags());
1945 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1946 // The legalizer (the caller) is expecting two values from the legalized
1947 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1948 // in LegalizeDAG.cpp which also uses MergeValues.
1949 SDValue Ops[] = { result, LD->getChain() };
1950 return DAG.getMergeValues(Ops, dl);
1953 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1954 EVT ValVT = Op.getOperand(1).getValueType();
1955 if (ValVT == MVT::i1)
1956 return LowerSTOREi1(Op, DAG);
1957 else if (ValVT.isVector())
1958 return LowerSTOREVector(Op, DAG);
1964 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1965 SDNode *N = Op.getNode();
1966 SDValue Val = N->getOperand(1);
1968 EVT ValVT = Val.getValueType();
1970 if (ValVT.isVector()) {
1971 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1972 // legal. We can (and should) split that into 2 stores of <2 x double> here
1973 // but I'm leaving that as a TODO for now.
1974 if (!ValVT.isSimple())
1976 switch (ValVT.getSimpleVT().SimpleTy) {
1989 // This is a "native" vector type
1993 MemSDNode *MemSD = cast<MemSDNode>(N);
1994 const DataLayout &TD = DAG.getDataLayout();
1996 unsigned Align = MemSD->getAlignment();
1997 unsigned PrefAlign =
1998 TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
1999 if (Align < PrefAlign) {
2000 // This store is not sufficiently aligned, so bail out and let this vector
2001 // store be scalarized. Note that we may still be able to emit smaller
2002 // vector stores. For example, if we are storing a <4 x float> with an
2003 // alignment of 8, this check will fail but the legalizer will try again
2004 // with 2 x <2 x float>, which will succeed with an alignment of 8.
2008 unsigned Opcode = 0;
2009 EVT EltVT = ValVT.getVectorElementType();
2010 unsigned NumElts = ValVT.getVectorNumElements();
2012 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
2013 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
2014 // stored type to i16 and propagate the "real" type as the memory type.
2015 bool NeedExt = false;
2016 if (EltVT.getSizeInBits() < 16)
2023 Opcode = NVPTXISD::StoreV2;
2026 Opcode = NVPTXISD::StoreV4;
2030 SmallVector<SDValue, 8> Ops;
2032 // First is the chain
2033 Ops.push_back(N->getOperand(0));
2035 // Then the split values
2036 for (unsigned i = 0; i < NumElts; ++i) {
2037 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
2038 DAG.getIntPtrConstant(i, DL));
2040 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
2041 Ops.push_back(ExtVal);
2044 // Then any remaining arguments
2045 Ops.append(N->op_begin() + 2, N->op_end());
2047 SDValue NewSt = DAG.getMemIntrinsicNode(
2048 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
2049 MemSD->getMemoryVT(), MemSD->getMemOperand());
2051 //return DCI.CombineTo(N, NewSt, true);
2060 // v1 = zxt v to i16
2062 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
2063 SDNode *Node = Op.getNode();
2065 StoreSDNode *ST = cast<StoreSDNode>(Node);
2066 SDValue Tmp1 = ST->getChain();
2067 SDValue Tmp2 = ST->getBasePtr();
2068 SDValue Tmp3 = ST->getValue();
2069 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2070 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2072 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8,
2073 ST->getAlignment(), ST->getMemOperand()->getFlags());
2078 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2079 std::string ParamSym;
2080 raw_string_ostream ParamStr(ParamSym);
2082 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2085 std::string *SavedStr =
2086 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2087 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2090 // Check to see if the kernel argument is image*_t or sampler_t
2092 static bool isImageOrSamplerVal(const Value *arg, const Module *context) {
2093 static const char *const specialTypes[] = { "struct._image2d_t",
2094 "struct._image3d_t",
2095 "struct._sampler_t" };
2097 Type *Ty = arg->getType();
2098 auto *PTy = dyn_cast<PointerType>(Ty);
2106 auto *STy = dyn_cast<StructType>(PTy->getElementType());
2107 if (!STy || STy->isLiteral())
2110 return std::find(std::begin(specialTypes), std::end(specialTypes),
2111 STy->getName()) != std::end(specialTypes);
2114 SDValue NVPTXTargetLowering::LowerFormalArguments(
2115 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2116 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2117 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2118 MachineFunction &MF = DAG.getMachineFunction();
2119 const DataLayout &DL = DAG.getDataLayout();
2120 auto PtrVT = getPointerTy(DAG.getDataLayout());
2122 const Function *F = MF.getFunction();
2123 const AttributeSet &PAL = F->getAttributes();
2124 const TargetLowering *TLI = STI.getTargetLowering();
2126 SDValue Root = DAG.getRoot();
2127 std::vector<SDValue> OutChains;
2129 bool isABI = (STI.getSmVersion() >= 20);
2130 assert(isABI && "Non-ABI compilation is not supported");
2134 std::vector<Type *> argTypes;
2135 std::vector<const Argument *> theArgs;
2136 for (const Argument &I : F->args()) {
2137 theArgs.push_back(&I);
2138 argTypes.push_back(I.getType());
2140 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2141 // Ins.size() will be larger
2142 // * if there is an aggregate argument with multiple fields (each field
2143 // showing up separately in Ins)
2144 // * if there is a vector argument with more than typical vector-length
2145 // elements (generally if more than 4) where each vector element is
2146 // individually present in Ins.
2147 // So a different index should be used for indexing into Ins.
2148 // See similar issue in LowerCall.
2149 unsigned InsIdx = 0;
2152 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2153 Type *Ty = argTypes[i];
2155 // If the kernel argument is image*_t or sampler_t, convert it to
2156 // a i32 constant holding the parameter position. This can later
2157 // matched in the AsmPrinter to output the correct mangled name.
2158 if (isImageOrSamplerVal(
2160 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2162 assert(isKernelFunction(*F) &&
2163 "Only kernels can have image/sampler params");
2164 InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2168 if (theArgs[i]->use_empty()) {
2170 if (Ty->isAggregateType()) {
2171 SmallVector<EVT, 16> vtparts;
2173 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2174 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2175 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2177 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2180 if (vtparts.size() > 0)
2184 if (Ty->isVectorTy()) {
2185 EVT ObjectVT = getValueType(DL, Ty);
2186 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2187 for (unsigned parti = 0; parti < NumRegs; ++parti) {
2188 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2195 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2199 // In the following cases, assign a node order of "idx+1"
2200 // to newly created nodes. The SDNodes for params have to
2201 // appear in the same order as their order of appearance
2202 // in the original function. "idx+1" holds that order.
2203 if (!PAL.hasAttribute(i + 1, Attribute::ByVal)) {
2204 if (Ty->isAggregateType()) {
2205 SmallVector<EVT, 16> vtparts;
2206 SmallVector<uint64_t, 16> offsets;
2208 // NOTE: Here, we lose the ability to issue vector loads for vectors
2209 // that are a part of a struct. This should be investigated in the
2211 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &offsets,
2213 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2214 bool aggregateIsPacked = false;
2215 if (StructType *STy = dyn_cast<StructType>(Ty))
2216 aggregateIsPacked = STy->isPacked();
2218 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2219 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2221 EVT partVT = vtparts[parti];
2222 Value *srcValue = Constant::getNullValue(
2223 PointerType::get(partVT.getTypeForEVT(F->getContext()),
2224 ADDRESS_SPACE_PARAM));
2226 DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2227 DAG.getConstant(offsets[parti], dl, PtrVT));
2228 unsigned partAlign = aggregateIsPacked
2230 : DL.getABITypeAlignment(
2231 partVT.getTypeForEVT(F->getContext()));
2233 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
2234 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2235 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2236 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2237 MachinePointerInfo(srcValue), partVT, partAlign);
2239 p = DAG.getLoad(partVT, dl, Root, srcAddr,
2240 MachinePointerInfo(srcValue), partAlign);
2243 p.getNode()->setIROrder(idx + 1);
2244 InVals.push_back(p);
2247 if (vtparts.size() > 0)
2251 if (Ty->isVectorTy()) {
2252 EVT ObjectVT = getValueType(DL, Ty);
2253 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2254 unsigned NumElts = ObjectVT.getVectorNumElements();
2255 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
2256 "Vector was not scalarized");
2257 EVT EltVT = ObjectVT.getVectorElementType();
2262 // We only have one element, so just directly load it
2263 Value *SrcValue = Constant::getNullValue(PointerType::get(
2264 EltVT.getTypeForEVT(F->getContext()), ADDRESS_SPACE_PARAM));
2265 SDValue P = DAG.getLoad(
2266 EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue),
2267 DL.getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())),
2268 MachineMemOperand::MODereferenceable |
2269 MachineMemOperand::MOInvariant);
2271 P.getNode()->setIROrder(idx + 1);
2273 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2274 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
2275 InVals.push_back(P);
2277 } else if (NumElts == 2) {
2279 // f32,f32 = load ...
2280 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
2281 Value *SrcValue = Constant::getNullValue(PointerType::get(
2282 VecVT.getTypeForEVT(F->getContext()), ADDRESS_SPACE_PARAM));
2283 SDValue P = DAG.getLoad(
2284 VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue),
2285 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())),
2286 MachineMemOperand::MODereferenceable |
2287 MachineMemOperand::MOInvariant);
2289 P.getNode()->setIROrder(idx + 1);
2291 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2292 DAG.getIntPtrConstant(0, dl));
2293 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2294 DAG.getIntPtrConstant(1, dl));
2296 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
2297 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
2298 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
2301 InVals.push_back(Elt0);
2302 InVals.push_back(Elt1);
2306 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
2307 // the vector will be expanded to a power of 2 elements, so we know we
2308 // can always round up to the next multiple of 4 when creating the
2310 // e.g. 4 elem => 1 ld.v4
2311 // 6 elem => 2 ld.v4
2312 // 8 elem => 2 ld.v4
2313 // 11 elem => 3 ld.v4
2314 unsigned VecSize = 4;
2315 if (EltVT.getSizeInBits() == 64) {
2318 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2320 for (unsigned i = 0; i < NumElts; i += VecSize) {
2321 Value *SrcValue = Constant::getNullValue(
2322 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
2323 ADDRESS_SPACE_PARAM));
2324 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2325 DAG.getConstant(Ofst, dl, PtrVT));
2326 SDValue P = DAG.getLoad(
2327 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue),
2328 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())),
2329 MachineMemOperand::MODereferenceable |
2330 MachineMemOperand::MOInvariant);
2332 P.getNode()->setIROrder(idx + 1);
2334 for (unsigned j = 0; j < VecSize; ++j) {
2335 if (i + j >= NumElts)
2337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2338 DAG.getIntPtrConstant(j, dl));
2339 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2340 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
2341 InVals.push_back(Elt);
2343 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2353 EVT ObjectVT = getValueType(DL, Ty);
2354 // If ABI, load from the param symbol
2355 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2356 Value *srcValue = Constant::getNullValue(PointerType::get(
2357 ObjectVT.getTypeForEVT(F->getContext()), ADDRESS_SPACE_PARAM));
2359 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2360 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2361 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2363 ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue),
2365 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2368 Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue),
2369 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2372 p.getNode()->setIROrder(idx + 1);
2373 InVals.push_back(p);
2377 // Param has ByVal attribute
2378 // Return MoveParam(param symbol).
2379 // Ideally, the param symbol can be returned directly,
2380 // but when SDNode builder decides to use it in a CopyToReg(),
2381 // machine instruction fails because TargetExternalSymbol
2382 // (not lowered) is target dependent, and CopyToReg assumes
2383 // the source is lowered.
2384 EVT ObjectVT = getValueType(DL, Ty);
2385 assert(ObjectVT == Ins[InsIdx].VT &&
2386 "Ins type did not match function type");
2387 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2388 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2390 p.getNode()->setIROrder(idx + 1);
2391 InVals.push_back(p);
2394 // Clang will check explicit VarArg and issue error if any. However, Clang
2395 // will let code with
2396 // implicit var arg like f() pass. See bug 617733.
2397 // We treat this case as if the arg list is empty.
2398 // if (F.isVarArg()) {
2399 // assert(0 && "VarArg not supported yet!");
2402 if (!OutChains.empty())
2403 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2409 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2411 const SmallVectorImpl<ISD::OutputArg> &Outs,
2412 const SmallVectorImpl<SDValue> &OutVals,
2413 const SDLoc &dl, SelectionDAG &DAG) const {
2414 MachineFunction &MF = DAG.getMachineFunction();
2415 const Function *F = MF.getFunction();
2416 Type *RetTy = F->getReturnType();
2417 const DataLayout &TD = DAG.getDataLayout();
2419 bool isABI = (STI.getSmVersion() >= 20);
2420 assert(isABI && "Non-ABI compilation is not supported");
2424 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2425 // If we have a vector type, the OutVals array will be the scalarized
2426 // components and we have combine them into 1 or more vector stores.
2427 unsigned NumElts = VTy->getNumElements();
2428 assert(NumElts == Outs.size() && "Bad scalarization of return value");
2430 // const_cast can be removed in later LLVM versions
2431 EVT EltVT = getValueType(TD, RetTy).getVectorElementType();
2432 bool NeedExtend = false;
2433 if (EltVT.getSizeInBits() < 16)
2438 SDValue StoreVal = OutVals[0];
2439 // We only have one element, so just directly store it
2441 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
2442 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal };
2443 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2444 DAG.getVTList(MVT::Other), Ops,
2445 EltVT, MachinePointerInfo());
2446 } else if (NumElts == 2) {
2448 SDValue StoreVal0 = OutVals[0];
2449 SDValue StoreVal1 = OutVals[1];
2452 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2453 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
2456 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0,
2458 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
2459 DAG.getVTList(MVT::Other), Ops,
2460 EltVT, MachinePointerInfo());
2463 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2464 // vector will be expanded to a power of 2 elements, so we know we can
2465 // always round up to the next multiple of 4 when creating the vector
2467 // e.g. 4 elem => 1 st.v4
2468 // 6 elem => 2 st.v4
2469 // 8 elem => 2 st.v4
2470 // 11 elem => 3 st.v4
2472 unsigned VecSize = 4;
2473 if (OutVals[0].getValueSizeInBits() == 64)
2476 unsigned Offset = 0;
2479 EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2480 unsigned PerStoreOffset =
2481 TD.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2483 for (unsigned i = 0; i < NumElts; i += VecSize) {
2486 SmallVector<SDValue, 8> Ops;
2487 Ops.push_back(Chain);
2488 Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32));
2489 unsigned Opc = NVPTXISD::StoreRetvalV2;
2490 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
2492 StoreVal = OutVals[i];
2494 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2495 Ops.push_back(StoreVal);
2497 if (i + 1 < NumElts) {
2498 StoreVal = OutVals[i + 1];
2500 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2502 StoreVal = DAG.getUNDEF(ExtendedVT);
2504 Ops.push_back(StoreVal);
2507 Opc = NVPTXISD::StoreRetvalV4;
2508 if (i + 2 < NumElts) {
2509 StoreVal = OutVals[i + 2];
2512 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2514 StoreVal = DAG.getUNDEF(ExtendedVT);
2516 Ops.push_back(StoreVal);
2518 if (i + 3 < NumElts) {
2519 StoreVal = OutVals[i + 3];
2522 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2524 StoreVal = DAG.getUNDEF(ExtendedVT);
2526 Ops.push_back(StoreVal);
2529 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2531 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2532 EltVT, MachinePointerInfo());
2533 Offset += PerStoreOffset;
2537 SmallVector<EVT, 16> ValVTs;
2538 SmallVector<uint64_t, 16> Offsets;
2539 ComputePTXValueVTs(*this, DAG.getDataLayout(), RetTy, ValVTs, &Offsets, 0);
2540 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2542 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2543 SDValue theVal = OutVals[i];
2544 EVT TheValType = theVal.getValueType();
2545 unsigned numElems = 1;
2546 if (TheValType.isVector())
2547 numElems = TheValType.getVectorNumElements();
2548 for (unsigned j = 0, je = numElems; j != je; ++j) {
2549 SDValue TmpVal = theVal;
2550 if (TheValType.isVector())
2551 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2552 TheValType.getVectorElementType(), TmpVal,
2553 DAG.getIntPtrConstant(j, dl));
2554 EVT TheStoreType = ValVTs[i];
2555 if (RetTy->isIntegerTy() && TD.getTypeAllocSizeInBits(RetTy) < 32) {
2556 // The following zero-extension is for integer types only, and
2557 // specifically not for aggregates.
2558 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2559 TheStoreType = MVT::i32;
2561 else if (TmpVal.getValueSizeInBits() < 16)
2562 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2566 DAG.getConstant(Offsets[i], dl, MVT::i32),
2568 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2569 DAG.getVTList(MVT::Other), Ops,
2571 MachinePointerInfo());
2576 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2579 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2580 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2581 SelectionDAG &DAG) const {
2582 if (Constraint.length() > 1)
2585 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2588 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2589 switch (Intrinsic) {
2593 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2594 return NVPTXISD::Tex1DFloatS32;
2595 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2596 return NVPTXISD::Tex1DFloatFloat;
2597 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2598 return NVPTXISD::Tex1DFloatFloatLevel;
2599 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2600 return NVPTXISD::Tex1DFloatFloatGrad;
2601 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2602 return NVPTXISD::Tex1DS32S32;
2603 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2604 return NVPTXISD::Tex1DS32Float;
2605 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2606 return NVPTXISD::Tex1DS32FloatLevel;
2607 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2608 return NVPTXISD::Tex1DS32FloatGrad;
2609 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2610 return NVPTXISD::Tex1DU32S32;
2611 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2612 return NVPTXISD::Tex1DU32Float;
2613 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2614 return NVPTXISD::Tex1DU32FloatLevel;
2615 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2616 return NVPTXISD::Tex1DU32FloatGrad;
2618 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2619 return NVPTXISD::Tex1DArrayFloatS32;
2620 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2621 return NVPTXISD::Tex1DArrayFloatFloat;
2622 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2623 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2624 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2625 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2626 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2627 return NVPTXISD::Tex1DArrayS32S32;
2628 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2629 return NVPTXISD::Tex1DArrayS32Float;
2630 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2631 return NVPTXISD::Tex1DArrayS32FloatLevel;
2632 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2633 return NVPTXISD::Tex1DArrayS32FloatGrad;
2634 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2635 return NVPTXISD::Tex1DArrayU32S32;
2636 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2637 return NVPTXISD::Tex1DArrayU32Float;
2638 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2639 return NVPTXISD::Tex1DArrayU32FloatLevel;
2640 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2641 return NVPTXISD::Tex1DArrayU32FloatGrad;
2643 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2644 return NVPTXISD::Tex2DFloatS32;
2645 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2646 return NVPTXISD::Tex2DFloatFloat;
2647 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2648 return NVPTXISD::Tex2DFloatFloatLevel;
2649 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2650 return NVPTXISD::Tex2DFloatFloatGrad;
2651 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2652 return NVPTXISD::Tex2DS32S32;
2653 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2654 return NVPTXISD::Tex2DS32Float;
2655 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2656 return NVPTXISD::Tex2DS32FloatLevel;
2657 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2658 return NVPTXISD::Tex2DS32FloatGrad;
2659 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2660 return NVPTXISD::Tex2DU32S32;
2661 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2662 return NVPTXISD::Tex2DU32Float;
2663 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2664 return NVPTXISD::Tex2DU32FloatLevel;
2665 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2666 return NVPTXISD::Tex2DU32FloatGrad;
2668 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2669 return NVPTXISD::Tex2DArrayFloatS32;
2670 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2671 return NVPTXISD::Tex2DArrayFloatFloat;
2672 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2673 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2674 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2675 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2676 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2677 return NVPTXISD::Tex2DArrayS32S32;
2678 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2679 return NVPTXISD::Tex2DArrayS32Float;
2680 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2681 return NVPTXISD::Tex2DArrayS32FloatLevel;
2682 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2683 return NVPTXISD::Tex2DArrayS32FloatGrad;
2684 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2685 return NVPTXISD::Tex2DArrayU32S32;
2686 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2687 return NVPTXISD::Tex2DArrayU32Float;
2688 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2689 return NVPTXISD::Tex2DArrayU32FloatLevel;
2690 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2691 return NVPTXISD::Tex2DArrayU32FloatGrad;
2693 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2694 return NVPTXISD::Tex3DFloatS32;
2695 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2696 return NVPTXISD::Tex3DFloatFloat;
2697 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2698 return NVPTXISD::Tex3DFloatFloatLevel;
2699 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2700 return NVPTXISD::Tex3DFloatFloatGrad;
2701 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2702 return NVPTXISD::Tex3DS32S32;
2703 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2704 return NVPTXISD::Tex3DS32Float;
2705 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2706 return NVPTXISD::Tex3DS32FloatLevel;
2707 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2708 return NVPTXISD::Tex3DS32FloatGrad;
2709 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2710 return NVPTXISD::Tex3DU32S32;
2711 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2712 return NVPTXISD::Tex3DU32Float;
2713 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2714 return NVPTXISD::Tex3DU32FloatLevel;
2715 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2716 return NVPTXISD::Tex3DU32FloatGrad;
2718 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2719 return NVPTXISD::TexCubeFloatFloat;
2720 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2721 return NVPTXISD::TexCubeFloatFloatLevel;
2722 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2723 return NVPTXISD::TexCubeS32Float;
2724 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2725 return NVPTXISD::TexCubeS32FloatLevel;
2726 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2727 return NVPTXISD::TexCubeU32Float;
2728 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2729 return NVPTXISD::TexCubeU32FloatLevel;
2731 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2732 return NVPTXISD::TexCubeArrayFloatFloat;
2733 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2734 return NVPTXISD::TexCubeArrayFloatFloatLevel;
2735 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2736 return NVPTXISD::TexCubeArrayS32Float;
2737 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2738 return NVPTXISD::TexCubeArrayS32FloatLevel;
2739 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2740 return NVPTXISD::TexCubeArrayU32Float;
2741 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2742 return NVPTXISD::TexCubeArrayU32FloatLevel;
2744 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2745 return NVPTXISD::Tld4R2DFloatFloat;
2746 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2747 return NVPTXISD::Tld4G2DFloatFloat;
2748 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2749 return NVPTXISD::Tld4B2DFloatFloat;
2750 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2751 return NVPTXISD::Tld4A2DFloatFloat;
2752 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2753 return NVPTXISD::Tld4R2DS64Float;
2754 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2755 return NVPTXISD::Tld4G2DS64Float;
2756 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2757 return NVPTXISD::Tld4B2DS64Float;
2758 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2759 return NVPTXISD::Tld4A2DS64Float;
2760 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2761 return NVPTXISD::Tld4R2DU64Float;
2762 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2763 return NVPTXISD::Tld4G2DU64Float;
2764 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2765 return NVPTXISD::Tld4B2DU64Float;
2766 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2767 return NVPTXISD::Tld4A2DU64Float;
2769 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2770 return NVPTXISD::TexUnified1DFloatS32;
2771 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2772 return NVPTXISD::TexUnified1DFloatFloat;
2773 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2774 return NVPTXISD::TexUnified1DFloatFloatLevel;
2775 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2776 return NVPTXISD::TexUnified1DFloatFloatGrad;
2777 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2778 return NVPTXISD::TexUnified1DS32S32;
2779 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2780 return NVPTXISD::TexUnified1DS32Float;
2781 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2782 return NVPTXISD::TexUnified1DS32FloatLevel;
2783 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2784 return NVPTXISD::TexUnified1DS32FloatGrad;
2785 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2786 return NVPTXISD::TexUnified1DU32S32;
2787 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2788 return NVPTXISD::TexUnified1DU32Float;
2789 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2790 return NVPTXISD::TexUnified1DU32FloatLevel;
2791 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2792 return NVPTXISD::TexUnified1DU32FloatGrad;
2794 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2795 return NVPTXISD::TexUnified1DArrayFloatS32;
2796 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2797 return NVPTXISD::TexUnified1DArrayFloatFloat;
2798 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2799 return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2800 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2801 return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2802 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2803 return NVPTXISD::TexUnified1DArrayS32S32;
2804 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2805 return NVPTXISD::TexUnified1DArrayS32Float;
2806 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2807 return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2808 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2809 return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2810 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2811 return NVPTXISD::TexUnified1DArrayU32S32;
2812 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2813 return NVPTXISD::TexUnified1DArrayU32Float;
2814 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2815 return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2816 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2817 return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2819 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2820 return NVPTXISD::TexUnified2DFloatS32;
2821 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2822 return NVPTXISD::TexUnified2DFloatFloat;
2823 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2824 return NVPTXISD::TexUnified2DFloatFloatLevel;
2825 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2826 return NVPTXISD::TexUnified2DFloatFloatGrad;
2827 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2828 return NVPTXISD::TexUnified2DS32S32;
2829 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2830 return NVPTXISD::TexUnified2DS32Float;
2831 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2832 return NVPTXISD::TexUnified2DS32FloatLevel;
2833 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2834 return NVPTXISD::TexUnified2DS32FloatGrad;
2835 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2836 return NVPTXISD::TexUnified2DU32S32;
2837 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2838 return NVPTXISD::TexUnified2DU32Float;
2839 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2840 return NVPTXISD::TexUnified2DU32FloatLevel;
2841 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2842 return NVPTXISD::TexUnified2DU32FloatGrad;
2844 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2845 return NVPTXISD::TexUnified2DArrayFloatS32;
2846 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2847 return NVPTXISD::TexUnified2DArrayFloatFloat;
2848 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2849 return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2850 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2851 return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2852 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2853 return NVPTXISD::TexUnified2DArrayS32S32;
2854 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2855 return NVPTXISD::TexUnified2DArrayS32Float;
2856 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2857 return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2858 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2859 return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2860 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2861 return NVPTXISD::TexUnified2DArrayU32S32;
2862 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2863 return NVPTXISD::TexUnified2DArrayU32Float;
2864 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2865 return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2866 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2867 return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2869 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2870 return NVPTXISD::TexUnified3DFloatS32;
2871 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2872 return NVPTXISD::TexUnified3DFloatFloat;
2873 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2874 return NVPTXISD::TexUnified3DFloatFloatLevel;
2875 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2876 return NVPTXISD::TexUnified3DFloatFloatGrad;
2877 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2878 return NVPTXISD::TexUnified3DS32S32;
2879 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2880 return NVPTXISD::TexUnified3DS32Float;
2881 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2882 return NVPTXISD::TexUnified3DS32FloatLevel;
2883 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2884 return NVPTXISD::TexUnified3DS32FloatGrad;
2885 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2886 return NVPTXISD::TexUnified3DU32S32;
2887 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2888 return NVPTXISD::TexUnified3DU32Float;
2889 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2890 return NVPTXISD::TexUnified3DU32FloatLevel;
2891 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2892 return NVPTXISD::TexUnified3DU32FloatGrad;
2894 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2895 return NVPTXISD::TexUnifiedCubeFloatFloat;
2896 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2897 return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2898 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2899 return NVPTXISD::TexUnifiedCubeS32Float;
2900 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2901 return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2902 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2903 return NVPTXISD::TexUnifiedCubeU32Float;
2904 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2905 return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2907 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2908 return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2909 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2910 return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2911 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2912 return NVPTXISD::TexUnifiedCubeArrayS32Float;
2913 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2914 return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2915 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2916 return NVPTXISD::TexUnifiedCubeArrayU32Float;
2917 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2918 return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2920 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2921 return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2922 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2923 return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2924 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2925 return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2926 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2927 return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2928 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2929 return NVPTXISD::Tld4UnifiedR2DS64Float;
2930 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2931 return NVPTXISD::Tld4UnifiedG2DS64Float;
2932 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2933 return NVPTXISD::Tld4UnifiedB2DS64Float;
2934 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2935 return NVPTXISD::Tld4UnifiedA2DS64Float;
2936 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2937 return NVPTXISD::Tld4UnifiedR2DU64Float;
2938 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2939 return NVPTXISD::Tld4UnifiedG2DU64Float;
2940 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2941 return NVPTXISD::Tld4UnifiedB2DU64Float;
2942 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2943 return NVPTXISD::Tld4UnifiedA2DU64Float;
2947 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2948 switch (Intrinsic) {
2951 case Intrinsic::nvvm_suld_1d_i8_clamp:
2952 return NVPTXISD::Suld1DI8Clamp;
2953 case Intrinsic::nvvm_suld_1d_i16_clamp:
2954 return NVPTXISD::Suld1DI16Clamp;
2955 case Intrinsic::nvvm_suld_1d_i32_clamp:
2956 return NVPTXISD::Suld1DI32Clamp;
2957 case Intrinsic::nvvm_suld_1d_i64_clamp:
2958 return NVPTXISD::Suld1DI64Clamp;
2959 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2960 return NVPTXISD::Suld1DV2I8Clamp;
2961 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2962 return NVPTXISD::Suld1DV2I16Clamp;
2963 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2964 return NVPTXISD::Suld1DV2I32Clamp;
2965 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2966 return NVPTXISD::Suld1DV2I64Clamp;
2967 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2968 return NVPTXISD::Suld1DV4I8Clamp;
2969 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2970 return NVPTXISD::Suld1DV4I16Clamp;
2971 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2972 return NVPTXISD::Suld1DV4I32Clamp;
2973 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2974 return NVPTXISD::Suld1DArrayI8Clamp;
2975 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2976 return NVPTXISD::Suld1DArrayI16Clamp;
2977 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2978 return NVPTXISD::Suld1DArrayI32Clamp;
2979 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2980 return NVPTXISD::Suld1DArrayI64Clamp;
2981 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2982 return NVPTXISD::Suld1DArrayV2I8Clamp;
2983 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2984 return NVPTXISD::Suld1DArrayV2I16Clamp;
2985 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2986 return NVPTXISD::Suld1DArrayV2I32Clamp;
2987 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2988 return NVPTXISD::Suld1DArrayV2I64Clamp;
2989 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2990 return NVPTXISD::Suld1DArrayV4I8Clamp;
2991 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2992 return NVPTXISD::Suld1DArrayV4I16Clamp;
2993 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2994 return NVPTXISD::Suld1DArrayV4I32Clamp;
2995 case Intrinsic::nvvm_suld_2d_i8_clamp:
2996 return NVPTXISD::Suld2DI8Clamp;
2997 case Intrinsic::nvvm_suld_2d_i16_clamp:
2998 return NVPTXISD::Suld2DI16Clamp;
2999 case Intrinsic::nvvm_suld_2d_i32_clamp:
3000 return NVPTXISD::Suld2DI32Clamp;
3001 case Intrinsic::nvvm_suld_2d_i64_clamp:
3002 return NVPTXISD::Suld2DI64Clamp;
3003 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3004 return NVPTXISD::Suld2DV2I8Clamp;
3005 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3006 return NVPTXISD::Suld2DV2I16Clamp;
3007 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3008 return NVPTXISD::Suld2DV2I32Clamp;
3009 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3010 return NVPTXISD::Suld2DV2I64Clamp;
3011 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3012 return NVPTXISD::Suld2DV4I8Clamp;
3013 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3014 return NVPTXISD::Suld2DV4I16Clamp;
3015 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3016 return NVPTXISD::Suld2DV4I32Clamp;
3017 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3018 return NVPTXISD::Suld2DArrayI8Clamp;
3019 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3020 return NVPTXISD::Suld2DArrayI16Clamp;
3021 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3022 return NVPTXISD::Suld2DArrayI32Clamp;
3023 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3024 return NVPTXISD::Suld2DArrayI64Clamp;
3025 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3026 return NVPTXISD::Suld2DArrayV2I8Clamp;
3027 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3028 return NVPTXISD::Suld2DArrayV2I16Clamp;
3029 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3030 return NVPTXISD::Suld2DArrayV2I32Clamp;
3031 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3032 return NVPTXISD::Suld2DArrayV2I64Clamp;
3033 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3034 return NVPTXISD::Suld2DArrayV4I8Clamp;
3035 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3036 return NVPTXISD::Suld2DArrayV4I16Clamp;
3037 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3038 return NVPTXISD::Suld2DArrayV4I32Clamp;
3039 case Intrinsic::nvvm_suld_3d_i8_clamp:
3040 return NVPTXISD::Suld3DI8Clamp;
3041 case Intrinsic::nvvm_suld_3d_i16_clamp:
3042 return NVPTXISD::Suld3DI16Clamp;
3043 case Intrinsic::nvvm_suld_3d_i32_clamp:
3044 return NVPTXISD::Suld3DI32Clamp;
3045 case Intrinsic::nvvm_suld_3d_i64_clamp:
3046 return NVPTXISD::Suld3DI64Clamp;
3047 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3048 return NVPTXISD::Suld3DV2I8Clamp;
3049 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3050 return NVPTXISD::Suld3DV2I16Clamp;
3051 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3052 return NVPTXISD::Suld3DV2I32Clamp;
3053 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3054 return NVPTXISD::Suld3DV2I64Clamp;
3055 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3056 return NVPTXISD::Suld3DV4I8Clamp;
3057 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3058 return NVPTXISD::Suld3DV4I16Clamp;
3059 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3060 return NVPTXISD::Suld3DV4I32Clamp;
3061 case Intrinsic::nvvm_suld_1d_i8_trap:
3062 return NVPTXISD::Suld1DI8Trap;
3063 case Intrinsic::nvvm_suld_1d_i16_trap:
3064 return NVPTXISD::Suld1DI16Trap;
3065 case Intrinsic::nvvm_suld_1d_i32_trap:
3066 return NVPTXISD::Suld1DI32Trap;
3067 case Intrinsic::nvvm_suld_1d_i64_trap:
3068 return NVPTXISD::Suld1DI64Trap;
3069 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3070 return NVPTXISD::Suld1DV2I8Trap;
3071 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3072 return NVPTXISD::Suld1DV2I16Trap;
3073 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3074 return NVPTXISD::Suld1DV2I32Trap;
3075 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3076 return NVPTXISD::Suld1DV2I64Trap;
3077 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3078 return NVPTXISD::Suld1DV4I8Trap;
3079 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3080 return NVPTXISD::Suld1DV4I16Trap;
3081 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3082 return NVPTXISD::Suld1DV4I32Trap;
3083 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3084 return NVPTXISD::Suld1DArrayI8Trap;
3085 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3086 return NVPTXISD::Suld1DArrayI16Trap;
3087 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3088 return NVPTXISD::Suld1DArrayI32Trap;
3089 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3090 return NVPTXISD::Suld1DArrayI64Trap;
3091 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3092 return NVPTXISD::Suld1DArrayV2I8Trap;
3093 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3094 return NVPTXISD::Suld1DArrayV2I16Trap;
3095 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3096 return NVPTXISD::Suld1DArrayV2I32Trap;
3097 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3098 return NVPTXISD::Suld1DArrayV2I64Trap;
3099 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3100 return NVPTXISD::Suld1DArrayV4I8Trap;
3101 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3102 return NVPTXISD::Suld1DArrayV4I16Trap;
3103 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3104 return NVPTXISD::Suld1DArrayV4I32Trap;
3105 case Intrinsic::nvvm_suld_2d_i8_trap:
3106 return NVPTXISD::Suld2DI8Trap;
3107 case Intrinsic::nvvm_suld_2d_i16_trap:
3108 return NVPTXISD::Suld2DI16Trap;
3109 case Intrinsic::nvvm_suld_2d_i32_trap:
3110 return NVPTXISD::Suld2DI32Trap;
3111 case Intrinsic::nvvm_suld_2d_i64_trap:
3112 return NVPTXISD::Suld2DI64Trap;
3113 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3114 return NVPTXISD::Suld2DV2I8Trap;
3115 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3116 return NVPTXISD::Suld2DV2I16Trap;
3117 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3118 return NVPTXISD::Suld2DV2I32Trap;
3119 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3120 return NVPTXISD::Suld2DV2I64Trap;
3121 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3122 return NVPTXISD::Suld2DV4I8Trap;
3123 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3124 return NVPTXISD::Suld2DV4I16Trap;
3125 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3126 return NVPTXISD::Suld2DV4I32Trap;
3127 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3128 return NVPTXISD::Suld2DArrayI8Trap;
3129 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3130 return NVPTXISD::Suld2DArrayI16Trap;
3131 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3132 return NVPTXISD::Suld2DArrayI32Trap;
3133 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3134 return NVPTXISD::Suld2DArrayI64Trap;
3135 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3136 return NVPTXISD::Suld2DArrayV2I8Trap;
3137 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3138 return NVPTXISD::Suld2DArrayV2I16Trap;
3139 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3140 return NVPTXISD::Suld2DArrayV2I32Trap;
3141 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3142 return NVPTXISD::Suld2DArrayV2I64Trap;
3143 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3144 return NVPTXISD::Suld2DArrayV4I8Trap;
3145 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3146 return NVPTXISD::Suld2DArrayV4I16Trap;
3147 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3148 return NVPTXISD::Suld2DArrayV4I32Trap;
3149 case Intrinsic::nvvm_suld_3d_i8_trap:
3150 return NVPTXISD::Suld3DI8Trap;
3151 case Intrinsic::nvvm_suld_3d_i16_trap:
3152 return NVPTXISD::Suld3DI16Trap;
3153 case Intrinsic::nvvm_suld_3d_i32_trap:
3154 return NVPTXISD::Suld3DI32Trap;
3155 case Intrinsic::nvvm_suld_3d_i64_trap:
3156 return NVPTXISD::Suld3DI64Trap;
3157 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3158 return NVPTXISD::Suld3DV2I8Trap;
3159 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3160 return NVPTXISD::Suld3DV2I16Trap;
3161 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3162 return NVPTXISD::Suld3DV2I32Trap;
3163 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3164 return NVPTXISD::Suld3DV2I64Trap;
3165 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3166 return NVPTXISD::Suld3DV4I8Trap;
3167 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3168 return NVPTXISD::Suld3DV4I16Trap;
3169 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3170 return NVPTXISD::Suld3DV4I32Trap;
3171 case Intrinsic::nvvm_suld_1d_i8_zero:
3172 return NVPTXISD::Suld1DI8Zero;
3173 case Intrinsic::nvvm_suld_1d_i16_zero:
3174 return NVPTXISD::Suld1DI16Zero;
3175 case Intrinsic::nvvm_suld_1d_i32_zero:
3176 return NVPTXISD::Suld1DI32Zero;
3177 case Intrinsic::nvvm_suld_1d_i64_zero:
3178 return NVPTXISD::Suld1DI64Zero;
3179 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3180 return NVPTXISD::Suld1DV2I8Zero;
3181 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3182 return NVPTXISD::Suld1DV2I16Zero;
3183 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3184 return NVPTXISD::Suld1DV2I32Zero;
3185 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3186 return NVPTXISD::Suld1DV2I64Zero;
3187 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3188 return NVPTXISD::Suld1DV4I8Zero;
3189 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3190 return NVPTXISD::Suld1DV4I16Zero;
3191 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3192 return NVPTXISD::Suld1DV4I32Zero;
3193 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3194 return NVPTXISD::Suld1DArrayI8Zero;
3195 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3196 return NVPTXISD::Suld1DArrayI16Zero;
3197 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3198 return NVPTXISD::Suld1DArrayI32Zero;
3199 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3200 return NVPTXISD::Suld1DArrayI64Zero;
3201 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3202 return NVPTXISD::Suld1DArrayV2I8Zero;
3203 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3204 return NVPTXISD::Suld1DArrayV2I16Zero;
3205 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3206 return NVPTXISD::Suld1DArrayV2I32Zero;
3207 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3208 return NVPTXISD::Suld1DArrayV2I64Zero;
3209 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3210 return NVPTXISD::Suld1DArrayV4I8Zero;
3211 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3212 return NVPTXISD::Suld1DArrayV4I16Zero;
3213 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3214 return NVPTXISD::Suld1DArrayV4I32Zero;
3215 case Intrinsic::nvvm_suld_2d_i8_zero:
3216 return NVPTXISD::Suld2DI8Zero;
3217 case Intrinsic::nvvm_suld_2d_i16_zero:
3218 return NVPTXISD::Suld2DI16Zero;
3219 case Intrinsic::nvvm_suld_2d_i32_zero:
3220 return NVPTXISD::Suld2DI32Zero;
3221 case Intrinsic::nvvm_suld_2d_i64_zero:
3222 return NVPTXISD::Suld2DI64Zero;
3223 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3224 return NVPTXISD::Suld2DV2I8Zero;
3225 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3226 return NVPTXISD::Suld2DV2I16Zero;
3227 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3228 return NVPTXISD::Suld2DV2I32Zero;
3229 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3230 return NVPTXISD::Suld2DV2I64Zero;
3231 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3232 return NVPTXISD::Suld2DV4I8Zero;
3233 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3234 return NVPTXISD::Suld2DV4I16Zero;
3235 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3236 return NVPTXISD::Suld2DV4I32Zero;
3237 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3238 return NVPTXISD::Suld2DArrayI8Zero;
3239 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3240 return NVPTXISD::Suld2DArrayI16Zero;
3241 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3242 return NVPTXISD::Suld2DArrayI32Zero;
3243 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3244 return NVPTXISD::Suld2DArrayI64Zero;
3245 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3246 return NVPTXISD::Suld2DArrayV2I8Zero;
3247 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3248 return NVPTXISD::Suld2DArrayV2I16Zero;
3249 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3250 return NVPTXISD::Suld2DArrayV2I32Zero;
3251 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3252 return NVPTXISD::Suld2DArrayV2I64Zero;
3253 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3254 return NVPTXISD::Suld2DArrayV4I8Zero;
3255 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3256 return NVPTXISD::Suld2DArrayV4I16Zero;
3257 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3258 return NVPTXISD::Suld2DArrayV4I32Zero;
3259 case Intrinsic::nvvm_suld_3d_i8_zero:
3260 return NVPTXISD::Suld3DI8Zero;
3261 case Intrinsic::nvvm_suld_3d_i16_zero:
3262 return NVPTXISD::Suld3DI16Zero;
3263 case Intrinsic::nvvm_suld_3d_i32_zero:
3264 return NVPTXISD::Suld3DI32Zero;
3265 case Intrinsic::nvvm_suld_3d_i64_zero:
3266 return NVPTXISD::Suld3DI64Zero;
3267 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3268 return NVPTXISD::Suld3DV2I8Zero;
3269 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3270 return NVPTXISD::Suld3DV2I16Zero;
3271 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3272 return NVPTXISD::Suld3DV2I32Zero;
3273 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3274 return NVPTXISD::Suld3DV2I64Zero;
3275 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3276 return NVPTXISD::Suld3DV4I8Zero;
3277 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3278 return NVPTXISD::Suld3DV4I16Zero;
3279 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3280 return NVPTXISD::Suld3DV4I32Zero;
3284 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3286 // because we need the information that is only available in the "Value" type
3288 // pointer. In particular, the address space information.
3289 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3290 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3291 switch (Intrinsic) {
3295 case Intrinsic::nvvm_atomic_load_add_f32:
3296 case Intrinsic::nvvm_atomic_load_inc_32:
3297 case Intrinsic::nvvm_atomic_load_dec_32:
3299 case Intrinsic::nvvm_atomic_add_gen_f_cta:
3300 case Intrinsic::nvvm_atomic_add_gen_f_sys:
3301 case Intrinsic::nvvm_atomic_add_gen_i_cta:
3302 case Intrinsic::nvvm_atomic_add_gen_i_sys:
3303 case Intrinsic::nvvm_atomic_and_gen_i_cta:
3304 case Intrinsic::nvvm_atomic_and_gen_i_sys:
3305 case Intrinsic::nvvm_atomic_cas_gen_i_cta:
3306 case Intrinsic::nvvm_atomic_cas_gen_i_sys:
3307 case Intrinsic::nvvm_atomic_dec_gen_i_cta:
3308 case Intrinsic::nvvm_atomic_dec_gen_i_sys:
3309 case Intrinsic::nvvm_atomic_inc_gen_i_cta:
3310 case Intrinsic::nvvm_atomic_inc_gen_i_sys:
3311 case Intrinsic::nvvm_atomic_max_gen_i_cta:
3312 case Intrinsic::nvvm_atomic_max_gen_i_sys:
3313 case Intrinsic::nvvm_atomic_min_gen_i_cta:
3314 case Intrinsic::nvvm_atomic_min_gen_i_sys:
3315 case Intrinsic::nvvm_atomic_or_gen_i_cta:
3316 case Intrinsic::nvvm_atomic_or_gen_i_sys:
3317 case Intrinsic::nvvm_atomic_exch_gen_i_cta:
3318 case Intrinsic::nvvm_atomic_exch_gen_i_sys:
3319 case Intrinsic::nvvm_atomic_xor_gen_i_cta:
3320 case Intrinsic::nvvm_atomic_xor_gen_i_sys: {
3321 auto &DL = I.getModule()->getDataLayout();
3322 Info.opc = ISD::INTRINSIC_W_CHAIN;
3323 Info.memVT = getValueType(DL, I.getType());
3324 Info.ptrVal = I.getArgOperand(0);
3327 Info.readMem = true;
3328 Info.writeMem = true;
3333 case Intrinsic::nvvm_ldu_global_i:
3334 case Intrinsic::nvvm_ldu_global_f:
3335 case Intrinsic::nvvm_ldu_global_p: {
3336 auto &DL = I.getModule()->getDataLayout();
3337 Info.opc = ISD::INTRINSIC_W_CHAIN;
3338 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3339 Info.memVT = getValueType(DL, I.getType());
3340 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3341 Info.memVT = getPointerTy(DL);
3343 Info.memVT = getValueType(DL, I.getType());
3344 Info.ptrVal = I.getArgOperand(0);
3347 Info.readMem = true;
3348 Info.writeMem = false;
3349 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3353 case Intrinsic::nvvm_ldg_global_i:
3354 case Intrinsic::nvvm_ldg_global_f:
3355 case Intrinsic::nvvm_ldg_global_p: {
3356 auto &DL = I.getModule()->getDataLayout();
3358 Info.opc = ISD::INTRINSIC_W_CHAIN;
3359 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3360 Info.memVT = getValueType(DL, I.getType());
3361 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3362 Info.memVT = getPointerTy(DL);
3364 Info.memVT = getValueType(DL, I.getType());
3365 Info.ptrVal = I.getArgOperand(0);
3368 Info.readMem = true;
3369 Info.writeMem = false;
3370 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3375 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3376 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3377 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3378 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3379 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3380 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3381 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3382 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3383 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3384 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3385 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3386 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3387 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3388 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3389 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3390 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3391 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3392 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3393 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3394 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3395 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3396 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3397 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3398 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3399 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3400 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3401 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3402 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3403 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3404 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3405 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3406 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3407 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3408 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3409 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3410 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3411 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3412 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3413 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3414 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3415 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3416 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3417 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3418 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3419 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3420 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3421 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3422 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3423 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3424 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3425 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3426 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3427 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3428 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3429 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3430 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
3431 Info.opc = getOpcForTextureInstr(Intrinsic);
3432 Info.memVT = MVT::v4f32;
3433 Info.ptrVal = nullptr;
3436 Info.readMem = true;
3437 Info.writeMem = false;
3441 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3442 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3443 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3444 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3445 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3446 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3447 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3448 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3449 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3450 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3451 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3452 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3453 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3454 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3455 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3456 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3457 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3458 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3459 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3460 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3461 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3462 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3463 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3464 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3465 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3466 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3467 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3468 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3469 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3470 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3471 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3472 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3473 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3474 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3475 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3476 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3477 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3478 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3479 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3480 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3481 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3482 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3483 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3484 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3485 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3486 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3487 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3488 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3489 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3490 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3491 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3492 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3493 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3494 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3495 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3496 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3497 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3498 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3499 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3500 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3501 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3502 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3503 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3504 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3505 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3506 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3507 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3508 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3509 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3510 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3511 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3512 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3513 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3514 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3515 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3516 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3517 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3518 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3519 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3520 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3521 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3522 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3523 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3524 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3525 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3526 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3527 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3528 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3529 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3530 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3531 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3532 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3533 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3534 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3535 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3536 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3537 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3538 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3539 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3540 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3541 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3542 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3543 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3544 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3545 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3546 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3547 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3548 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3549 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3550 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3551 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3552 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
3553 Info.opc = getOpcForTextureInstr(Intrinsic);
3554 Info.memVT = MVT::v4i32;
3555 Info.ptrVal = nullptr;
3558 Info.readMem = true;
3559 Info.writeMem = false;
3563 case Intrinsic::nvvm_suld_1d_i8_clamp:
3564 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3565 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3566 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3567 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3568 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3569 case Intrinsic::nvvm_suld_2d_i8_clamp:
3570 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3571 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3572 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3573 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3574 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3575 case Intrinsic::nvvm_suld_3d_i8_clamp:
3576 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3577 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3578 case Intrinsic::nvvm_suld_1d_i8_trap:
3579 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3580 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3581 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3582 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3583 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3584 case Intrinsic::nvvm_suld_2d_i8_trap:
3585 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3586 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3587 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3588 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3589 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3590 case Intrinsic::nvvm_suld_3d_i8_trap:
3591 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3592 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3593 case Intrinsic::nvvm_suld_1d_i8_zero:
3594 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3595 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3596 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3597 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3598 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3599 case Intrinsic::nvvm_suld_2d_i8_zero:
3600 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3601 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3602 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3603 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3604 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3605 case Intrinsic::nvvm_suld_3d_i8_zero:
3606 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3607 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3608 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3609 Info.memVT = MVT::i8;
3610 Info.ptrVal = nullptr;
3613 Info.readMem = true;
3614 Info.writeMem = false;
3618 case Intrinsic::nvvm_suld_1d_i16_clamp:
3619 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3620 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3621 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3622 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3623 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3624 case Intrinsic::nvvm_suld_2d_i16_clamp:
3625 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3626 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3627 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3628 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3629 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3630 case Intrinsic::nvvm_suld_3d_i16_clamp:
3631 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3632 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3633 case Intrinsic::nvvm_suld_1d_i16_trap:
3634 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3635 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3636 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3637 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3638 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3639 case Intrinsic::nvvm_suld_2d_i16_trap:
3640 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3641 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3642 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3643 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3644 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3645 case Intrinsic::nvvm_suld_3d_i16_trap:
3646 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3647 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3648 case Intrinsic::nvvm_suld_1d_i16_zero:
3649 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3650 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3651 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3652 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3653 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3654 case Intrinsic::nvvm_suld_2d_i16_zero:
3655 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3656 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3657 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3658 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3659 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3660 case Intrinsic::nvvm_suld_3d_i16_zero:
3661 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3662 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3663 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3664 Info.memVT = MVT::i16;
3665 Info.ptrVal = nullptr;
3668 Info.readMem = true;
3669 Info.writeMem = false;
3673 case Intrinsic::nvvm_suld_1d_i32_clamp:
3674 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3675 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3676 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3677 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3678 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3679 case Intrinsic::nvvm_suld_2d_i32_clamp:
3680 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3681 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3682 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3683 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3684 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3685 case Intrinsic::nvvm_suld_3d_i32_clamp:
3686 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3687 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3688 case Intrinsic::nvvm_suld_1d_i32_trap:
3689 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3690 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3691 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3692 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3693 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3694 case Intrinsic::nvvm_suld_2d_i32_trap:
3695 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3696 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3697 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3698 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3699 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3700 case Intrinsic::nvvm_suld_3d_i32_trap:
3701 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3702 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3703 case Intrinsic::nvvm_suld_1d_i32_zero:
3704 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3705 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3706 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3707 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3708 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3709 case Intrinsic::nvvm_suld_2d_i32_zero:
3710 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3711 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3712 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3713 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3714 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3715 case Intrinsic::nvvm_suld_3d_i32_zero:
3716 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3717 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3718 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3719 Info.memVT = MVT::i32;
3720 Info.ptrVal = nullptr;
3723 Info.readMem = true;
3724 Info.writeMem = false;
3728 case Intrinsic::nvvm_suld_1d_i64_clamp:
3729 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3730 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3731 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3732 case Intrinsic::nvvm_suld_2d_i64_clamp:
3733 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3734 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3735 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3736 case Intrinsic::nvvm_suld_3d_i64_clamp:
3737 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3738 case Intrinsic::nvvm_suld_1d_i64_trap:
3739 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3740 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3741 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3742 case Intrinsic::nvvm_suld_2d_i64_trap:
3743 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3744 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3745 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3746 case Intrinsic::nvvm_suld_3d_i64_trap:
3747 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3748 case Intrinsic::nvvm_suld_1d_i64_zero:
3749 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3750 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3751 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3752 case Intrinsic::nvvm_suld_2d_i64_zero:
3753 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3754 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3755 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3756 case Intrinsic::nvvm_suld_3d_i64_zero:
3757 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3758 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3759 Info.memVT = MVT::i64;
3760 Info.ptrVal = nullptr;
3763 Info.readMem = true;
3764 Info.writeMem = false;
3771 /// isLegalAddressingMode - Return true if the addressing mode represented
3772 /// by AM is legal for this target, for a load/store of the specified type.
3773 /// Used to guide target specific optimizations, like loop strength reduction
3774 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3775 /// (CodeGenPrepare.cpp)
3776 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3777 const AddrMode &AM, Type *Ty,
3778 unsigned AS) const {
3779 // AddrMode - This represents an addressing mode of:
3780 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3782 // The legal address modes are
3789 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3793 case 0: // "r", "r+i" or "i" is allowed
3796 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3798 // Otherwise we have r+i.
3801 // No scale > 1 is allowed
3807 //===----------------------------------------------------------------------===//
3808 // NVPTX Inline Assembly Support
3809 //===----------------------------------------------------------------------===//
3811 /// getConstraintType - Given a constraint letter, return the type of
3812 /// constraint it is for this target.
3813 NVPTXTargetLowering::ConstraintType
3814 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
3815 if (Constraint.size() == 1) {
3816 switch (Constraint[0]) {
3828 return C_RegisterClass;
3831 return TargetLowering::getConstraintType(Constraint);
3834 std::pair<unsigned, const TargetRegisterClass *>
3835 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3836 StringRef Constraint,
3838 if (Constraint.size() == 1) {
3839 switch (Constraint[0]) {
3841 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3843 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3845 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3847 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3850 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3852 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3854 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3857 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3860 //===----------------------------------------------------------------------===//
3861 // NVPTX DAG Combining
3862 //===----------------------------------------------------------------------===//
3864 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3865 CodeGenOpt::Level OptLevel) const {
3866 const Function *F = MF.getFunction();
3867 const TargetOptions &TO = MF.getTarget().Options;
3869 // Always honor command-line argument
3870 if (FMAContractLevelOpt.getNumOccurrences() > 0) {
3871 return FMAContractLevelOpt > 0;
3872 } else if (OptLevel == 0) {
3873 // Do not contract if we're not optimizing the code
3875 } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
3876 // Honor TargetOptions flags that explicitly say fusion is okay
3878 } else if (F->hasFnAttribute("unsafe-fp-math")) {
3879 // Check for unsafe-fp-math=true coming from Clang
3880 Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3881 StringRef Val = Attr.getValueAsString();
3886 // We did not have a clear indication that fusion is allowed, so assume not
3890 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3891 /// operands N0 and N1. This is a helper for PerformADDCombine that is
3892 /// called with the default operands, and if that fails, with commuted
3894 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3895 TargetLowering::DAGCombinerInfo &DCI,
3896 const NVPTXSubtarget &Subtarget,
3897 CodeGenOpt::Level OptLevel) {
3898 SelectionDAG &DAG = DCI.DAG;
3899 // Skip non-integer, non-scalar case
3900 EVT VT=N0.getValueType();
3904 // fold (add (mul a, b), c) -> (mad a, b, c)
3906 if (N0.getOpcode() == ISD::MUL) {
3907 assert (VT.isInteger());
3909 // Since integer multiply-add costs the same as integer multiply
3910 // but is more costly than integer add, do the fusion only when
3911 // the mul is only used in the add.
3912 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3913 !N0.getNode()->hasOneUse())
3917 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3918 N0.getOperand(0), N0.getOperand(1), N1);
3920 else if (N0.getOpcode() == ISD::FMUL) {
3921 if (VT == MVT::f32 || VT == MVT::f64) {
3922 const auto *TLI = static_cast<const NVPTXTargetLowering *>(
3923 &DAG.getTargetLoweringInfo());
3924 if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3927 // For floating point:
3928 // Do the fusion only when the mul has less than 5 uses and all
3930 // The heuristic is that if a use is not an add, then that use
3931 // cannot be fused into fma, therefore mul is still needed anyway.
3932 // If there are more than 4 uses, even if they are all add, fusing
3933 // them will increase register pressue.
3936 int nonAddCount = 0;
3937 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3938 UE = N0.getNode()->use_end();
3942 if (User->getOpcode() != ISD::FADD)
3948 int orderNo = N->getIROrder();
3949 int orderNo2 = N0.getNode()->getIROrder();
3950 // simple heuristics here for considering potential register
3951 // pressure, the logics here is that the differnce are used
3952 // to measure the distance between def and use, the longer distance
3953 // more likely cause register pressure.
3954 if (orderNo - orderNo2 < 500)
3957 // Now, check if at least one of the FMUL's operands is live beyond the node N,
3958 // which guarantees that the FMA will not increase register pressure at node N.
3959 bool opIsLive = false;
3960 const SDNode *left = N0.getOperand(0).getNode();
3961 const SDNode *right = N0.getOperand(1).getNode();
3963 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3967 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
3969 int orderNo3 = User->getIROrder();
3970 if (orderNo3 > orderNo) {
3977 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
3979 int orderNo3 = User->getIROrder();
3980 if (orderNo3 > orderNo) {
3990 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
3991 N0.getOperand(0), N0.getOperand(1), N1);
3998 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4000 static SDValue PerformADDCombine(SDNode *N,
4001 TargetLowering::DAGCombinerInfo &DCI,
4002 const NVPTXSubtarget &Subtarget,
4003 CodeGenOpt::Level OptLevel) {
4004 SDValue N0 = N->getOperand(0);
4005 SDValue N1 = N->getOperand(1);
4007 // First try with the default operand order.
4008 if (SDValue Result =
4009 PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, OptLevel))
4012 // If that didn't work, try again with the operands commuted.
4013 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
4016 static SDValue PerformANDCombine(SDNode *N,
4017 TargetLowering::DAGCombinerInfo &DCI) {
4018 // The type legalizer turns a vector load of i8 values into a zextload to i16
4019 // registers, optionally ANY_EXTENDs it (if target type is integer),
4020 // and ANDs off the high 8 bits. Since we turn this load into a
4021 // target-specific DAG node, the DAG combiner fails to eliminate these AND
4022 // nodes. Do that here.
4023 SDValue Val = N->getOperand(0);
4024 SDValue Mask = N->getOperand(1);
4026 if (isa<ConstantSDNode>(Val)) {
4027 std::swap(Val, Mask);
4031 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4032 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4034 Val = Val->getOperand(0);
4037 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4038 Val = Val->getOperand(0);
4041 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4042 Val->getOpcode() == NVPTXISD::LoadV4) {
4043 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
4045 // Not an AND with a constant
4049 uint64_t MaskVal = MaskCnst->getZExtValue();
4050 if (MaskVal != 0xff) {
4051 // Not an AND that chops off top 8 bits
4055 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4057 // Not a MemSDNode?!?
4061 EVT MemVT = Mem->getMemoryVT();
4062 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4063 // We only handle the i8 case
4068 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4070 if (ExtType == ISD::SEXTLOAD) {
4071 // If for some reason the load is a sextload, the and is needed to zero
4072 // out the high 8 bits
4077 if (AExt.getNode() != nullptr) {
4078 // Re-insert the ext as a zext.
4079 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4080 AExt.getValueType(), Val);
4084 // If we get here, the AND is unnecessary. Just replace it with the load
4085 DCI.CombineTo(N, Val, AddTo);
4091 static SDValue PerformSELECTCombine(SDNode *N,
4092 TargetLowering::DAGCombinerInfo &DCI) {
4093 // Currently this detects patterns for integer min and max and
4094 // lowers them to PTX-specific intrinsics that enable hardware
4097 const SDValue Cond = N->getOperand(0);
4098 if (Cond.getOpcode() != ISD::SETCC) return SDValue();
4100 const SDValue LHS = Cond.getOperand(0);
4101 const SDValue RHS = Cond.getOperand(1);
4102 const SDValue True = N->getOperand(1);
4103 const SDValue False = N->getOperand(2);
4104 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4107 const EVT VT = N->getValueType(0);
4108 if (VT != MVT::i32 && VT != MVT::i64) return SDValue();
4110 const ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4111 SDValue Larger; // The larger of LHS and RHS when condition is true.
4130 const bool IsMax = (Larger == True);
4131 const bool IsSigned = ISD::isSignedIntSetCC(CC);
4133 unsigned IntrinsicId;
4134 if (VT == MVT::i32) {
4136 IntrinsicId = IsMax ? Intrinsic::nvvm_max_i : Intrinsic::nvvm_min_i;
4138 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ui : Intrinsic::nvvm_min_ui;
4140 assert(VT == MVT::i64);
4142 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ll : Intrinsic::nvvm_min_ll;
4144 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ull : Intrinsic::nvvm_min_ull;
4148 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
4149 DCI.DAG.getConstant(IntrinsicId, DL, VT), LHS, RHS);
4152 static SDValue PerformREMCombine(SDNode *N,
4153 TargetLowering::DAGCombinerInfo &DCI,
4154 CodeGenOpt::Level OptLevel) {
4155 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4157 // Don't do anything at less than -O2.
4158 if (OptLevel < CodeGenOpt::Default)
4161 SelectionDAG &DAG = DCI.DAG;
4163 EVT VT = N->getValueType(0);
4164 bool IsSigned = N->getOpcode() == ISD::SREM;
4165 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
4167 const SDValue &Num = N->getOperand(0);
4168 const SDValue &Den = N->getOperand(1);
4170 for (const SDNode *U : Num->uses()) {
4171 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
4172 U->getOperand(1) == Den) {
4173 // Num % Den -> Num - (Num / Den) * Den
4174 return DAG.getNode(ISD::SUB, DL, VT, Num,
4175 DAG.getNode(ISD::MUL, DL, VT,
4176 DAG.getNode(DivOpc, DL, VT, Num, Den),
4183 enum OperandSignedness {
4189 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4190 /// that can be demoted to \p OptSize bits without loss of information. The
4191 /// signedness of the operand, if determinable, is placed in \p S.
4192 static bool IsMulWideOperandDemotable(SDValue Op,
4194 OperandSignedness &S) {
4197 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4198 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4199 EVT OrigVT = Op.getOperand(0).getValueType();
4200 if (OrigVT.getSizeInBits() <= OptSize) {
4204 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4205 EVT OrigVT = Op.getOperand(0).getValueType();
4206 if (OrigVT.getSizeInBits() <= OptSize) {
4215 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4216 /// be demoted to \p OptSize bits without loss of information. If the operands
4217 /// contain a constant, it should appear as the RHS operand. The signedness of
4218 /// the operands is placed in \p IsSigned.
4219 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4222 OperandSignedness LHSSign;
4224 // The LHS operand must be a demotable op
4225 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4228 // We should have been able to determine the signedness from the LHS
4229 if (LHSSign == Unknown)
4232 IsSigned = (LHSSign == Signed);
4234 // The RHS can be a demotable op or a constant
4235 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4236 const APInt &Val = CI->getAPIntValue();
4237 if (LHSSign == Unsigned) {
4238 return Val.isIntN(OptSize);
4240 return Val.isSignedIntN(OptSize);
4243 OperandSignedness RHSSign;
4244 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4247 return LHSSign == RHSSign;
4251 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4252 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4253 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4255 static SDValue TryMULWIDECombine(SDNode *N,
4256 TargetLowering::DAGCombinerInfo &DCI) {
4257 EVT MulType = N->getValueType(0);
4258 if (MulType != MVT::i32 && MulType != MVT::i64) {
4263 unsigned OptSize = MulType.getSizeInBits() >> 1;
4264 SDValue LHS = N->getOperand(0);
4265 SDValue RHS = N->getOperand(1);
4267 // Canonicalize the multiply so the constant (if any) is on the right
4268 if (N->getOpcode() == ISD::MUL) {
4269 if (isa<ConstantSDNode>(LHS)) {
4270 std::swap(LHS, RHS);
4274 // If we have a SHL, determine the actual multiply amount
4275 if (N->getOpcode() == ISD::SHL) {
4276 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4281 APInt ShiftAmt = ShlRHS->getAPIntValue();
4282 unsigned BitWidth = MulType.getSizeInBits();
4283 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4284 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4285 RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4292 // Verify that our operands are demotable
4293 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4298 if (MulType == MVT::i32) {
4299 DemotedVT = MVT::i16;
4301 DemotedVT = MVT::i32;
4304 // Truncate the operands to the correct size. Note that these are just for
4305 // type consistency and will (likely) be eliminated in later phases.
4307 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4309 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4313 Opc = NVPTXISD::MUL_WIDE_SIGNED;
4315 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4318 return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4321 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4322 static SDValue PerformMULCombine(SDNode *N,
4323 TargetLowering::DAGCombinerInfo &DCI,
4324 CodeGenOpt::Level OptLevel) {
4326 // Try mul.wide combining at OptLevel > 0
4327 if (SDValue Ret = TryMULWIDECombine(N, DCI))
4334 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4335 static SDValue PerformSHLCombine(SDNode *N,
4336 TargetLowering::DAGCombinerInfo &DCI,
4337 CodeGenOpt::Level OptLevel) {
4339 // Try mul.wide combining at OptLevel > 0
4340 if (SDValue Ret = TryMULWIDECombine(N, DCI))
4347 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4348 DAGCombinerInfo &DCI) const {
4349 CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4350 switch (N->getOpcode()) {
4354 return PerformADDCombine(N, DCI, STI, OptLevel);
4356 return PerformMULCombine(N, DCI, OptLevel);
4358 return PerformSHLCombine(N, DCI, OptLevel);
4360 return PerformANDCombine(N, DCI);
4362 return PerformSELECTCombine(N, DCI);
4365 return PerformREMCombine(N, DCI, OptLevel);
4370 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4371 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4372 SmallVectorImpl<SDValue> &Results) {
4373 EVT ResVT = N->getValueType(0);
4376 assert(ResVT.isVector() && "Vector load must have vector type");
4378 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4379 // legal. We can (and should) split that into 2 loads of <2 x double> here
4380 // but I'm leaving that as a TODO for now.
4381 assert(ResVT.isSimple() && "Can only handle simple types");
4382 switch (ResVT.getSimpleVT().SimpleTy) {
4395 // This is a "native" vector type
4399 LoadSDNode *LD = cast<LoadSDNode>(N);
4401 unsigned Align = LD->getAlignment();
4402 auto &TD = DAG.getDataLayout();
4403 unsigned PrefAlign =
4404 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4405 if (Align < PrefAlign) {
4406 // This load is not sufficiently aligned, so bail out and let this vector
4407 // load be scalarized. Note that we may still be able to emit smaller
4408 // vector loads. For example, if we are loading a <4 x float> with an
4409 // alignment of 8, this check will fail but the legalizer will try again
4410 // with 2 x <2 x float>, which will succeed with an alignment of 8.
4414 EVT EltVT = ResVT.getVectorElementType();
4415 unsigned NumElts = ResVT.getVectorNumElements();
4417 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4418 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4419 // loaded type to i16 and propagate the "real" type as the memory type.
4420 bool NeedTrunc = false;
4421 if (EltVT.getSizeInBits() < 16) {
4426 unsigned Opcode = 0;
4433 Opcode = NVPTXISD::LoadV2;
4434 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4437 Opcode = NVPTXISD::LoadV4;
4438 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4439 LdResVTs = DAG.getVTList(ListVTs);
4444 // Copy regular operands
4445 SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4447 // The select routine does not have access to the LoadSDNode instance, so
4448 // pass along the extension information
4449 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4451 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4453 LD->getMemOperand());
4455 SmallVector<SDValue, 4> ScalarRes;
4457 for (unsigned i = 0; i < NumElts; ++i) {
4458 SDValue Res = NewLD.getValue(i);
4460 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4461 ScalarRes.push_back(Res);
4464 SDValue LoadChain = NewLD.getValue(NumElts);
4466 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes);
4468 Results.push_back(BuildVec);
4469 Results.push_back(LoadChain);
4472 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4473 SmallVectorImpl<SDValue> &Results) {
4474 SDValue Chain = N->getOperand(0);
4475 SDValue Intrin = N->getOperand(1);
4478 // Get the intrinsic ID
4479 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4483 case Intrinsic::nvvm_ldg_global_i:
4484 case Intrinsic::nvvm_ldg_global_f:
4485 case Intrinsic::nvvm_ldg_global_p:
4486 case Intrinsic::nvvm_ldu_global_i:
4487 case Intrinsic::nvvm_ldu_global_f:
4488 case Intrinsic::nvvm_ldu_global_p: {
4489 EVT ResVT = N->getValueType(0);
4491 if (ResVT.isVector()) {
4494 unsigned NumElts = ResVT.getVectorNumElements();
4495 EVT EltVT = ResVT.getVectorElementType();
4497 // Since LDU/LDG are target nodes, we cannot rely on DAG type
4499 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4500 // loaded type to i16 and propagate the "real" type as the memory type.
4501 bool NeedTrunc = false;
4502 if (EltVT.getSizeInBits() < 16) {
4507 unsigned Opcode = 0;
4517 case Intrinsic::nvvm_ldg_global_i:
4518 case Intrinsic::nvvm_ldg_global_f:
4519 case Intrinsic::nvvm_ldg_global_p:
4520 Opcode = NVPTXISD::LDGV2;
4522 case Intrinsic::nvvm_ldu_global_i:
4523 case Intrinsic::nvvm_ldu_global_f:
4524 case Intrinsic::nvvm_ldu_global_p:
4525 Opcode = NVPTXISD::LDUV2;
4528 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4534 case Intrinsic::nvvm_ldg_global_i:
4535 case Intrinsic::nvvm_ldg_global_f:
4536 case Intrinsic::nvvm_ldg_global_p:
4537 Opcode = NVPTXISD::LDGV4;
4539 case Intrinsic::nvvm_ldu_global_i:
4540 case Intrinsic::nvvm_ldu_global_f:
4541 case Intrinsic::nvvm_ldu_global_p:
4542 Opcode = NVPTXISD::LDUV4;
4545 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4546 LdResVTs = DAG.getVTList(ListVTs);
4551 SmallVector<SDValue, 8> OtherOps;
4553 // Copy regular operands
4555 OtherOps.push_back(Chain); // Chain
4556 // Skip operand 1 (intrinsic ID)
4558 OtherOps.append(N->op_begin() + 2, N->op_end());
4560 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4562 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4563 MemSD->getMemoryVT(),
4564 MemSD->getMemOperand());
4566 SmallVector<SDValue, 4> ScalarRes;
4568 for (unsigned i = 0; i < NumElts; ++i) {
4569 SDValue Res = NewLD.getValue(i);
4572 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4573 ScalarRes.push_back(Res);
4576 SDValue LoadChain = NewLD.getValue(NumElts);
4579 DAG.getBuildVector(ResVT, DL, ScalarRes);
4581 Results.push_back(BuildVec);
4582 Results.push_back(LoadChain);
4585 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4586 "Custom handling of non-i8 ldu/ldg?");
4588 // Just copy all operands as-is
4589 SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4591 // Force output to i16
4592 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4594 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4596 // We make sure the memory type is i8, which will be used during isel
4597 // to select the proper instruction.
4599 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4600 MVT::i8, MemSD->getMemOperand());
4602 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4603 NewLD.getValue(0)));
4604 Results.push_back(NewLD.getValue(1));
4610 void NVPTXTargetLowering::ReplaceNodeResults(
4611 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4612 switch (N->getOpcode()) {
4614 report_fatal_error("Unhandled custom legalization");
4616 ReplaceLoadVector(N, DAG, Results);
4618 case ISD::INTRINSIC_W_CHAIN:
4619 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4624 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4625 void NVPTXSection::anchor() {}
4627 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4628 delete static_cast<NVPTXSection *>(TextSection);
4629 delete static_cast<NVPTXSection *>(DataSection);
4630 delete static_cast<NVPTXSection *>(BSSSection);
4631 delete static_cast<NVPTXSection *>(ReadOnlySection);
4633 delete static_cast<NVPTXSection *>(StaticCtorSection);
4634 delete static_cast<NVPTXSection *>(StaticDtorSection);
4635 delete static_cast<NVPTXSection *>(LSDASection);
4636 delete static_cast<NVPTXSection *>(EHFrameSection);
4637 delete static_cast<NVPTXSection *>(DwarfAbbrevSection);
4638 delete static_cast<NVPTXSection *>(DwarfInfoSection);
4639 delete static_cast<NVPTXSection *>(DwarfLineSection);
4640 delete static_cast<NVPTXSection *>(DwarfFrameSection);
4641 delete static_cast<NVPTXSection *>(DwarfPubTypesSection);
4642 delete static_cast<const NVPTXSection *>(DwarfDebugInlineSection);
4643 delete static_cast<NVPTXSection *>(DwarfStrSection);
4644 delete static_cast<NVPTXSection *>(DwarfLocSection);
4645 delete static_cast<NVPTXSection *>(DwarfARangesSection);
4646 delete static_cast<NVPTXSection *>(DwarfRangesSection);
4647 delete static_cast<NVPTXSection *>(DwarfMacinfoSection);
4650 MCSection *NVPTXTargetObjectFile::SelectSectionForGlobal(
4651 const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
4652 return getDataSection();