1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
19 #include "NVPTXSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
55 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
69 StoreParamS32, // to sext and store a <32bit value, not used currently
70 StoreParamU32, // to zext and store a <32bit value, not used currently
77 //===--------------------------------------------------------------------===//
78 // TargetLowering Implementation
79 //===--------------------------------------------------------------------===//
80 class NVPTXTargetLowering : public TargetLowering {
82 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
83 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
87 SelectionDAG &DAG) const;
89 virtual const char *getTargetNodeName(unsigned Opcode) const;
91 bool isTypeSupportedInIntrinsic(MVT VT) const;
93 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
94 unsigned Intrinsic) const;
96 /// isLegalAddressingMode - Return true if the addressing mode represented
97 /// by AM is legal for this target, for a load/store of the specified type
98 /// Used to guide target specific optimizations, like loop strength
99 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
100 /// address mode (CodeGenPrepare.cpp)
101 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
103 /// getFunctionAlignment - Return the Log2 alignment of this function.
104 virtual unsigned getFunctionAlignment(const Function *F) const;
106 virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
108 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
112 ConstraintType getConstraintType(const std::string &Constraint) const;
113 std::pair<unsigned, const TargetRegisterClass *>
114 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
116 virtual SDValue LowerFormalArguments(
117 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
118 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
119 SmallVectorImpl<SDValue> &InVals) const;
122 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
124 std::string getPrototype(Type *, const ArgListTy &,
125 const SmallVectorImpl<ISD::OutputArg> &,
126 unsigned retAlignment,
127 const ImmutableCallSite *CS) const;
130 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
132 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
133 SelectionDAG &DAG) const;
135 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
136 std::vector<SDValue> &Ops,
137 SelectionDAG &DAG) const;
139 NVPTXTargetMachine *nvTM;
141 // PTX always uses 32-bit shift amounts
142 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
144 virtual bool shouldSplitVectorElementType(EVT VT) const;
147 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
149 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
150 EVT = MVT::i32) const;
151 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
152 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
154 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
163 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
164 SelectionDAG &DAG) const;
166 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
167 Type *Ty, unsigned Idx) const;
171 #endif // NVPTXISELLOWERING_H