1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "NVPTXInstrInfo.h"
16 #include "NVPTXTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
25 #define GET_INSTRINFO_CTOR_DTOR
26 #include "NVPTXGenInstrInfo.inc"
28 // Pin the vtable to this file.
29 void NVPTXInstrInfo::anchor() {}
31 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
33 void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator I,
35 const DebugLoc &DL, unsigned DestReg,
36 unsigned SrcReg, bool KillSrc) const {
37 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
41 if (DestRC->getSize() != SrcRC->getSize())
42 report_fatal_error("Copy one register into another with a different width");
45 if (DestRC == &NVPTX::Int1RegsRegClass) {
47 } else if (DestRC == &NVPTX::Int16RegsRegClass) {
49 } else if (DestRC == &NVPTX::Int32RegsRegClass) {
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
51 : NVPTX::BITCONVERT_32_F2I);
52 } else if (DestRC == &NVPTX::Int64RegsRegClass) {
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
54 : NVPTX::BITCONVERT_64_F2I);
55 } else if (DestRC == &NVPTX::Float32RegsRegClass) {
56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
57 : NVPTX::BITCONVERT_32_I2F);
58 } else if (DestRC == &NVPTX::Float64RegsRegClass) {
59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
60 : NVPTX::BITCONVERT_64_I2F);
62 llvm_unreachable("Bad register copy");
64 BuildMI(MBB, I, DL, get(Op), DestReg)
65 .addReg(SrcReg, getKillRegState(KillSrc));
68 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
69 unsigned &DestReg) const {
70 // Look for the appropriate part of TSFlags
74 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
75 isMove = (TSFlags == 1);
78 MachineOperand dest = MI.getOperand(0);
79 MachineOperand src = MI.getOperand(1);
80 assert(dest.isReg() && "dest of a movrr is not a reg");
81 assert(src.isReg() && "src of a movrr is not a reg");
83 SrcReg = src.getReg();
84 DestReg = dest.getReg();
91 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
92 unsigned &AddrSpace) const {
95 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
96 isLoad = (TSFlags == 1);
98 AddrSpace = getLdStCodeAddrSpace(MI);
102 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
103 unsigned &AddrSpace) const {
104 bool isStore = false;
106 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
107 isStore = (TSFlags == 1);
109 AddrSpace = getLdStCodeAddrSpace(MI);
113 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
114 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
115 /// implemented for a target). Upon success, this returns false and returns
116 /// with the following information in various cases:
118 /// 1. If this block ends with no branches (it just falls through to its succ)
119 /// just return false, leaving TBB/FBB null.
120 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
121 /// the destination block.
122 /// 3. If this block ends with an conditional branch and it falls through to
123 /// an successor block, it sets TBB to be the branch destination block and a
124 /// list of operands that evaluate the condition. These
125 /// operands can be passed to other TargetInstrInfo methods to create new
127 /// 4. If this block ends with an conditional branch and an unconditional
128 /// block, it returns the 'true' destination in TBB, the 'false' destination
129 /// in FBB, and a list of operands that evaluate the condition. These
130 /// operands can be passed to other TargetInstrInfo methods to create new
133 /// Note that removeBranch and insertBranch must be implemented to support
134 /// cases where this method returns success.
136 bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
137 MachineBasicBlock *&TBB,
138 MachineBasicBlock *&FBB,
139 SmallVectorImpl<MachineOperand> &Cond,
140 bool AllowModify) const {
141 // If the block has no terminators, it just falls into the block after it.
142 MachineBasicBlock::iterator I = MBB.end();
143 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I))
146 // Get the last instruction in the block.
147 MachineInstr &LastInst = *I;
149 // If there is only one terminator instruction, process it.
150 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
151 if (LastInst.getOpcode() == NVPTX::GOTO) {
152 TBB = LastInst.getOperand(0).getMBB();
154 } else if (LastInst.getOpcode() == NVPTX::CBranch) {
155 // Block ends with fall-through condbranch.
156 TBB = LastInst.getOperand(1).getMBB();
157 Cond.push_back(LastInst.getOperand(0));
160 // Otherwise, don't know what this is.
164 // Get the instruction before it if it's a terminator.
165 MachineInstr &SecondLastInst = *I;
167 // If there are three terminators, we don't know what sort of block this is.
168 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
171 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
172 if (SecondLastInst.getOpcode() == NVPTX::CBranch &&
173 LastInst.getOpcode() == NVPTX::GOTO) {
174 TBB = SecondLastInst.getOperand(1).getMBB();
175 Cond.push_back(SecondLastInst.getOperand(0));
176 FBB = LastInst.getOperand(0).getMBB();
180 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
181 // executed, so remove it.
182 if (SecondLastInst.getOpcode() == NVPTX::GOTO &&
183 LastInst.getOpcode() == NVPTX::GOTO) {
184 TBB = SecondLastInst.getOperand(0).getMBB();
187 I->eraseFromParent();
191 // Otherwise, can't handle this.
195 unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
196 int *BytesRemoved) const {
197 assert(!BytesRemoved && "code size not handled");
198 MachineBasicBlock::iterator I = MBB.end();
199 if (I == MBB.begin())
202 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
205 // Remove the branch.
206 I->eraseFromParent();
210 if (I == MBB.begin())
213 if (I->getOpcode() != NVPTX::CBranch)
216 // Remove the branch.
217 I->eraseFromParent();
221 unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
222 MachineBasicBlock *TBB,
223 MachineBasicBlock *FBB,
224 ArrayRef<MachineOperand> Cond,
226 int *BytesAdded) const {
227 assert(!BytesAdded && "code size not handled");
229 // Shouldn't be a fall through.
230 assert(TBB && "insertBranch must not be told to insert a fallthrough");
231 assert((Cond.size() == 1 || Cond.size() == 0) &&
232 "NVPTX branch conditions have two components!");
236 if (Cond.empty()) // Unconditional branch
237 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
238 else // Conditional branch
239 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
244 // Two-way Conditional Branch.
245 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
246 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);