1 //===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the niversity of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
18 #include "NVPTXRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "NVPTXGenInstrInfo.inc"
26 class NVPTXInstrInfo : public NVPTXGenInstrInfo {
27 const NVPTXRegisterInfo RegInfo;
28 virtual void anchor();
30 explicit NVPTXInstrInfo();
32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
34 /* The following virtual functions are used in register allocation.
35 * They are not implemented because the existing interface and the logic
36 * at the caller side do not work for the elementized vector load and store.
38 * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
39 * int &FrameIndex) const;
40 * virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
41 * int &FrameIndex) const;
42 * virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
43 * MachineBasicBlock::iterator MBBI,
44 * unsigned SrcReg, bool isKill, int FrameIndex,
45 * const TargetRegisterClass *RC) const;
46 * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
47 * MachineBasicBlock::iterator MBBI,
48 * unsigned DestReg, int FrameIndex,
49 * const TargetRegisterClass *RC) const;
52 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
54 bool KillSrc) const override;
55 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
56 unsigned &DestReg) const;
57 bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
58 bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
61 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62 MachineBasicBlock *&FBB,
63 SmallVectorImpl<MachineOperand> &Cond,
64 bool AllowModify) const override;
65 unsigned removeBranch(MachineBasicBlock &MBB,
66 int *BytesRemoved = nullptr) const override;
67 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
68 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
70 int *BytesAdded = nullptr) const override;
71 unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
72 return MI.getOperand(2).getImm();