1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXRegisterInfo.h"
16 #include "NVPTXSubtarget.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/MC/MachineLocation.h"
22 #include "llvm/Target/TargetInstrInfo.h"
26 #define DEBUG_TYPE "nvptx-reg-info"
29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
30 if (RC == &NVPTX::Float32RegsRegClass)
32 if (RC == &NVPTX::Float16RegsRegClass)
33 // Ideally fp16 registers should be .f16, but this syntax is only
34 // supported on sm_53+. On the other hand, .b16 registers are
35 // accepted for all supported fp16 instructions on all GPU
36 // variants, so we can use them instead.
38 if (RC == &NVPTX::Float16x2RegsRegClass)
40 if (RC == &NVPTX::Float64RegsRegClass)
42 if (RC == &NVPTX::Int64RegsRegClass)
43 // We use untyped (.b) integer registers here as NVCC does.
44 // Correctness of generated code does not depend on register type,
45 // but using .s/.u registers runs into ptxas bug that prevents
46 // assembly of otherwise valid PTX into SASS. Despite PTX ISA
47 // specifying only argument size for fp16 instructions, ptxas does
48 // not allow using .s16 or .u16 arguments for .fp16
49 // instructions. At the same time it allows using .s32/.u32
50 // arguments for .fp16v2 instructions:
54 // add.f16 rb16,rb16,rb16; // OK
55 // add.f16 rs16,rs16,rs16; // Arguments mismatch for instruction 'add'
59 // add.f16v2 rb32,rb32,rb32; // OK
60 // add.f16v2 rs32,rs32,rs32; // OK
62 if (RC == &NVPTX::Int32RegsRegClass)
64 if (RC == &NVPTX::Int16RegsRegClass)
66 if (RC == &NVPTX::Int1RegsRegClass)
68 if (RC == &NVPTX::SpecialRegsRegClass)
73 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
74 if (RC == &NVPTX::Float32RegsRegClass)
76 if (RC == &NVPTX::Float16RegsRegClass)
78 if (RC == &NVPTX::Float16x2RegsRegClass)
80 if (RC == &NVPTX::Float64RegsRegClass)
82 if (RC == &NVPTX::Int64RegsRegClass)
84 if (RC == &NVPTX::Int32RegsRegClass)
86 if (RC == &NVPTX::Int16RegsRegClass)
88 if (RC == &NVPTX::Int1RegsRegClass)
90 if (RC == &NVPTX::SpecialRegsRegClass)
96 NVPTXRegisterInfo::NVPTXRegisterInfo() : NVPTXGenRegisterInfo(0) {}
98 #define GET_REGINFO_TARGET_DESC
99 #include "NVPTXGenRegisterInfo.inc"
101 /// NVPTX Callee Saved Registers
103 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
104 static const MCPhysReg CalleeSavedRegs[] = { 0 };
105 return CalleeSavedRegs;
108 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
109 BitVector Reserved(getNumRegs());
113 void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
114 int SPAdj, unsigned FIOperandNum,
115 RegScavenger *RS) const {
116 assert(SPAdj == 0 && "Unexpected");
118 MachineInstr &MI = *II;
119 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
121 MachineFunction &MF = *MI.getParent()->getParent();
122 int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
123 MI.getOperand(FIOperandNum + 1).getImm();
125 // Using I0 as the frame pointer
126 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
127 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
130 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
131 return NVPTX::VRFrame;