1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
15 #include "NVPTXAllocaHoisting.h"
16 #include "NVPTXLowerAggrCopies.h"
17 #include "NVPTXTargetMachine.h"
18 #include "NVPTXTargetObjectFile.h"
19 #include "NVPTXTargetTransformInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/TargetPassConfig.h"
25 #include "llvm/IR/LegacyPassManager.h"
26 #include "llvm/Pass.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
32 #include "llvm/Transforms/Scalar.h"
33 #include "llvm/Transforms/Scalar/GVN.h"
34 #include "llvm/Transforms/Vectorize.h"
40 // LSV is still relatively new; this switch lets us turn it off in case we
41 // encounter (or suspect) a bug.
43 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
44 cl::desc("Disable load/store vectorizer"),
45 cl::init(false), cl::Hidden);
49 void initializeNVVMIntrRangePass(PassRegistry&);
50 void initializeNVVMReflectPass(PassRegistry&);
51 void initializeGenericToNVVMPass(PassRegistry&);
52 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
53 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
54 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
55 void initializeNVPTXLowerArgsPass(PassRegistry &);
56 void initializeNVPTXLowerAllocaPass(PassRegistry &);
58 } // end namespace llvm
60 extern "C" void LLVMInitializeNVPTXTarget() {
61 // Register the target.
62 RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
63 RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
65 // FIXME: This pass is really intended to be invoked during IR optimization,
66 // but it's very NVPTX-specific.
67 PassRegistry &PR = *PassRegistry::getPassRegistry();
68 initializeNVVMReflectPass(PR);
69 initializeNVVMIntrRangePass(PR);
70 initializeGenericToNVVMPass(PR);
71 initializeNVPTXAllocaHoistingPass(PR);
72 initializeNVPTXAssignValidGlobalNamesPass(PR);
73 initializeNVPTXLowerArgsPass(PR);
74 initializeNVPTXLowerAllocaPass(PR);
75 initializeNVPTXLowerAggrCopiesPass(PR);
78 static std::string computeDataLayout(bool is64Bit) {
79 std::string Ret = "e";
84 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
89 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
90 StringRef CPU, StringRef FS,
91 const TargetOptions &Options,
92 Optional<Reloc::Model> RM,
94 CodeGenOpt::Level OL, bool is64bit)
95 // The pic relocation model is used regardless of what the client has
96 // specified, as it is the only relocation model currently supported.
97 : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
100 TLOF(llvm::make_unique<NVPTXTargetObjectFile>()),
101 Subtarget(TT, CPU, FS, *this) {
102 if (TT.getOS() == Triple::NVCL)
103 drvInterface = NVPTX::NVCL;
105 drvInterface = NVPTX::CUDA;
109 NVPTXTargetMachine::~NVPTXTargetMachine() = default;
111 void NVPTXTargetMachine32::anchor() {}
113 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
114 StringRef CPU, StringRef FS,
115 const TargetOptions &Options,
116 Optional<Reloc::Model> RM,
118 CodeGenOpt::Level OL)
119 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
121 void NVPTXTargetMachine64::anchor() {}
123 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
124 StringRef CPU, StringRef FS,
125 const TargetOptions &Options,
126 Optional<Reloc::Model> RM,
128 CodeGenOpt::Level OL)
129 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
133 class NVPTXPassConfig : public TargetPassConfig {
135 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
136 : TargetPassConfig(TM, PM) {}
138 NVPTXTargetMachine &getNVPTXTargetMachine() const {
139 return getTM<NVPTXTargetMachine>();
142 void addIRPasses() override;
143 bool addInstSelector() override;
144 void addPostRegAlloc() override;
145 void addMachineSSAOptimization() override;
147 FunctionPass *createTargetRegisterAllocator(bool) override;
148 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
149 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
152 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
153 // function is only called in opt mode.
154 void addEarlyCSEOrGVNPass();
156 // Add passes that propagate special memory spaces.
157 void addAddressSpaceInferencePasses();
159 // Add passes that perform straight-line scalar optimizations.
160 void addStraightLineScalarOptimizationPasses();
163 } // end anonymous namespace
165 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
166 return new NVPTXPassConfig(this, PM);
169 void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
170 Builder.addExtension(
171 PassManagerBuilder::EP_EarlyAsPossible,
172 [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
173 PM.add(createNVVMReflectPass());
174 PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
178 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
179 return TargetIRAnalysis([this](const Function &F) {
180 return TargetTransformInfo(NVPTXTTIImpl(this, F));
184 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
185 if (getOptLevel() == CodeGenOpt::Aggressive)
186 addPass(createGVNPass());
188 addPass(createEarlyCSEPass());
191 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
192 // NVPTXLowerArgs emits alloca for byval parameters which can often
193 // be eliminated by SROA.
194 addPass(createSROAPass());
195 addPass(createNVPTXLowerAllocaPass());
196 addPass(createInferAddressSpacesPass());
199 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
200 addPass(createSeparateConstOffsetFromGEPPass());
201 addPass(createSpeculativeExecutionPass());
202 // ReassociateGEPs exposes more opportunites for SLSR. See
203 // the example in reassociate-geps-and-slsr.ll.
204 addPass(createStraightLineStrengthReducePass());
205 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
206 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
207 // for some of our benchmarks.
208 addEarlyCSEOrGVNPass();
209 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
210 addPass(createNaryReassociatePass());
211 // NaryReassociate on GEPs creates redundant common expressions, so run
212 // EarlyCSE after it.
213 addPass(createEarlyCSEPass());
216 void NVPTXPassConfig::addIRPasses() {
217 // The following passes are known to not play well with virtual regs hanging
218 // around after register allocation (which in our case, is *all* registers).
219 // We explicitly disable them here. We do, however, need some functionality
220 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
221 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
222 disablePass(&PrologEpilogCodeInserterID);
223 disablePass(&MachineCopyPropagationID);
224 disablePass(&TailDuplicateID);
225 disablePass(&StackMapLivenessID);
226 disablePass(&LiveDebugValuesID);
227 disablePass(&PostRASchedulerID);
228 disablePass(&FuncletLayoutID);
229 disablePass(&PatchableFunctionID);
231 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
232 // it here does nothing. But since we need it for correctness when lowering
233 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
234 // call addEarlyAsPossiblePasses.
235 addPass(createNVVMReflectPass());
237 if (getOptLevel() != CodeGenOpt::None)
238 addPass(createNVPTXImageOptimizerPass());
239 addPass(createNVPTXAssignValidGlobalNamesPass());
240 addPass(createGenericToNVVMPass());
242 // NVPTXLowerArgs is required for correctness and should be run right
243 // before the address space inference passes.
244 addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
245 if (getOptLevel() != CodeGenOpt::None) {
246 addAddressSpaceInferencePasses();
247 if (!DisableLoadStoreVectorizer)
248 addPass(createLoadStoreVectorizerPass());
249 addStraightLineScalarOptimizationPasses();
252 // === LSR and other generic IR passes ===
253 TargetPassConfig::addIRPasses();
254 // EarlyCSE is not always strong enough to clean up what LSR produces. For
255 // example, GVN can combine
262 // %0 = shl nsw %a, 2
265 // but EarlyCSE can do neither of them.
266 if (getOptLevel() != CodeGenOpt::None)
267 addEarlyCSEOrGVNPass();
270 bool NVPTXPassConfig::addInstSelector() {
271 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
273 addPass(createLowerAggrCopies());
274 addPass(createAllocaHoisting());
275 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
277 if (!ST.hasImageHandles())
278 addPass(createNVPTXReplaceImageHandlesPass());
283 void NVPTXPassConfig::addPostRegAlloc() {
284 addPass(createNVPTXPrologEpilogPass(), false);
285 if (getOptLevel() != CodeGenOpt::None) {
286 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
287 // index with VRFrame register. NVPTXPeephole need to be run after that and
288 // will replace VRFrame with VRFrameLocal when possible.
289 addPass(createNVPTXPeephole());
293 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
294 return nullptr; // No reg alloc
297 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
298 assert(!RegAllocPass && "NVPTX uses no regalloc!");
299 addPass(&PHIEliminationID);
300 addPass(&TwoAddressInstructionPassID);
303 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
304 assert(!RegAllocPass && "NVPTX uses no regalloc!");
306 addPass(&ProcessImplicitDefsID);
307 addPass(&LiveVariablesID);
308 addPass(&MachineLoopInfoID);
309 addPass(&PHIEliminationID);
311 addPass(&TwoAddressInstructionPassID);
312 addPass(&RegisterCoalescerID);
314 // PreRA instruction scheduling.
315 if (addPass(&MachineSchedulerID))
316 printAndVerify("After Machine Scheduling");
319 addPass(&StackSlotColoringID);
321 // FIXME: Needs physical registers
322 //addPass(&PostRAMachineLICMID);
324 printAndVerify("After StackSlotColoring");
327 void NVPTXPassConfig::addMachineSSAOptimization() {
328 // Pre-ra tail duplication.
329 if (addPass(&EarlyTailDuplicateID))
330 printAndVerify("After Pre-RegAlloc TailDuplicate");
332 // Optimize PHIs before DCE: removing dead PHI cycles may make more
333 // instructions dead.
334 addPass(&OptimizePHIsID);
336 // This pass merges large allocas. StackSlotColoring is a different pass
337 // which merges spill slots.
338 addPass(&StackColoringID);
340 // If the target requests it, assign local variables to stack slots relative
341 // to one another and simplify frame index references where possible.
342 addPass(&LocalStackSlotAllocationID);
344 // With optimization, dead code should already be eliminated. However
345 // there is one known exception: lowered code for arguments that are only
346 // used by tail calls, where the tail calls reuse the incoming stack
347 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
348 addPass(&DeadMachineInstructionElimID);
349 printAndVerify("After codegen DCE pass");
351 // Allow targets to insert passes that improve instruction level parallelism,
352 // like if-conversion. Such passes will typically need dominator trees and
353 // loop info, just like LICM and CSE below.
355 printAndVerify("After ILP optimizations");
357 addPass(&MachineLICMID);
358 addPass(&MachineCSEID);
360 addPass(&MachineSinkingID);
361 printAndVerify("After Machine LICM, CSE and Sinking passes");
363 addPass(&PeepholeOptimizerID);
364 printAndVerify("After codegen peephole optimization pass");