1 //===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// NVPTX target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
21 #include "NVPTXTargetMachine.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/BasicTTIImpl.h"
24 #include "llvm/CodeGen/TargetLowering.h"
28 class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
29 typedef BasicTTIImplBase<NVPTXTTIImpl> BaseT;
30 typedef TargetTransformInfo TTI;
33 const NVPTXSubtarget *ST;
34 const NVPTXTargetLowering *TLI;
36 const NVPTXSubtarget *getST() const { return ST; };
37 const NVPTXTargetLowering *getTLI() const { return TLI; };
40 explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
42 TLI(ST->getTargetLowering()) {}
44 bool hasBranchDivergence() { return true; }
46 bool isSourceOfDivergence(const Value *V);
48 unsigned getFlatAddressSpace() const {
49 return AddressSpace::ADDRESS_SPACE_GENERIC;
52 // Loads and stores can be vectorized if the alignment is at least as big as
53 // the load/store we want to vectorize.
54 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
56 unsigned AddrSpace) const {
57 return Alignment >= ChainSizeInBytes;
59 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
61 unsigned AddrSpace) const {
62 return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace);
65 // NVPTX has infinite registers of all kinds, but the actual machine doesn't.
66 // We conservatively return 1 here which is just enough to enable the
67 // vectorizers but disables heuristics based on the number of registers.
68 // FIXME: Return a more reasonable number, while keeping an eye on
69 // LoopVectorizer's unrolling heuristics.
70 unsigned getNumberOfRegisters(bool Vector) const { return 1; }
72 // Only <2 x half> should be vectorized, so always return 32 for the vector
74 unsigned getRegisterBitWidth(bool Vector) const { return 32; }
75 unsigned getMinVectorRegisterBitWidth() const { return 32; }
77 // We don't want to prevent inlining because of target-cpu and -features
78 // attributes that were added to newer versions of LLVM/Clang: There are
79 // no incompatible functions in PTX, ptxas will throw errors in such cases.
80 bool areInlineCompatible(const Function *Caller,
81 const Function *Callee) const {
85 // Increase the inlining cost threshold by a factor of 5, reflecting that
86 // calls are particularly expensive in NVPTX.
87 unsigned getInliningThresholdMultiplier() { return 5; }
89 int getArithmeticInstrCost(
90 unsigned Opcode, Type *Ty,
91 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
92 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
93 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
94 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
95 ArrayRef<const Value *> Args = ArrayRef<const Value *>());
97 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
98 TTI::UnrollingPreferences &UP);
99 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) {
100 // Volatile loads/stores are only supported for shared and global address
101 // spaces, or for generic AS that maps to them.
102 if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC ||
103 AddrSpace == llvm::ADDRESS_SPACE_GLOBAL ||
104 AddrSpace == llvm::ADDRESS_SPACE_SHARED))
107 switch(I->getOpcode()){
110 case Instruction::Load:
111 case Instruction::Store:
117 } // end namespace llvm