1 //===- Nios2InstrInfo.td - Target Description for Nios2 ------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Nios2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "Nios2InstrFormats.td"
21 //===----------------------------------------------------------------------===//
22 // Nios2 Operand, Complex Patterns and Transformations Definitions.
23 //===----------------------------------------------------------------------===//
25 def simm16 : Operand<i32> {
26 let DecoderMethod= "DecodeSimm16";
29 // Node immediate fits as 16-bit sign extended on target immediate.
31 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
33 //===----------------------------------------------------------------------===//
34 // Instructions specific format
35 //===----------------------------------------------------------------------===//
37 // Arithmetic and logical instructions with 2 registers and 16-bit immediate
39 multiclass ArithLogicRegImm16<bits<6> op, string mnemonic, SDNode opNode,
40 Operand immOp, PatLeaf immType>:
41 CommonInstr_I_F2I16<op, (outs CPURegs:$rB),
42 (ins CPURegs:$rA, immOp:$imm),
43 !strconcat(mnemonic, "\t$rB, $rA, $imm"),
45 (opNode CPURegs:$rA, immType:$imm))],
48 multiclass Return<bits<6> opx, dag outs, dag ins, string mnemonic> {
53 hasExtraSrcRegAllocReq = 1 in {
54 defm NAME# : CommonInstr_R_F3X6<opx, outs, ins, mnemonic, [], IIBranch>;
58 // Custom return SDNode
59 def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
60 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
62 //===----------------------------------------------------------------------===//
64 //===----------------------------------------------------------------------===//
66 /// Arithmetic Instructions (ALU Immediate)
67 defm ADDI : ArithLogicRegImm16<0x04, "addi", add, simm16, immSExt16>;
70 defm RET : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
72 //===----------------------------------------------------------------------===//
73 // Pseudo instructions
74 //===----------------------------------------------------------------------===//
77 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
78 def RetRA : Nios2Pseudo<(outs), (ins), "", [(Nios2Ret)]>;