1 //===- Nios2InstrInfo.td - Target Description for Nios2 ------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Nios2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "Nios2InstrFormats.td"
21 //===----------------------------------------------------------------------===//
22 // Nios2 Operand, Complex Patterns and Transformations Definitions.
23 //===----------------------------------------------------------------------===//
25 def simm16 : Operand<i32> {
26 let DecoderMethod= "DecodeSimm16";
29 // Node immediate fits as 16-bit sign extended on target immediate.
31 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
33 // Custom return SDNode
34 def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
35 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
37 //===----------------------------------------------------------------------===//
38 // Instructions specific format
39 //===----------------------------------------------------------------------===//
41 // Arithmetic and logical instructions with 2 registers and 16-bit immediate
43 multiclass ArithLogicRegImm16<bits<6> op, string mnemonic, SDNode opNode,
44 Operand immOp, PatLeaf immType>:
45 CommonInstr_I_F2I16<op, (outs CPURegs:$rB),
46 (ins CPURegs:$rA, immOp:$imm),
47 !strconcat(mnemonic, "\t$rB, $rA, $imm"),
49 (opNode CPURegs:$rA, immType:$imm))],
52 // Arithmetic and logical instructions with 3 register operands.
53 // Defines R1 and R2 instruction at the same time.
54 multiclass ArithLogicReg<bits<6> opx, string mnemonic,
56 CommonInstr_R_F3X6<opx, (outs CPURegs:$rC),
57 (ins CPURegs:$rA, CPURegs:$rB),
58 !strconcat(mnemonic, "\t$rC, $rA, $rB"),
59 [(set CPURegs:$rC, (opNode CPURegs:$rA, CPURegs:$rB))],
62 multiclass Return<bits<6> opx, dag outs, dag ins, string mnemonic> {
67 hasExtraSrcRegAllocReq = 1 in {
68 defm NAME# : CommonInstr_R_F3X6<opx, outs, ins, mnemonic, [], IIBranch>;
72 //===----------------------------------------------------------------------===//
74 //===----------------------------------------------------------------------===//
76 /// Arithmetic instructions operating on registers.
77 let isCommutable = 1 ,
78 isReMaterializable = 1 in {
79 defm ADD : ArithLogicReg<0x31, "add", add>;
80 defm AND : ArithLogicReg<0x0e, "and", and>;
81 defm OR : ArithLogicReg<0x16, "or", or>;
82 defm XOR : ArithLogicReg<0x1e, "xor", xor>;
83 defm MUL : ArithLogicReg<0x27, "mul", mul>;
86 let isReMaterializable = 1 in {
87 defm SUB : ArithLogicReg<0x39, "sub", sub>;
90 defm DIVU : ArithLogicReg<0x24, "divu", udiv>;
91 defm DIV : ArithLogicReg<0x25, "div", sdiv>;
93 defm SLL : ArithLogicReg<0x13, "sll", shl>;
94 defm SRL : ArithLogicReg<0x1b, "srl", srl>;
95 defm SRA : ArithLogicReg<0x3b, "sra", sra>;
97 /// Arithmetic Instructions (ALU Immediate)
98 defm ADDI : ArithLogicRegImm16<0x04, "addi", add, simm16, immSExt16>;
101 defm RET : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
103 //===----------------------------------------------------------------------===//
104 // Pseudo instructions
105 //===----------------------------------------------------------------------===//
108 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
109 def RetRA : Nios2Pseudo<(outs), (ins), "", [(Nios2Ret)]>;