1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstPrinter.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCInstrInfo.h"
18 #include "llvm/CodeGen/TargetOpcodes.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "asm-printer"
31 // FIXME: Once the integrated assembler supports full register names, tie this
32 // to the verbose-asm setting.
34 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
35 cl::desc("Use full register names when printing assembly"));
37 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
39 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
40 cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
42 // Prints full register names with percent symbol.
44 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
46 cl::desc("Prints full register names with percent"));
48 #define PRINT_ALIAS_INSTR
49 #include "PPCGenAsmWriter.inc"
51 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
52 const char *RegName = getRegisterName(RegNo);
53 if (RegName[0] == 'q' /* QPX */) {
54 // The system toolchain on the BG/Q does not understand QPX register names
55 // in .cfi_* directives, so print the name of the floating-point
56 // subregister instead.
57 std::string RN(RegName);
68 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
69 StringRef Annot, const MCSubtargetInfo &STI) {
70 // Check for slwi/srwi mnemonics.
71 if (MI->getOpcode() == PPC::RLWINM) {
72 unsigned char SH = MI->getOperand(2).getImm();
73 unsigned char MB = MI->getOperand(3).getImm();
74 unsigned char ME = MI->getOperand(4).getImm();
75 bool useSubstituteMnemonic = false;
76 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
77 O << "\tslwi "; useSubstituteMnemonic = true;
79 if (SH <= 31 && MB == (32-SH) && ME == 31) {
80 O << "\tsrwi "; useSubstituteMnemonic = true;
83 if (useSubstituteMnemonic) {
84 printOperand(MI, 0, O);
86 printOperand(MI, 1, O);
87 O << ", " << (unsigned int)SH;
89 printAnnotation(O, Annot);
94 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
95 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
97 printOperand(MI, 0, O);
99 printOperand(MI, 1, O);
100 printAnnotation(O, Annot);
104 if (MI->getOpcode() == PPC::RLDICR ||
105 MI->getOpcode() == PPC::RLDICR_32) {
106 unsigned char SH = MI->getOperand(2).getImm();
107 unsigned char ME = MI->getOperand(3).getImm();
108 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
111 printOperand(MI, 0, O);
113 printOperand(MI, 1, O);
114 O << ", " << (unsigned int)SH;
115 printAnnotation(O, Annot);
120 // dcbt[st] is printed manually here because:
121 // 1. The assembly syntax is different between embedded and server targets
122 // 2. We must print the short mnemonics for TH == 0 because the
123 // embedded/server syntax default will not be stable across assemblers
124 // The syntax for dcbt is:
125 // dcbt ra, rb, th [server]
126 // dcbt th, ra, rb [embedded]
127 // where th can be omitted when it is 0. dcbtst is the same.
128 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
129 unsigned char TH = MI->getOperand(0).getImm();
131 if (MI->getOpcode() == PPC::DCBTST)
137 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
138 if (IsBookE && TH != 0 && TH != 16)
139 O << (unsigned int) TH << ", ";
141 printOperand(MI, 1, O);
143 printOperand(MI, 2, O);
145 if (!IsBookE && TH != 0 && TH != 16)
146 O << ", " << (unsigned int) TH;
148 printAnnotation(O, Annot);
152 if (MI->getOpcode() == PPC::DCBF) {
153 unsigned char L = MI->getOperand(0).getImm();
154 if (!L || L == 1 || L == 3) {
156 if (L == 1 || L == 3)
162 printOperand(MI, 1, O);
164 printOperand(MI, 2, O);
166 printAnnotation(O, Annot);
171 if (!printAliasInstr(MI, O))
172 printInstruction(MI, O);
173 printAnnotation(O, Annot);
177 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
179 const char *Modifier) {
180 unsigned Code = MI->getOperand(OpNo).getImm();
182 if (StringRef(Modifier) == "cc") {
183 switch ((PPC::Predicate)Code) {
184 case PPC::PRED_LT_MINUS:
185 case PPC::PRED_LT_PLUS:
189 case PPC::PRED_LE_MINUS:
190 case PPC::PRED_LE_PLUS:
194 case PPC::PRED_EQ_MINUS:
195 case PPC::PRED_EQ_PLUS:
199 case PPC::PRED_GE_MINUS:
200 case PPC::PRED_GE_PLUS:
204 case PPC::PRED_GT_MINUS:
205 case PPC::PRED_GT_PLUS:
209 case PPC::PRED_NE_MINUS:
210 case PPC::PRED_NE_PLUS:
214 case PPC::PRED_UN_MINUS:
215 case PPC::PRED_UN_PLUS:
219 case PPC::PRED_NU_MINUS:
220 case PPC::PRED_NU_PLUS:
224 case PPC::PRED_BIT_SET:
225 case PPC::PRED_BIT_UNSET:
226 llvm_unreachable("Invalid use of bit predicate code");
228 llvm_unreachable("Invalid predicate code");
231 if (StringRef(Modifier) == "pm") {
232 switch ((PPC::Predicate)Code) {
242 case PPC::PRED_LT_MINUS:
243 case PPC::PRED_LE_MINUS:
244 case PPC::PRED_EQ_MINUS:
245 case PPC::PRED_GE_MINUS:
246 case PPC::PRED_GT_MINUS:
247 case PPC::PRED_NE_MINUS:
248 case PPC::PRED_UN_MINUS:
249 case PPC::PRED_NU_MINUS:
252 case PPC::PRED_LT_PLUS:
253 case PPC::PRED_LE_PLUS:
254 case PPC::PRED_EQ_PLUS:
255 case PPC::PRED_GE_PLUS:
256 case PPC::PRED_GT_PLUS:
257 case PPC::PRED_NE_PLUS:
258 case PPC::PRED_UN_PLUS:
259 case PPC::PRED_NU_PLUS:
262 case PPC::PRED_BIT_SET:
263 case PPC::PRED_BIT_UNSET:
264 llvm_unreachable("Invalid use of bit predicate code");
266 llvm_unreachable("Invalid predicate code");
269 assert(StringRef(Modifier) == "reg" &&
270 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
271 printOperand(MI, OpNo+1, O);
274 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
276 unsigned Code = MI->getOperand(OpNo).getImm();
283 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
285 unsigned int Value = MI->getOperand(OpNo).getImm();
286 assert(Value <= 1 && "Invalid u1imm argument!");
287 O << (unsigned int)Value;
290 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
292 unsigned int Value = MI->getOperand(OpNo).getImm();
293 assert(Value <= 3 && "Invalid u2imm argument!");
294 O << (unsigned int)Value;
297 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
299 unsigned int Value = MI->getOperand(OpNo).getImm();
300 assert(Value <= 8 && "Invalid u3imm argument!");
301 O << (unsigned int)Value;
304 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
306 unsigned int Value = MI->getOperand(OpNo).getImm();
307 assert(Value <= 15 && "Invalid u4imm argument!");
308 O << (unsigned int)Value;
311 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
313 int Value = MI->getOperand(OpNo).getImm();
314 Value = SignExtend32<5>(Value);
318 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
320 unsigned int Value = MI->getOperand(OpNo).getImm();
321 assert(Value <= 31 && "Invalid u5imm argument!");
322 O << (unsigned int)Value;
325 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
327 unsigned int Value = MI->getOperand(OpNo).getImm();
328 assert(Value <= 63 && "Invalid u6imm argument!");
329 O << (unsigned int)Value;
332 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
334 unsigned int Value = MI->getOperand(OpNo).getImm();
335 assert(Value <= 127 && "Invalid u7imm argument!");
336 O << (unsigned int)Value;
339 // Operands of BUILD_VECTOR are signed and we use this to print operands
340 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
341 // print as unsigned.
342 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
344 unsigned char Value = MI->getOperand(OpNo).getImm();
345 O << (unsigned int)Value;
348 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
350 unsigned short Value = MI->getOperand(OpNo).getImm();
351 assert(Value <= 1023 && "Invalid u10imm argument!");
352 O << (unsigned short)Value;
355 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
357 unsigned short Value = MI->getOperand(OpNo).getImm();
358 assert(Value <= 4095 && "Invalid u12imm argument!");
359 O << (unsigned short)Value;
362 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
364 if (MI->getOperand(OpNo).isImm())
365 O << (short)MI->getOperand(OpNo).getImm();
367 printOperand(MI, OpNo, O);
370 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
372 if (MI->getOperand(OpNo).isImm())
373 O << (unsigned short)MI->getOperand(OpNo).getImm();
375 printOperand(MI, OpNo, O);
378 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
380 if (!MI->getOperand(OpNo).isImm())
381 return printOperand(MI, OpNo, O);
383 // Branches can take an immediate operand. This is used by the branch
384 // selection pass to print .+8, an eight byte displacement from the PC.
386 printAbsBranchOperand(MI, OpNo, O);
389 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
391 if (!MI->getOperand(OpNo).isImm())
392 return printOperand(MI, OpNo, O);
394 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
398 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
400 unsigned CCReg = MI->getOperand(OpNo).getReg();
403 default: llvm_unreachable("Unknown CR register");
404 case PPC::CR0: RegNo = 0; break;
405 case PPC::CR1: RegNo = 1; break;
406 case PPC::CR2: RegNo = 2; break;
407 case PPC::CR3: RegNo = 3; break;
408 case PPC::CR4: RegNo = 4; break;
409 case PPC::CR5: RegNo = 5; break;
410 case PPC::CR6: RegNo = 6; break;
411 case PPC::CR7: RegNo = 7; break;
413 O << (0x80 >> RegNo);
416 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
418 printS16ImmOperand(MI, OpNo, O);
420 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
423 printOperand(MI, OpNo+1, O);
427 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
429 // When used as the base register, r0 reads constant zero rather than
430 // the value contained in the register. For this reason, the darwin
431 // assembler requires that we print r0 as 0 (no r) when used as the base.
432 if (MI->getOperand(OpNo).getReg() == PPC::R0)
435 printOperand(MI, OpNo, O);
437 printOperand(MI, OpNo+1, O);
440 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
442 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
443 // come at the _end_ of the expression.
444 const MCOperand &Op = MI->getOperand(OpNo);
445 const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
446 O << refExp.getSymbol().getName();
448 printOperand(MI, OpNo+1, O);
450 if (refExp.getKind() != MCSymbolRefExpr::VK_None)
451 O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
454 /// showRegistersWithPercentPrefix - Check if this register name should be
455 /// printed with a percentage symbol as prefix.
456 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
457 if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
460 switch (RegName[0]) {
472 /// getVerboseConditionalRegName - This method expands the condition register
473 /// when requested explicitly or targetting Darwin.
474 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
475 unsigned RegEncoding)
477 if (!TT.isOSDarwin() && !FullRegNames)
479 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
481 const char *CRBits[] = {
482 "lt", "gt", "eq", "un",
483 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
484 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
485 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
486 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
487 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
488 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
489 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
491 return CRBits[RegEncoding];
494 // showRegistersWithPrefix - This method determines whether registers
495 // should be number-only or include the prefix.
496 bool PPCInstPrinter::showRegistersWithPrefix() const {
497 if (TT.getOS() == Triple::AIX)
499 return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
502 /// stripRegisterPrefix - This method strips the character prefix from a
503 /// register name so that only the number is left.
504 static const char *stripRegisterPrefix(const char *RegName) {
505 switch (RegName[0]) {
510 if (RegName[1] == 's')
513 case 'c': if (RegName[1] == 'r') return RegName + 2;
519 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
521 const MCOperand &Op = MI->getOperand(OpNo);
523 unsigned Reg = Op.getReg();
525 // There are VSX instructions that use VSX register numbering (vs0 - vs63)
526 // as well as those that use VMX register numbering (v0 - v31 which
527 // correspond to vs32 - vs63). If we have an instruction that uses VSX
528 // numbering, we need to convert the VMX registers to VSX registers.
529 // Namely, we print 32-63 when the instruction operates on one of the
531 // (Please synchronize with PPCAsmPrinter::printOperand)
532 if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg) &&
534 if (PPCInstrInfo::isVRRegister(Reg))
535 Reg = PPC::VSX32 + (Reg - PPC::V0);
536 else if (PPCInstrInfo::isVFRegister(Reg))
537 Reg = PPC::VSX32 + (Reg - PPC::VF0);
541 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
542 if (RegName == nullptr)
543 RegName = getRegisterName(Reg);
544 if (showRegistersWithPercentPrefix(RegName))
546 if (!showRegistersWithPrefix())
547 RegName = stripRegisterPrefix(RegName);
558 assert(Op.isExpr() && "unknown operand kind in printOperand");
559 Op.getExpr()->print(O, &MAI);