1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/EndianStream.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetOpcodes.h"
32 #define DEBUG_TYPE "mccodeemitter"
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
37 class PPCMCCodeEmitter : public MCCodeEmitter {
38 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete;
39 void operator=(const PPCMCCodeEmitter &) = delete;
41 const MCInstrInfo &MCII;
46 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
47 : MCII(mcii), CTX(ctx),
48 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
50 ~PPCMCCodeEmitter() override {}
52 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
53 SmallVectorImpl<MCFixup> &Fixups,
54 const MCSubtargetInfo &STI) const;
55 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const;
58 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
59 SmallVectorImpl<MCFixup> &Fixups,
60 const MCSubtargetInfo &STI) const;
61 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
62 SmallVectorImpl<MCFixup> &Fixups,
63 const MCSubtargetInfo &STI) const;
64 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
65 SmallVectorImpl<MCFixup> &Fixups,
66 const MCSubtargetInfo &STI) const;
67 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
68 SmallVectorImpl<MCFixup> &Fixups,
69 const MCSubtargetInfo &STI) const;
70 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
71 SmallVectorImpl<MCFixup> &Fixups,
72 const MCSubtargetInfo &STI) const;
73 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
74 SmallVectorImpl<MCFixup> &Fixups,
75 const MCSubtargetInfo &STI) const;
76 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
77 SmallVectorImpl<MCFixup> &Fixups,
78 const MCSubtargetInfo &STI) const;
79 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
82 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
83 SmallVectorImpl<MCFixup> &Fixups,
84 const MCSubtargetInfo &STI) const;
85 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
86 SmallVectorImpl<MCFixup> &Fixups,
87 const MCSubtargetInfo &STI) const;
88 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
89 SmallVectorImpl<MCFixup> &Fixups,
90 const MCSubtargetInfo &STI) const;
91 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
92 SmallVectorImpl<MCFixup> &Fixups,
93 const MCSubtargetInfo &STI) const;
95 /// getMachineOpValue - Return binary encoding of operand. If the machine
96 /// operand requires relocation, record the relocation and return zero.
97 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
98 SmallVectorImpl<MCFixup> &Fixups,
99 const MCSubtargetInfo &STI) const;
101 // getBinaryCodeForInstr - TableGen'erated function for getting the
102 // binary encoding for an instruction.
103 uint64_t getBinaryCodeForInstr(const MCInst &MI,
104 SmallVectorImpl<MCFixup> &Fixups,
105 const MCSubtargetInfo &STI) const;
106 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
107 SmallVectorImpl<MCFixup> &Fixups,
108 const MCSubtargetInfo &STI) const override {
109 verifyInstructionPredicates(MI,
110 computeAvailableFeatures(STI.getFeatureBits()));
112 unsigned Opcode = MI.getOpcode();
113 const MCInstrDesc &Desc = MCII.get(Opcode);
115 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
117 // Output the constant in big/little endian byte order.
118 unsigned Size = Desc.getSize();
123 if (IsLittleEndian) {
124 support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
126 support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
130 // If we emit a pair of instructions, the first one is
131 // always in the top 32 bits, even on little-endian.
132 if (IsLittleEndian) {
133 uint64_t Swapped = (Bits << 32) | (Bits >> 32);
134 support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped);
136 support::endian::Writer<support::big>(OS).write<uint64_t>(Bits);
140 llvm_unreachable ("Invalid instruction size");
143 ++MCNumEmitted; // Keep track of the # of mi's emitted.
147 uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
148 void verifyInstructionPredicates(const MCInst &MI,
149 uint64_t AvailableFeatures) const;
152 } // end anonymous namespace
154 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
155 const MCRegisterInfo &MRI,
157 return new PPCMCCodeEmitter(MCII, Ctx);
160 unsigned PPCMCCodeEmitter::
161 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI) const {
164 const MCOperand &MO = MI.getOperand(OpNo);
165 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
167 // Add a fixup for the branch target.
168 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
169 (MCFixupKind)PPC::fixup_ppc_br24));
173 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
174 SmallVectorImpl<MCFixup> &Fixups,
175 const MCSubtargetInfo &STI) const {
176 const MCOperand &MO = MI.getOperand(OpNo);
177 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
179 // Add a fixup for the branch target.
180 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
181 (MCFixupKind)PPC::fixup_ppc_brcond14));
185 unsigned PPCMCCodeEmitter::
186 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
187 SmallVectorImpl<MCFixup> &Fixups,
188 const MCSubtargetInfo &STI) const {
189 const MCOperand &MO = MI.getOperand(OpNo);
190 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
192 // Add a fixup for the branch target.
193 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
194 (MCFixupKind)PPC::fixup_ppc_br24abs));
198 unsigned PPCMCCodeEmitter::
199 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
200 SmallVectorImpl<MCFixup> &Fixups,
201 const MCSubtargetInfo &STI) const {
202 const MCOperand &MO = MI.getOperand(OpNo);
203 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
205 // Add a fixup for the branch target.
206 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
207 (MCFixupKind)PPC::fixup_ppc_brcond14abs));
211 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
212 SmallVectorImpl<MCFixup> &Fixups,
213 const MCSubtargetInfo &STI) const {
214 const MCOperand &MO = MI.getOperand(OpNo);
215 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
217 // Add a fixup for the immediate field.
218 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
219 (MCFixupKind)PPC::fixup_ppc_half16));
223 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
224 SmallVectorImpl<MCFixup> &Fixups,
225 const MCSubtargetInfo &STI) const {
226 // Encode (imm, reg) as a memri, which has the low 16-bits as the
227 // displacement and the next 5 bits as the register #.
228 assert(MI.getOperand(OpNo+1).isReg());
229 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
231 const MCOperand &MO = MI.getOperand(OpNo);
233 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
235 // Add a fixup for the displacement field.
236 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
237 (MCFixupKind)PPC::fixup_ppc_half16));
242 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
243 SmallVectorImpl<MCFixup> &Fixups,
244 const MCSubtargetInfo &STI) const {
245 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
246 // displacement and the next 5 bits as the register #.
247 assert(MI.getOperand(OpNo+1).isReg());
248 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
250 const MCOperand &MO = MI.getOperand(OpNo);
252 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
254 // Add a fixup for the displacement field.
255 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
256 (MCFixupKind)PPC::fixup_ppc_half16ds));
260 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
261 SmallVectorImpl<MCFixup> &Fixups,
262 const MCSubtargetInfo &STI) const {
263 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
264 // displacement and the next 5 bits as the register #.
265 assert(MI.getOperand(OpNo+1).isReg());
266 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
268 const MCOperand &MO = MI.getOperand(OpNo);
271 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
274 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
275 SmallVectorImpl<MCFixup> &Fixups,
276 const MCSubtargetInfo &STI)
278 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
279 // as the displacement and the next 5 bits as the register #.
280 assert(MI.getOperand(OpNo+1).isReg());
281 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
283 const MCOperand &MO = MI.getOperand(OpNo);
285 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
286 return reverseBits(Imm | RegBits) >> 22;
290 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
291 SmallVectorImpl<MCFixup> &Fixups,
292 const MCSubtargetInfo &STI)
294 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
295 // as the displacement and the next 5 bits as the register #.
296 assert(MI.getOperand(OpNo+1).isReg());
297 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
299 const MCOperand &MO = MI.getOperand(OpNo);
301 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
302 return reverseBits(Imm | RegBits) >> 22;
306 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
307 SmallVectorImpl<MCFixup> &Fixups,
308 const MCSubtargetInfo &STI)
310 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
311 // as the displacement and the next 5 bits as the register #.
312 assert(MI.getOperand(OpNo+1).isReg());
313 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
315 const MCOperand &MO = MI.getOperand(OpNo);
317 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
318 return reverseBits(Imm | RegBits) >> 22;
322 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
323 SmallVectorImpl<MCFixup> &Fixups,
324 const MCSubtargetInfo &STI) const {
325 const MCOperand &MO = MI.getOperand(OpNo);
326 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
328 // Add a fixup for the TLS register, which simply provides a relocation
329 // hint to the linker that this statement is part of a relocation sequence.
330 // Return the thread-pointer register's encoding.
331 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
332 (MCFixupKind)PPC::fixup_ppc_nofixup));
333 const Triple &TT = STI.getTargetTriple();
334 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
335 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
338 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
339 SmallVectorImpl<MCFixup> &Fixups,
340 const MCSubtargetInfo &STI) const {
341 // For special TLS calls, we need two fixups; one for the branch target
342 // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
343 // and one for the TLSGD or TLSLD symbol, which is emitted here.
344 const MCOperand &MO = MI.getOperand(OpNo+1);
345 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
346 (MCFixupKind)PPC::fixup_ppc_nofixup));
347 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
350 unsigned PPCMCCodeEmitter::
351 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
352 SmallVectorImpl<MCFixup> &Fixups,
353 const MCSubtargetInfo &STI) const {
354 const MCOperand &MO = MI.getOperand(OpNo);
355 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
356 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
357 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
358 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
361 unsigned PPCMCCodeEmitter::
362 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
363 SmallVectorImpl<MCFixup> &Fixups,
364 const MCSubtargetInfo &STI) const {
366 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
367 // The GPR operand should come through here though.
368 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
369 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
370 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
371 unsigned Reg = MO.getReg();
372 unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg);
374 if ((MCII.get(MI.getOpcode()).TSFlags & PPCII::UseVSXReg))
375 if (PPCInstrInfo::isVRRegister(Reg))
382 "Relocation required in an instruction that we cannot encode!");
388 #define ENABLE_INSTR_PREDICATE_VERIFIER
389 #include "PPCGenMCCodeEmitter.inc"