1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/PPCFixupKinds.h"
15 #include "PPCInstrInfo.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/Endian.h"
29 #include "llvm/Support/EndianStream.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
38 #define DEBUG_TYPE "mccodeemitter"
40 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
44 class PPCMCCodeEmitter : public MCCodeEmitter {
45 const MCInstrInfo &MCII;
50 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
51 : MCII(mcii), CTX(ctx),
52 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {}
53 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete;
54 void operator=(const PPCMCCodeEmitter &) = delete;
55 ~PPCMCCodeEmitter() override = default;
57 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
58 SmallVectorImpl<MCFixup> &Fixups,
59 const MCSubtargetInfo &STI) const;
60 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
61 SmallVectorImpl<MCFixup> &Fixups,
62 const MCSubtargetInfo &STI) const;
63 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const;
66 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
69 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
70 SmallVectorImpl<MCFixup> &Fixups,
71 const MCSubtargetInfo &STI) const;
72 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
73 SmallVectorImpl<MCFixup> &Fixups,
74 const MCSubtargetInfo &STI) const;
75 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
76 SmallVectorImpl<MCFixup> &Fixups,
77 const MCSubtargetInfo &STI) const;
78 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
79 SmallVectorImpl<MCFixup> &Fixups,
80 const MCSubtargetInfo &STI) const;
81 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const;
84 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
85 SmallVectorImpl<MCFixup> &Fixups,
86 const MCSubtargetInfo &STI) const;
87 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups,
89 const MCSubtargetInfo &STI) const;
90 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
91 SmallVectorImpl<MCFixup> &Fixups,
92 const MCSubtargetInfo &STI) const;
93 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI) const;
96 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
97 SmallVectorImpl<MCFixup> &Fixups,
98 const MCSubtargetInfo &STI) const;
100 /// getMachineOpValue - Return binary encoding of operand. If the machine
101 /// operand requires relocation, record the relocation and return zero.
102 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
103 SmallVectorImpl<MCFixup> &Fixups,
104 const MCSubtargetInfo &STI) const;
106 // getBinaryCodeForInstr - TableGen'erated function for getting the
107 // binary encoding for an instruction.
108 uint64_t getBinaryCodeForInstr(const MCInst &MI,
109 SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &STI) const;
112 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
113 SmallVectorImpl<MCFixup> &Fixups,
114 const MCSubtargetInfo &STI) const override {
115 verifyInstructionPredicates(MI,
116 computeAvailableFeatures(STI.getFeatureBits()));
118 unsigned Opcode = MI.getOpcode();
119 const MCInstrDesc &Desc = MCII.get(Opcode);
121 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
123 // Output the constant in big/little endian byte order.
124 unsigned Size = Desc.getSize();
129 if (IsLittleEndian) {
130 support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
132 support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
136 // If we emit a pair of instructions, the first one is
137 // always in the top 32 bits, even on little-endian.
138 if (IsLittleEndian) {
139 uint64_t Swapped = (Bits << 32) | (Bits >> 32);
140 support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped);
142 support::endian::Writer<support::big>(OS).write<uint64_t>(Bits);
146 llvm_unreachable("Invalid instruction size");
149 ++MCNumEmitted; // Keep track of the # of mi's emitted.
153 uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
154 void verifyInstructionPredicates(const MCInst &MI,
155 uint64_t AvailableFeatures) const;
158 } // end anonymous namespace
160 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
161 const MCRegisterInfo &MRI,
163 return new PPCMCCodeEmitter(MCII, Ctx);
166 unsigned PPCMCCodeEmitter::
167 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
168 SmallVectorImpl<MCFixup> &Fixups,
169 const MCSubtargetInfo &STI) const {
170 const MCOperand &MO = MI.getOperand(OpNo);
171 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
173 // Add a fixup for the branch target.
174 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
175 (MCFixupKind)PPC::fixup_ppc_br24));
179 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
180 SmallVectorImpl<MCFixup> &Fixups,
181 const MCSubtargetInfo &STI) const {
182 const MCOperand &MO = MI.getOperand(OpNo);
183 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
185 // Add a fixup for the branch target.
186 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
187 (MCFixupKind)PPC::fixup_ppc_brcond14));
191 unsigned PPCMCCodeEmitter::
192 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
193 SmallVectorImpl<MCFixup> &Fixups,
194 const MCSubtargetInfo &STI) const {
195 const MCOperand &MO = MI.getOperand(OpNo);
196 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
198 // Add a fixup for the branch target.
199 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
200 (MCFixupKind)PPC::fixup_ppc_br24abs));
204 unsigned PPCMCCodeEmitter::
205 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
206 SmallVectorImpl<MCFixup> &Fixups,
207 const MCSubtargetInfo &STI) const {
208 const MCOperand &MO = MI.getOperand(OpNo);
209 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
211 // Add a fixup for the branch target.
212 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
213 (MCFixupKind)PPC::fixup_ppc_brcond14abs));
217 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
218 SmallVectorImpl<MCFixup> &Fixups,
219 const MCSubtargetInfo &STI) const {
220 const MCOperand &MO = MI.getOperand(OpNo);
221 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
223 // Add a fixup for the immediate field.
224 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
225 (MCFixupKind)PPC::fixup_ppc_half16));
229 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
230 SmallVectorImpl<MCFixup> &Fixups,
231 const MCSubtargetInfo &STI) const {
232 // Encode (imm, reg) as a memri, which has the low 16-bits as the
233 // displacement and the next 5 bits as the register #.
234 assert(MI.getOperand(OpNo+1).isReg());
235 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
237 const MCOperand &MO = MI.getOperand(OpNo);
239 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
241 // Add a fixup for the displacement field.
242 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
243 (MCFixupKind)PPC::fixup_ppc_half16));
247 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
248 SmallVectorImpl<MCFixup> &Fixups,
249 const MCSubtargetInfo &STI) const {
250 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
251 // displacement and the next 5 bits as the register #.
252 assert(MI.getOperand(OpNo+1).isReg());
253 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
255 const MCOperand &MO = MI.getOperand(OpNo);
257 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
259 // Add a fixup for the displacement field.
260 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
261 (MCFixupKind)PPC::fixup_ppc_half16ds));
265 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
266 SmallVectorImpl<MCFixup> &Fixups,
267 const MCSubtargetInfo &STI) const {
268 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
269 // displacement and the next 5 bits as the register #.
270 assert(MI.getOperand(OpNo+1).isReg());
271 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
273 const MCOperand &MO = MI.getOperand(OpNo);
276 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
279 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
280 SmallVectorImpl<MCFixup> &Fixups,
281 const MCSubtargetInfo &STI)
283 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
284 // as the displacement and the next 5 bits as the register #.
285 assert(MI.getOperand(OpNo+1).isReg());
286 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
288 const MCOperand &MO = MI.getOperand(OpNo);
290 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
291 return reverseBits(Imm | RegBits) >> 22;
294 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
295 SmallVectorImpl<MCFixup> &Fixups,
296 const MCSubtargetInfo &STI)
298 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
299 // as the displacement and the next 5 bits as the register #.
300 assert(MI.getOperand(OpNo+1).isReg());
301 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
303 const MCOperand &MO = MI.getOperand(OpNo);
305 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
306 return reverseBits(Imm | RegBits) >> 22;
309 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
310 SmallVectorImpl<MCFixup> &Fixups,
311 const MCSubtargetInfo &STI)
313 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
314 // as the displacement and the next 5 bits as the register #.
315 assert(MI.getOperand(OpNo+1).isReg());
316 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
318 const MCOperand &MO = MI.getOperand(OpNo);
320 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
321 return reverseBits(Imm | RegBits) >> 22;
324 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
325 SmallVectorImpl<MCFixup> &Fixups,
326 const MCSubtargetInfo &STI) const {
327 const MCOperand &MO = MI.getOperand(OpNo);
328 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
330 // Add a fixup for the TLS register, which simply provides a relocation
331 // hint to the linker that this statement is part of a relocation sequence.
332 // Return the thread-pointer register's encoding.
333 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
334 (MCFixupKind)PPC::fixup_ppc_nofixup));
335 const Triple &TT = STI.getTargetTriple();
336 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
337 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
340 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
341 SmallVectorImpl<MCFixup> &Fixups,
342 const MCSubtargetInfo &STI) const {
343 // For special TLS calls, we need two fixups; one for the branch target
344 // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
345 // and one for the TLSGD or TLSLD symbol, which is emitted here.
346 const MCOperand &MO = MI.getOperand(OpNo+1);
347 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
348 (MCFixupKind)PPC::fixup_ppc_nofixup));
349 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
352 unsigned PPCMCCodeEmitter::
353 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
354 SmallVectorImpl<MCFixup> &Fixups,
355 const MCSubtargetInfo &STI) const {
356 const MCOperand &MO = MI.getOperand(OpNo);
357 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
358 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
359 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
360 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
363 unsigned PPCMCCodeEmitter::
364 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
365 SmallVectorImpl<MCFixup> &Fixups,
366 const MCSubtargetInfo &STI) const {
368 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
369 // The GPR operand should come through here though.
370 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
371 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
372 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
373 unsigned Reg = MO.getReg();
374 unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg);
376 if ((MCII.get(MI.getOpcode()).TSFlags & PPCII::UseVSXReg))
377 if (PPCInstrInfo::isVRRegister(Reg))
384 "Relocation required in an instruction that we cannot encode!");
388 #define ENABLE_INSTR_PREDICATE_VERIFIER
389 #include "PPCGenMCCodeEmitter.inc"