1 //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides PowerPC specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
17 // GCC #defines PPC on Linux but we use it as our namespace name
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/Support/MathExtras.h"
31 class MCObjectTargetWriter;
33 class MCSubtargetInfo;
34 class MCTargetOptions;
38 class raw_pwrite_stream;
40 Target &getThePPC32Target();
41 Target &getThePPC64Target();
42 Target &getThePPC64LETarget();
44 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
45 const MCRegisterInfo &MRI,
48 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
49 const MCRegisterInfo &MRI,
50 const MCTargetOptions &Options);
52 /// Construct an PPC ELF object writer.
53 std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
55 /// Construct a PPC Mach-O object writer.
56 std::unique_ptr<MCObjectTargetWriter>
57 createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
59 /// Returns true iff Val consists of one contiguous run of 1s with any number of
60 /// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
61 /// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
62 /// since all 1s are not contiguous.
63 static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
67 if (isShiftedMask_32(Val)) {
68 // look for the first non-zero bit
69 MB = countLeadingZeros(Val);
70 // look for the first zero bit after the run of ones
71 ME = countLeadingZeros((Val - 1) ^ Val);
74 Val = ~Val; // invert mask
75 if (isShiftedMask_32(Val)) {
76 // effectively look for the first zero bit
77 ME = countLeadingZeros(Val) - 1;
78 // effectively look for the first one bit after the run of zeros
79 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
87 } // end namespace llvm
89 // Generated files will use "namespace PPC". To avoid symbol clash,
90 // undefine PPC here. PPC may be predefined on some hosts.
93 // Defines symbolic names for PowerPC registers. This defines a mapping from
94 // register name to register number.
96 #define GET_REGINFO_ENUM
97 #include "PPCGenRegisterInfo.inc"
99 // Defines symbolic names for the PowerPC instructions.
101 #define GET_INSTRINFO_ENUM
102 #define GET_INSTRINFO_SCHED_ENUM
103 #include "PPCGenInstrInfo.inc"
105 #define GET_SUBTARGETINFO_ENUM
106 #include "PPCGenSubtargetInfo.inc"
108 #define PPC_REGS0_31(X) \
110 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
111 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
112 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
115 #define PPC_REGS_NO0_31(Z, X) \
117 Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
118 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
119 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
122 #define PPC_REGS_LO_HI(LO, HI) \
124 LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
125 LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
126 LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
127 LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
128 HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
129 HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
130 HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
131 HI##28, HI##29, HI##30, HI##31 \
134 using llvm::MCPhysReg;
136 #define DEFINE_PPC_REGCLASSES \
137 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
138 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
139 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
140 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
141 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
142 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
143 static const MCPhysReg QFRegs[32] = PPC_REGS0_31(PPC::QF); \
144 static const MCPhysReg RRegsNoR0[32] = \
145 PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
146 static const MCPhysReg XRegsNoX0[32] = \
147 PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
148 static const MCPhysReg VSRegs[64] = \
149 PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
150 static const MCPhysReg VSFRegs[64] = \
151 PPC_REGS_LO_HI(PPC::F, PPC::VF); \
152 static const MCPhysReg VSSRegs[64] = \
153 PPC_REGS_LO_HI(PPC::F, PPC::VF); \
154 static const MCPhysReg CRBITRegs[32] = { \
155 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, \
156 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
157 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
158 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
159 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
160 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
161 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
162 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
163 static const MCPhysReg CRRegs[8] = { \
164 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, \
165 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7}
167 #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H