contrib/llvm/lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x
  46     : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  47 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  48 def DirectivePwr6x
  49     : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  50 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  51 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  52 def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">;
  53
  54 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  55                                         "Enable 64-bit instructions">;
  56 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
  57                               "Use software emulation for floating point">;
  58 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  59                               "Enable 64-bit registers usage for ppc32 [beta]">;
  60 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  61                               "Use condition-register bits individually">;
  62 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  63                                         "Enable Altivec instructions">;
  64 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  65                                         "Enable SPE instructions">;
  66 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  67                                         "Enable the MFOCRF instruction">;
  68 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  69                                         "Enable the fsqrt instruction">;
  70 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  71                                         "Enable the fcpsgn instruction">;
  72 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  73                                         "Enable the fre instruction">;
  74 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  75                                         "Enable the fres instruction">;
  76 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  77                                         "Enable the frsqrte instruction">;
  78 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  79                                         "Enable the frsqrtes instruction">;
  80 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  81                               "Assume higher precision reciprocal estimates">;
  82 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  83                                         "Enable the stfiwx instruction">;
  84 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  85                                         "Enable the lfiwax instruction">;
  86 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  87                                         "Enable the fri[mnpz] instructions">;
  88 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  89   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  90 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  91                                         "Enable the isel instruction">;
  92 def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
  93                                         "Enable the bpermd instruction">;
  94 def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
  95                                         "Enable extended divide instructions">;
  96 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  97                                         "Enable the ldbrx instruction">;
  98 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
  99                                         "Enable the cmpb instruction">;
 100 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
 101                                         "Enable icbt instruction">;
 102 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
 103                                         "Enable Book E instructions",
 104                                         [FeatureICBT]>;
 105 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
 106                               "Has only the msync instruction instead of sync",
 107                               [FeatureBookE]>;
 108 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 109                                         "Enable E500/E500mc instructions">;
 110 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 111                                         "Enable PPC 4xx instructions">;
 112 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 113                                         "Enable PPC 6xx instructions">;
 114 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 115                                         "Enable QPX instructions">;
 116 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 117                                         "Enable VSX instructions",
 118                                         [FeatureAltivec]>;
 119 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 120                                         "Enable POWER8 Altivec instructions",
 121                                         [FeatureAltivec]>;
 122 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 123                                        "Enable POWER8 Crypto instructions",
 124                                        [FeatureP8Altivec]>;
 125 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 126                                         "Enable POWER8 vector instructions",
 127                                         [FeatureVSX, FeatureP8Altivec]>;
 128 def FeatureDirectMove :
 129   SubtargetFeature<"direct-move", "HasDirectMove", "true",
 130                    "Enable Power8 direct move instructions",
 131                    [FeatureVSX]>;
 132 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
 133                                              "HasPartwordAtomics", "true",
 134                                              "Enable l[bh]arx and st[bh]cx.">;
 135 def FeatureInvariantFunctionDescriptors :
 136   SubtargetFeature<"invariant-function-descriptors",
 137                    "HasInvariantFunctionDescriptors", "true",
 138                    "Assume function descriptors are invariant">;
 139 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
 140                                        "Always use indirect calls">;
 141 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
 142                                   "Enable Hardware Transactional Memory instructions">;
 143 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
 144                                         "Implement mftb using the mfspr instruction">;
 145 def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
 146                                      "Target supports add/load integer fusion.">;
 147 def FeatureFloat128 :
 148   SubtargetFeature<"float128", "HasFloat128", "true",
 149                    "Enable the __float128 data type for IEEE-754R Binary128.",
 150                    [FeatureVSX]>;
 151 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
 152                                         "POPCNTD_Fast",
 153                                         "Enable the popcnt[dw] instructions">;
 154 // Note that for the a2/a2q processor models we should not use popcnt[dw] by
 155 // default. These processors do support the instructions, but they're
 156 // microcoded, and the software emulation is about twice as fast.
 157 def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
 158                                           "POPCNTD_Slow",
 159                                           "Has slow popcnt[dw] instructions">;
 160
 161 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 162   "Treat vector data stream cache control instructions as deprecated">;
 163
 164 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
 165                                      "true",
 166                                      "Enable instructions added in ISA 3.0.">;
 167 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
 168                                         "Enable POWER9 Altivec instructions",
 169                                         [FeatureISA3_0, FeatureP8Altivec]>;
 170 def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
 171                                         "Enable POWER9 vector instructions",
 172                                         [FeatureISA3_0, FeatureP8Vector,
 173                                          FeatureP9Altivec]>;
 174
 175 // Since new processors generally contain a superset of features of those that
 176 // came before them, the idea is to make implementations of new processors
 177 // less error prone and easier to read.
 178 // Namely:
 179 //     list<SubtargetFeature> Power8FeatureList = ...
 180 //     list<SubtargetFeature> FutureProcessorSpecificFeatureList =
 181 //         [ features that Power8 does not support ]
 182 //     list<SubtargetFeature> FutureProcessorFeatureList =
 183 //         !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
 184
 185 // Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
 186 // well as providing a single point of definition if the feature set will be
 187 // used elsewhere.
 188 def ProcessorFeatures {
 189   list<SubtargetFeature> Power7FeatureList =
 190       [DirectivePwr7, FeatureAltivec, FeatureVSX,
 191        FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 192        FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 193        FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 194        FeatureFPRND, FeatureFPCVT, FeatureISEL,
 195        FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
 196        Feature64Bit /*, Feature64BitRegs */,
 197        FeatureBPERMD, FeatureExtDiv,
 198        FeatureMFTB, DeprecatedDST];
 199   list<SubtargetFeature> Power8SpecificFeatures =
 200       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
 201        FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,
 202        FeatureFusion];
 203   list<SubtargetFeature> Power8FeatureList =
 204       !listconcat(Power7FeatureList, Power8SpecificFeatures);
 205   list<SubtargetFeature> Power9SpecificFeatures =
 206       [FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
 207   list<SubtargetFeature> Power9FeatureList =
 208       !listconcat(Power8FeatureList, Power9SpecificFeatures);
 209 }
 210
 211 // Note: Future features to add when support is extended to more
 212 // recent ISA levels:
 213 //
 214 // DFP          p6, p6x, p7        decimal floating-point instructions
 215 // POPCNTB      p5 through p7      popcntb and related instructions
 216
 217 //===----------------------------------------------------------------------===//
 218 // Classes used for relation maps.
 219 //===----------------------------------------------------------------------===//
 220 // RecFormRel - Filter class used to relate non-record-form instructions with
 221 // their record-form variants.
 222 class RecFormRel;
 223
 224 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 225 // FMA instruction forms with their corresponding factor-killing forms.
 226 class AltVSXFMARel {
 227   bit IsVSXFMAAlt = 0;
 228 }
 229
 230 //===----------------------------------------------------------------------===//
 231 // Relation Map Definitions.
 232 //===----------------------------------------------------------------------===//
 233
 234 def getRecordFormOpcode : InstrMapping {
 235   let FilterClass = "RecFormRel";
 236   // Instructions with the same BaseName and Interpretation64Bit values
 237   // form a row.
 238   let RowFields = ["BaseName", "Interpretation64Bit"];
 239   // Instructions with the same RC value form a column.
 240   let ColFields = ["RC"];
 241   // The key column are the non-record-form instructions.
 242   let KeyCol = ["0"];
 243   // Value columns RC=1
 244   let ValueCols = [["1"]];
 245 }
 246
 247 def getNonRecordFormOpcode : InstrMapping {
 248   let FilterClass = "RecFormRel";
 249   // Instructions with the same BaseName and Interpretation64Bit values
 250   // form a row.
 251   let RowFields = ["BaseName", "Interpretation64Bit"];
 252   // Instructions with the same RC value form a column.
 253   let ColFields = ["RC"];
 254   // The key column are the record-form instructions.
 255   let KeyCol = ["1"];
 256   // Value columns are RC=0
 257   let ValueCols = [["0"]];
 258 }
 259
 260 def getAltVSXFMAOpcode : InstrMapping {
 261   let FilterClass = "AltVSXFMARel";
 262   // Instructions with the same BaseName and Interpretation64Bit values
 263   // form a row.
 264   let RowFields = ["BaseName"];
 265   // Instructions with the same RC value form a column.
 266   let ColFields = ["IsVSXFMAAlt"];
 267   // The key column are the (default) addend-killing instructions.
 268   let KeyCol = ["0"];
 269   // Value columns IsVSXFMAAlt=1
 270   let ValueCols = [["1"]];
 271 }
 272
 273 //===----------------------------------------------------------------------===//
 274 // Register File Description
 275 //===----------------------------------------------------------------------===//
 276
 277 include "PPCRegisterInfo.td"
 278 include "PPCSchedule.td"
 279 include "PPCInstrInfo.td"
 280
 281 //===----------------------------------------------------------------------===//
 282 // PowerPC processors supported.
 283 //
 284
 285 def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>;
 286 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 287                                           FeatureFRES, FeatureFRSQRTE,
 288                                           FeatureICBT, FeatureBookE,
 289                                           FeatureMSYNC, FeatureMFTB]>;
 290 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 291                                           FeatureFRES, FeatureFRSQRTE,
 292                                           FeatureICBT, FeatureBookE,
 293                                           FeatureMSYNC, FeatureMFTB]>;
 294 def : Processor<"601", G3Itineraries, [Directive601]>;
 295 def : Processor<"602", G3Itineraries, [Directive602,
 296                                        FeatureMFTB]>;
 297 def : Processor<"603", G3Itineraries, [Directive603,
 298                                        FeatureFRES, FeatureFRSQRTE,
 299                                        FeatureMFTB]>;
 300 def : Processor<"603e", G3Itineraries, [Directive603,
 301                                         FeatureFRES, FeatureFRSQRTE,
 302                                         FeatureMFTB]>;
 303 def : Processor<"603ev", G3Itineraries, [Directive603,
 304                                          FeatureFRES, FeatureFRSQRTE,
 305                                          FeatureMFTB]>;
 306 def : Processor<"604", G3Itineraries, [Directive604,
 307                                        FeatureFRES, FeatureFRSQRTE,
 308                                        FeatureMFTB]>;
 309 def : Processor<"604e", G3Itineraries, [Directive604,
 310                                         FeatureFRES, FeatureFRSQRTE,
 311                                         FeatureMFTB]>;
 312 def : Processor<"620", G3Itineraries, [Directive620,
 313                                        FeatureFRES, FeatureFRSQRTE,
 314                                        FeatureMFTB]>;
 315 def : Processor<"750", G4Itineraries, [Directive750,
 316                                        FeatureFRES, FeatureFRSQRTE,
 317                                        FeatureMFTB]>;
 318 def : Processor<"g3", G3Itineraries, [Directive750,
 319                                       FeatureFRES, FeatureFRSQRTE,
 320                                       FeatureMFTB]>;
 321 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 322                                         FeatureFRES, FeatureFRSQRTE,
 323                                         FeatureMFTB]>;
 324 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 325                                       FeatureFRES, FeatureFRSQRTE,
 326                                       FeatureMFTB]>;
 327 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 328                                             FeatureFRES, FeatureFRSQRTE,
 329                                             FeatureMFTB]>;
 330 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 331                                            FeatureFRES, FeatureFRSQRTE,
 332                                            FeatureMFTB]>;
 333
 334 def : ProcessorModel<"970", G5Model,
 335                   [Directive970, FeatureAltivec,
 336                    FeatureMFOCRF, FeatureFSqrt,
 337                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 338                    Feature64Bit /*, Feature64BitRegs */,
 339                    FeatureMFTB]>;
 340 def : ProcessorModel<"g5", G5Model,
 341                   [Directive970, FeatureAltivec,
 342                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 343                    FeatureFRES, FeatureFRSQRTE,
 344                    Feature64Bit /*, Feature64BitRegs */,
 345                    FeatureMFTB, DeprecatedDST]>;
 346 def : ProcessorModel<"e500mc", PPCE500mcModel,
 347                   [DirectiveE500mc,
 348                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 349                    FeatureISEL, FeatureMFTB]>;
 350 def : ProcessorModel<"e5500", PPCE5500Model,
 351                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 352                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 353                    FeatureISEL, FeatureMFTB]>;
 354 def : ProcessorModel<"a2", PPCA2Model,
 355                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 356                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 357                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 358                    FeatureSTFIWX, FeatureLFIWAX,
 359                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 360                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 361                    Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
 362 def : ProcessorModel<"a2q", PPCA2Model,
 363                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 364                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 365                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 366                    FeatureSTFIWX, FeatureLFIWAX,
 367                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 368                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 369                    Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
 370                    FeatureMFTB]>;
 371 def : ProcessorModel<"pwr3", G5Model,
 372                   [DirectivePwr3, FeatureAltivec,
 373                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 374                    FeatureSTFIWX, Feature64Bit]>;
 375 def : ProcessorModel<"pwr4", G5Model,
 376                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 377                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 378                    FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 379 def : ProcessorModel<"pwr5", G5Model,
 380                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 381                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 382                    FeatureFRSQRTE, FeatureFRSQRTES,
 383                    FeatureSTFIWX, Feature64Bit,
 384                    FeatureMFTB, DeprecatedDST]>;
 385 def : ProcessorModel<"pwr5x", G5Model,
 386                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 387                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 388                    FeatureFRSQRTE, FeatureFRSQRTES,
 389                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 390                    FeatureMFTB, DeprecatedDST]>;
 391 def : ProcessorModel<"pwr6", G5Model,
 392                   [DirectivePwr6, FeatureAltivec,
 393                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 394                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 395                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 396                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 397                    FeatureMFTB, DeprecatedDST]>;
 398 def : ProcessorModel<"pwr6x", G5Model,
 399                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 400                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 401                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 402                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 403                    FeatureFPRND, Feature64Bit,
 404                    FeatureMFTB, DeprecatedDST]>;
 405 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 406 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
 407 // FIXME: Same as P8 until the POWER9 scheduling info is available
 408 def : ProcessorModel<"pwr9", P8Model, ProcessorFeatures.Power9FeatureList>;
 409 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>;
 410 def : ProcessorModel<"ppc64", G5Model,
 411                   [Directive64, FeatureAltivec,
 412                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 413                    FeatureFRSQRTE, FeatureSTFIWX,
 414                    Feature64Bit /*, Feature64BitRegs */,
 415                    FeatureMFTB]>;
 416 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
 417
 418 //===----------------------------------------------------------------------===//
 419 // Calling Conventions
 420 //===----------------------------------------------------------------------===//
 421
 422 include "PPCCallingConv.td"
 423
 424 def PPCInstrInfo : InstrInfo {
 425   let isLittleEndianEncoding = 1;
 426
 427   // FIXME: Unset this when no longer needed!
 428   let decodePositionallyEncodedOperands = 1;
 429
 430   let noNamedPositionallyEncodedOperands = 1;
 431 }
 432
 433 def PPCAsmParser : AsmParser {
 434   let ShouldEmitMatchRegisterName = 0;
 435 }
 436
 437 def PPCAsmParserVariant : AsmParserVariant {
 438   int Variant = 0;
 439
 440   // We do not use hard coded registers in asm strings.  However, some
 441   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 442   // so that those are not misinterpreted as registers.
 443   string RegisterPrefix = "%";
 444   string BreakCharacters = ".";
 445 }
 446
 447 def PPC : Target {
 448   // Information about the instructions.
 449   let InstructionSet = PPCInstrInfo;
 450
 451   let AssemblyParsers = [PPCAsmParser];
 452   let AssemblyParserVariants = [PPCAsmParserVariant];
 453 }